M68360QUADS Hardware User's Manual Revision August 1993
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M68360QUADS User's Manual
M68360QUADS Hardware User's Manual
Revision
August 1993
M68360QUADS User's Manual GENERAL INFORMATION
CHAPTER GENERAL INFORMATION
INTRODUCTION
This manual provides general information, preparation installation instructions, operating instructions, functional description, support information M68360QUADS QUICC Application Development System board.
FEATURES
main features QUADS board follows: Master QUICC MC68360 with 32-bit address, data, MHz. Mbyte Dynamic RAM, bits wide (data parity) SIMM. Kbyte boot EPROM, bits wide. Kbyte Flash Memory, bits wide. byte serial EEPROM. Application Development Interface (ADI) port connector. Serial port with RS-232 connector terminal host computer. AppleTalk serial connector. Controller capability external QUICC device. Ethernet interface (twisted-pair AUI) using Motorola MC68160. Expansion connectors providing signals master QUICC. Logic analyzer connectors compatible with logic analyzers. connector master QUICC. Slave QUICC (core disabled) providing following functions: DRAM Controller Chip Select DSACK~ generator. Parallel port (ADI). UART terminal host computer connection. AppleTalk controller MacIntosh computer connection. controller other QUICC devices. Ethernet controller. Serial EEPROM interface. General Purpose signals. HARD RESET, SOFT RESET, ABORT switches. Status LEDs RUN, HALT, Ethernet interface. 5Vdc 12Vdc power supply.
M68360QUADS User's Manual GENERAL INFORMATION
SPECIFICATIONS
M68360QUADS specifications given Table 1-1. Paragraph details cooling requirements.
Table M68360QUADS Specifications
CHARACTERISTICS Power requirements other boards attached) Microprocessor Addressing Total address range off-board) Boot EPROM Flash Memory Dynamic EEPROM Operating temperature Storage temperature Relative humidity Dimensions Height Depth Thickness SPECIFICATIONS +5Vdc (typical), (maximum) +12Vdc (maximum) MC68360 gigabytes KByte, bits wide KByte, bits wide MByte, bits wide SIMM data, parity) option higher density SIMM, MByte Byte, serial EEPROM degrees degrees ambient temperature degrees degrees (non-condensing) 9.173 inches (233 7.087 inches (180 0.063 inches (1.6
COOLING REQUIREMENTS
M68360QUADS specified, designed, tested operate reliably withan ambient temperature range from degrees degrees Dynamic Burn-in performed while board table mounted with other boards attached Test software executed board subjected temperature variations. board attached other boards, thermal conditions worse recommended that operating temperature should exceed degrees
M68360QUADS User's Manual GENERAL INFORMATION
GENERAL DESCRIPTION
M68360QUADS development tool MC68360 QUICC device. This board used hardware software development applications using QUICC device, such Ethernet interface other communication boards. M68360QUADS logic analyzer connectors expansion connectors, providing physical connection pins master QUICC board. logic analyzer connectors enablethe user monitor activity pins QUICC, providing direct connection other logic analyzers. expansion connectors enable attach user applications board, board hardware software resources check user application. M68360QUADS Ethernet LocalTalk ports, which enable user develop test software board, before integrating application.
RELATED DOCUMENTATION
following publications applicable M68360QUADS provide additional helpful information. MC68360 QUICC User's Manual. MC68160 EEST User's Manual.
ABBREVIATIONS USED DOCUMENT
QUICC QUad Integrated Communications Controller MC68360 device. EEST Enhanced Ethernet Serial Transceiver MC68160 device. QUADS Application Development System QUICC device. Application Development Interface. UART Universal Asynchronous Receiver/Transmitter. Background Debug Mode. SIMM Single In-line Memory Module. Attachment Unit Interface. Twisted Pair. spec Engineering specification document. nsec nano second. µsec micro second. Maskable Interrupt.
REQUIRED EQUIPMENT
M68360QUADS operate working environments: Host controlled Stand-alone
both operating modes, possible only power supply. power supply required only desired port when programming Flash Memory. (Most Hubs require supplies provided network termination equipment).
M68360QUADS User's Manual GENERAL INFORMATION
1.8.1
Host controlled setup
FIGURE describes setup host controlled mode operation. required equipment this mode follows: power supply power supply (optional) Host Computer, following: (SBus interface) IBM-PC/XT/AT board compatible with host computer line flat cable with female D-type connectors each
FIGURE Host Controlled Configuration
power supply
power supply
HOST COMPUTER
M68360QUADS
LINE FLAT CABLE
M68360QUADS User's Manual GENERAL INFORMATION
1.8.2
Stand alone setup
FIGURE describes setup stand-alone mode operation. required equipment this mode follows: power supply power supply (optional) VT100 compatible terminal RS-232 cable with male D-type connector QUADS side.
FIGURE Stand-alone Configuration
power supply
power supply
VT100 compatible terminal
M68360QUADS
RS-232 CABLE
M68360QUADS User's Manual HARDWARE PREPARATION INSTALLATION
CHAPTER HARDWARE PREPARATION INSTALLATION
INTRODUCTION
This chapter provides unpacking instructions, hardware preparation, installation instructions M68360QUADS.
UNPACKING INSTRUCTIONS NOTE shipping carton damaged upon receipt, request carrier's agent present during unpacking inspection equipment.
Unpack equipment from shipping carton. Refer packing list verify that items present. Save packing material storing reshipping equipment.
CAUTION AVOID TOUCHING AREAS INTEGRATED CIRCUITRY; STATIC DISCHARGE DAMAGE CIRCUITS. HARDWARE PREPARATION
select desired configuration ensure proper operation M68360QUADS board, changes Dip-Switch settings required before installation. location switches, LEDs, DipSwitches, connectors illustrated FIGURE 2-1. board been factory tested shipped with Dip-Switch settings described following paragraphs. Parameters changed following conditions: port address (Dip-Switch U46). Enable/Disable following devices QUADS (Dip-Switch U52): Slave QUICC EPROM DRAM Flash Memory Clock Generator Interrupt Generator Operation mode Master QUICC (Dip-Switch U52): Configuring A(31:28) address lines write enables. Data width, bits.
MC68360 MASTER QUICC Flash Memory DRAM SIMM Flash Memory Flash Memory +12V Dip-Switch EPROM MASTER MC68360 SLAVE QUICC Dip-Switch
Flash Memory
FIGURE M68360QUADS Location diagram
HARD RESET
M68360QUADS User's Manual HARDWARE PREPARATION INSTALLATION
SOFT RESET Ethernet Ethernet
ABORT
CONTROL from SLAVE
AppleTalk RS-232 PORT
PORT
M68360QUADS User's Manual HARDWARE PREPARATION INSTALLATION
2.3.1
Port Address Selection (Dip-Switch U46)
Each M68360QUADS have eight possible slave addresses port, enabling eight M68360QUADS boards connected same board host computer. selection slave address done setting switches Dip-Switch. Switch reserved future should 'OFF' state. Switch stands most-significant address switch stands least-significant bit. switch 'ON' state, stands logical '1'.
FIGURE Dip-Switch configuration address
Table describes switch settings each slave address:
Table Address Selection
ADDRESS Switch Switch Switch
M68360QUADS User's Manual HARDWARE PREPARATION INSTALLATION
2.3.2
QUADS Operation Mode Configuration (Dip-Switch U52)
Dip-Switch switches, which responsible configuring operation mode master QUICC M68360QUADS, they also enable devices QUADS. Table describes function each switch.
Table Dip-Switch Description
Switch Function Enable EPROM This switch connects between EPROM chip-select input master QUICC CS0~ signal. signal CS0~ used external logic connected expansion connectors, switch must disable EPROM QUADS. switch must otherwise. Enable slave QUICC This switch connects between slave QUICC MBRE~ input data signal D30. This switch factory testing QUADS, must during normal operation. Enable DRAM This switch indicates master QUICC whether initialize DRAM control registers not. switch DRAM QUADS enabled. switch OFF, DRAM disabled, memory space free user. This useful user needs connect application QUADS expansion connectors DRAM memory space application. Enable Flash Memory This switch indicates master QUICC whether initialize Flash Memory control registers not. switch Flash Memory QUADS enabled. switch OFF, Flash Memory disabled, memory space free user. This useful user needs connect application QUADS expansion connectors Flash Memory space application. A(31:28) Configuration This switch indicates CPU32bug software whether configure master QUICC A(31:28) pins address lines write enable signals. switch pins configured address lines. switch OFF, pins configured write enable signals. Enable Clock This switch enables clock generator QUADS. clock generator enabled. OFF, clock generator driver disabled, user must supply clock QUADS through pins CLK1 CLK2 expansion connectors. Enable Interrupt When this switch enables slave QUICC interrupt generator drive master QUICC interrupt input pins. switch OFF, interrupts master QUICC disabled. master QUICC internal interrupt sources affected position this switch. user application drive master QUICC interrupt pins through expansion connectors. When switch OFF, external interrupts master QUICC only generated user application. Default setting
M68360QUADS User's Manual HARDWARE PREPARATION INSTALLATION
Table Dip-Switch Description
Switch Function Data Configuration This switch connected signal MPRTY3 master QUICC. level this signal during hard reset determines data size master QUICC. switch OFF, size bits. size bits. mode, interrupt vectors from slave QUICC pass master QUICC, auto-vector function must used. Note: Power QUADS before setting this switch Default setting
M68360QUADS User's Manual HARDWARE PREPARATION INSTALLATION
INSTALLATION INSTRUCTIONS
When M68360QUADS been configured desired user, installed according required working environment follows:
2.4.1
Power Supply Connection
M68360QUADS requires max, power supply operation. QUADS fuses ground, protected against reverse connection power supply. Connect power supply connector shown below:
FIGURE P11: Power Connector
terminal block power connector with power plug. plug designed accept wires. recommended wires. insure solid ground, terminals supplied. recommended connect both wires common power supply, while connected with single wire.
NOTE Since hardware applications connected M68360QUADS using expansion connectors additional power consumption should taken into consideration when power supply connected QUADS. 2.4.2 +12V Power Supply Connection
M68360QUADS requires max, power supply Ethernet port, programming Flash Memory devices. QUADS work properly without +12V power supply, port port used with that does require provided network termination equipment, there need reprogram Flash Memory. QUADS fuses +12V ground, protected against reverse connection +12V power supply. Connect +12V power supply connector shown below:
FIGURE P12: +12V Power Connector
terminal block power connector with power plug. plug designed accept wires. recommended wires.
M68360QUADS User's Manual HARDWARE PREPARATION INSTALLATION
2.4.3 2.4.4
Installation Host computer M68360QUADS Connection
installation various host computers, refer APPENDIX page
M68360QUADS interface connector, pin, male, type connector. connection between M68360QUADS host computer line flat cable, supplied with board. FIGURE below shows configuration connector.
FIGURE Port Connector
N.C. HOST_VCC HOST_VCC HOST_VCC HOST_ENABLE~ INT_ACK N.C. HST_ACK ADS_ALL ADS_RESET ADS_SEL2 ADS_SEL1 ADS_SEL0 HOST_REQ ADS_REQ ADS_ACK ADS_INT HOST_BRK~ ADS_BRK N.C.
NOTE: connected power supply, used QUADS.
2.4.5
Terminal M68360QUADS RS-232 Connection
stand-alone operation mode, VT100 compatible terminal should connected RS-232 connector RS-232 connector pin, female, D-type connector shown FIGURE 4-3.
FIGURE RS-232 Serial Port Connector
N.C.
NOTE: line (pin connected M68360QUADS.
M68360QUADS User's Manual OPERATING INSTRUCTIONS
CHAPTER OPERATING INSTRUCTIONS
INTRODUCTION
This chapter provides necessary information M68360QUADS host-controlled stand-alone configurations. This includes controls indicators, memory details, software initialization board.
CONTROLS INDICATORS
M68360QUADS following switches indicators.
3.2.1
HARD RESET Switch
HARD RESET switch resets QUADS devices, performs hard reset QUICC devices. switch signal debounced, possible disable software. This switch must pressed along with SOFT RESET switch activate hard reset mechanism. action taken this switch pressed alone. This feature intended protect QUICC devices from accidental hard reset.
3.2.2
SOFT RESET Switch
SOFT RESET switch resets QUADS devices, performs soft reset QUICC devices. switch signal debounced, possible disable software.
3.2.3
ABORT Switch
ABORT switch normally used abort program execution return control CPU32bug. slave QUICC provides ABORT switch interface should programmed described section 3.4. ABORT switch signal debounced, enabled software, causes level interrupt master QUICC.
3.2.4 3.2.5
HALT Indicator Indicator
HALT indicator whenever master QUICC HALT~ (asserted).
green indicator connected address strobe (AS~) signal. signal (asserted) indicates activity bus.
3.2.6
Ethernet Indicator
green Ethernet Transmit indicator blinks whenever EEST transmitting data through Ethernet ports
3.2.7
Ethernet Indicator
green Ethernet Receive indicator blinks whenever EEST receiving data from Ethernet ports
3.2.8
Ethernet CLSN Indicator
Ethernet Collision indicator blinks whenever collision detected port port, jabber condition detected mode.
M68360QUADS User's Manual OPERATING INSTRUCTIONS
3.2.9
Ethernet TPLIL Indicator
yellow Ethernet Twisted Pair Link Integrity indicator lights indicate good link integrity port. when link integrity fails, when port selected.
3.2.10
Ethernet TPPLR Indicator
Ethernet Polarity indicator lights wires connected receiver input port reversed. EEST, remains when EEST automatically corrected reversed wires.
3.2.11
Ethernet TPJABB Indicator
Ethernet Jabber indicator lights whenever jabber condition detected port.
MEMORY
beginning each cycle, chip-select generators master QUICC slave QUICC determine what kind memory cycle takes place which device selected. Cycle types address spaces determined function code lines FC3-FC0. cycle types devices that respond described Table 3-1.
Table Cycle Types Responding Devices
FC3-FC0 0000 0001 0010 0011 0100 0101 0110 0111 1XXX Address Space Reserved User Data User Program Reserved Reserved Supervisor Data Supervisor Program Supervisor Responding Devices None None None MBAR registers both QUICC devices slave QUICC during interrupt acknowledge cycle.
M68360QUADS User's Manual OPERATING INSTRUCTIONS
3.3.1
Main Memory
memory devices that respond User Data, User Program, Supervisory Data, Supervisory Program, spaces shown Table 3-2.
Table M68360QUADS Main Memory
ADDESS RANGE 00000000 0001FFFF 00020000 00021FFF 00022000 00023FFF 00024000 00024001 00024002 00025FFF 00026000 00026000 00026001 00027FFF 00028000 00028000 00028001 00029FFF 00080000 000FFFFF 00400000 004FFFFF 00400000 005FFFFF 00400000 007FFFFF 00400000 00BFFFFF F0000000 FFFFFFFF Boot EPROM Master QUICC Internal Memory Slave QUICC Internal Memory M68360QUADS Status Register Status Register appears repeatedly here. Clear Status Registers This function repeated here Enable A(31:28) This function repeated here Flash Memory DRAM SIMM MCM36256 DRAM SIMM MCM36512 DRAM SIMM MCM36100 DRAM SIMM MCM36200 Slave QUICC during interrupt acknowledge cycle Accessed Device Data Size Parity NOTES
NOTES:
Refer MC68360 QUICC User's Manual complete description QUICC internal memory. device appears repeatedly multiples size. example, Status Register appears memory locations 00024000, 00024002, 00024004 etc. DRAM SIMM installed M68360QUADS MCM36256 256Kx36 bit. user replace DRAM module with higher density SIMM, increase DRAM space MByte. master QUICC read interrupt vector generated slave QUICC configured work mode. auto-vector function must used this mode. External interrupting devices connected QUADS must auto-vector function, because interrupt acknowledge address space occupied slave QUICC.
3.3.2
Address Space
master QUICC generate four types space cycles: Breakpoint Acknowledge, LPSTOP broadcast, MBAR access, Interrupt Acknowledge (IACK). Breakpoint Acknowledge cycle supported M68360QUADS. LPSTOP broadcast cycle generated because does need response from external device. slave master QUICCs respond when their MBAR accessed. IACK cycle supported M68360QUADS slave QUICC, which functions interrupt handler board responds IACK cycle.
M68360QUADS User's Manual OPERATING INSTRUCTIONS
Programming master QUICC
master QUICC internal registers must programmed after hardware reset described following paragraphs. addresses programming values hexadecimal base. Please refer MC68360 QUICC User's Manual more information.
3.4.1
Module Base Address Register
master QUICC's module base address register (MBAR) controls location internal memory registers their access space. master QUICC MBAR resides fixed location '0003FF00' space. MBAR must initialized '00020001' obtain memory described Table 3-2.
3.4.2
Module Configuration Register
controls SIM60 configuration master QUICC. BSbit must '0'. This setting will enable using asynchronous timing signals.
3.4.3
Auto Vector Register
auto vector register (AVR) contains bits that correspond external interrupt levels that require auto vector response. must initialized generate auto vectors interrupt levels These interrupts generated through slave QUICC without supplying interrupt vectors during IACK cycle.
3.4.4
Reset Status Register
reset status register (RSR) indicates source last reset that occurred, when relevant set. This register must cleared after every reset, that when next reset occurs, source easily determined. register cleared writing 'FF'.
3.4.5
CLKO Control Register
CLKO control register (CLKOCR) controls operation CLKO(0:1) pins. This register must initialized 'AB', that CLKO1 disabled CLKO2 enabled with strength output buffer.
3.4.6
Control Register
control register (PLLCR) controls operation PLL. There need program PLLCR after hard reset, because configuration MODCK(0:1) pins QUADS determines value. recommended PLLWR prevent accidental writing.
3.4.7
Port Assignment Register
Port pins programmed port assignment register (PEPAR). A(31:28) pins master QUICC programmed address lines write enable W(0:3)~ lines. PEPAR must cleared select address lines function, must select write enable function. Until this written, A(31:28) pins three-stated.
3.4.8
System Protection Control
system protection register (SYPCR) controls system monitors, software watchdog, monitor timing. This register must initialized '37' disable software watchdog, enable monitor function.
M68360QUADS User's Manual OPERATING INSTRUCTIONS
3.4.9
Global Memory Register
global memory register (GMR) contains selections memory controller master QUICC. SYNC must EMWS must cleared, obtain synchronous operation memory controller when slave QUICC active.
3.4.10
Base Register Option Register
Base register (BR0) Option register (OR0) control operation CS0~ master QUICC. Boot EPROM M68360QUADS connected this pin. must initialized '00000003', must initialized '5FFE0004' obtain memory described Table 3-2.
Programming slave QUICC
slave QUICC (core disabled) provides following functions M68360QUADS: DRAM Controller Chip Select DSACK~ generator. Parallel port (ADI). UART terminal host computer connection. AppleTalk controller MacIntosh computer connection. controller other QUICC devices. Ethernet controller. Serial EEPROM interface. General Purpose signals. slave QUICC internal registers must programmed after hardware reset described following paragraphs. addresses programming values hexadecimal base. Please refer MC68360 QUICC User's Manual more information.
3.5.1
Module Base Address Register
slave QUICC's module base address register (MBAR) controls location internal memory registers their access space. slave QUICC MBAR resides fixed location '0003FF04' space. Before accessing MBAR, software must write module base address register enable (MBARE), which resides fixed location '0003FF08' space. MBARE~ slave QUICC connected data line D30, therefore MBARE register must initialized 'BFFFFFFF' before initializing MBAR. MBAR must initialized '00022001' obtain memory described Table 3-2. Note: master QUICC data configured operate mode, MBARE must written with 'BFFF' before each word access MBAR.
3.5.2
Module Configuration Register
module configuration register (MCR) controls SIM60 configuration slave QUICC. BSbit must '0'. This setting will enable using asynchronous timing signals.
3.5.3
CLKO Control Register
CLKO control register (CLKOCR) controls operation CLKO(0:1) pins. This register must initialized 'AF', that CLKO(0:1) pins slave QUICC disabled.
3.5.4
Control Register
control register (PLLCR) controls operation PLL. There need program PLLCR after hard reset, because configuration MODCK(0:1) pins QUADS determines value. recommended PLLWR prevent accidental writing.
M68360QUADS User's Manual OPERATING INSTRUCTIONS
3.5.5
Port Assignment Register
Port pins programmed port assignment register (PEPAR). PEPAR must initialized '3760' configure Port slave QUICC follows: output slave QUICC interrupt request IOUT(0:2)~ pins. RAS1~ RAS2~ double drive function used drive DRAM. A(31:28) pins slave QUICC configured address lines. OE~/AMUX configured AMUX drive external multiplexers DRAM. CAS(0:3)~ output function used DRAM. CS7~ output function enabled.
3.5.6
System Protection Control
system protection register (SYPCR) controls system monitors, software watchdog, monitor timing. This register must initialized '37' disable software watchdog enable monitor function slave QUICC.
3.5.7
Global Memory Register
global memory register (GMR) contains selections memory controller slave QUICC. must initialized according size access time DRAM SIMM installed M68360QUADS follows: nsec DRAM type MCM36256 MCM36100, must initialized '17840380'. nsec DRAM type MCM36512 MCM36200, must initialized '0A840380'. nsec DRAM type MCM36256 MCM36100, must initialized '17A40380'. nsec DRAM type MCM36512 MCM36200, must initialized '0AA40380'. nsec DRAM type MCM36256 MCM36100, must initialized '17A44380'. nsec DRAM type MCM36512 MCM36200, must initialized '0AA44380'. defines following parameters: DRAM refresh period 15.36 µsec. DRAM refresh cycle length depends DRAM access time, either clocks clocks long. DRAM module port size bits. parity disabled. CS~/RAS~ lines slave QUICC will assert when accessing space. Internal address multiplexing DRAM disabled.
3.5.8
Base Register Option Register
Base register (BR0) Option register (OR0) control operation CS0~ slave QUICC. This connection M68360QUADS, CS0~ CS7~ used distinguish between accesses board internal resources external devices that attached board. must initialized '00000003', must initialized 'FFFE0006', proper operation board.
M68360QUADS User's Manual OPERATING INSTRUCTIONS
3.5.9
Base Register Option Register
Base register (BR1) Option register (OR1) control operation RAS1~ slave QUICC. This connected DRAM module. These registers must initialized according type DRAM SIMM installed M68360QUADS follows: must initialized '2FF00009' nsec nsec DRAM, types MCM36256 MCM36512. must initialized '3FF00009' nsec DRAM, types MCM36256 MCM36512. must initialized '2FC00009' nsec nsec DRAM, type MCM36100 MCM36200. must initialized '3FC00009' nsec DRAM, type MCM36100 MCM36200. must initialized '00400005', disregarding type access time DRAM. Note: CPU32bug software does access after reset Enable DRAM switch 'OFF' position. software must perform accesses RAS1~ address space after initialization proper operation DRAM.
3.5.10
Base Register Option Register
Base register (BR2) Option register (OR2) control operation RAS2~ slave QUICC. This connected DRAM module. These registers must initialized type DRAM SIMM installed M68360QUADS MCM36512 MCM36200, because these types contain DRAM banks, RAS1~ connected both banks. DRAM SIMM type MCM36512, must initialized '00500005'. must initialized '2FF00009' nsec nsec DRAM, '3FF00009' nsec DRAM. DRAM SIMM type MCM36200, must initialized '00800005'. must initialized '2FC00009' nsec nsec DRAM, '3FC00009' nsec DRAM. Note: CPU32bug software does access after reset Enable DRAM switch 'OFF' position. software must perform accesses RAS2~ address space after initialization proper operation DRAM.
3.5.11
Base Register Option Register
Base register (BR3) Option register (OR3) control operation CS3~ slave QUICC. Flash Memory M68360QUADS connected this pin. must initialized '00080009', must initialized '3FF80000' obtain memory described Table 3-2. Note: CPU32bug software does access after reset Enable Flash Memory switch 'OFF' position.
3.5.12
Base Register Option Register
Base register (BR4) Option register (OR4) control operation CS4~ slave QUICC. M68360QUADS Status Register connected this pin. must initialized '00024003', must initialized '0FFFE002' obtain memory described Table 3-2.
3.5.13
Base Register Option Register
Base register (BR5) Option register (OR5) control operation CS5~ slave QUICC. M68360QUADS Abort Register that Abort switch Host Register that host computer connected port. Setting either register generates level interrupt master QUICC. CS5~ signal used M68360QUADS interrupt handling routine clear these registers. must initialized '00026001', must initialized '0FFFE004' obtain memory described Table 3-2.
M68360QUADS User's Manual OPERATING INSTRUCTIONS
3.5.14
Base Register Option Register
Base register (BR6) Option register (OR6) control operation CS6~ slave QUICC. A(31:28) pins master QUICC configured address lines write enable lines. After hard reset, these lines three-state condition until PEPAR master QUICC written. A(31:28) Configuration switch 'ON', CPU32bug software initializes PEPAR master QUICC, asserts CS6~ signal enable using A(31:28) address lines board. must initialized '00028001', must initialized '0FFFE004' obtain memory described Table 3-2. Note: A(31:28) pins used write enable lines, CS6~ must never asserted. recommended initialize '00028000' avoid accidental accesses address space CS6~.
3.5.15
Base Register Option Register
Base register (BR7) Option register (OR7) control operation CS7~ slave QUICC. CS0~ CS7~ used distinguish between accesses board internal resources external devices that attached board. proper operation board, must initialized '00000001', must initialized 'F0000006'.
3.5.16
Port Open Drain Register
Port slave QUICC pins port, each configured general purpose dedicated peripheral interface pin. port open drain register (PAODR) configures drivers port pins open-drain active drivers. PAODR must initialized '0000' select active drivers configuration.
3.5.17
Port Data Register
Port data register (PADAT) read check data pin. port configured general purpose output pin, value PADAT that driven onto pin. recommended initialize PADAT 'FFFF' before configuring other port registers.
3.5.18
Port Data Direction Register
port data direction register (PADIR) different functions according configuration port pins. general purpose pin, value PADIR that defines direction pin. dedicated peripheral interface pin, value PADIR that select dedicated functions pin. PADIR must initialized '3C00'.
3.5.19
Port Assignment Register
port assignment register (PAPAR) configures function port pins. value PAPAR general purpose I/O, otherwise dedicated peripheral interface pin. PAPAR must initialized '033F'.
3.5.20
Port Open Drain Register
Port slave QUICC pins port, each configured general purpose dedicated peripheral interface pin. port open drain register (PBODR) configures drivers port pins open-drain active drivers. PBODR must initialized '0000' select active drivers configuration.
3.5.21
Port Data Register
Port data register (PBDAT) read check data pin. port configured general purpose output pin, value PBDAT that driven onto pin. recommended initialize PBDAT '3FFFF' before configuring other port registers.
M68360QUADS User's Manual OPERATING INSTRUCTIONS
3.5.22
Port Data Direction Register
port data direction register (PBDIR) different functions according configuration port pins. general purpose pin, value PBDIR that defines direction pin. dedicated peripheral interface pin, value PBDIR that select dedicated functions pin. PBDIR must initialized '0007F'. Pins connected port data bus, therefore their direction must changed software according data flow.
3.5.23
Port Assignment Register
port assignment register (PBPAR) configures function port pins. value PBPAR general purpose I/O, otherwise dedicated peripheral interface pin. PBPAR must initialized '0000E'.
3.5.24
Port Data Register
Port slave QUICC port, each configured general purpose dedicated peripheral interface pin, with interrupt capability. Port data register (PCDAT) read check data pin. port configured general purpose output pin, value PCDAT that driven onto pin. recommended initialize PCDAT '0740' before configuring other port registers.
3.5.25
Port Data Direction Register
port data direction register (PCDIR) different functions according configuration port pins. general purpose pin, value PCDIR that defines direction pin. dedicated peripheral interface pin, value PCDIR that select three dedicated functions pin. PCDIR must initialized '0F8C'.
3.5.26
Port Assignment Register
port assignment register (PCPAR) configures function port pins, along with PCDIR PCSO. PCPAR must initialized '0003'.
3.5.27
Port Special Options Register
port special options register (PCSO) configures CTSx pins. Port detect changes lines, assert corresponding interrupt while simultaneously uses those lines. PCSO must initialized '0030'.
M68360QUADS User's Manual FUNCTIONAL DESCRIPTION
CHAPTER FUNCTIONAL DESCRIPTION
INTRODUCTION
This chapter details hardware design M68360QUADS, describes each module.
Master QUICC
master QUICC device, sheet main processor QUADS. working frequency QUICC Mhz, user change frequency replacing oscillator sheet frequency oscillator twice working frequency board. master QUICC configured operate either mode mode, according level MPRTY3 signal during hard reset. user drive this signal mode) either selecting this mode Dip-Switch (Sheet 14), driving through expansion connector (Sheet 21). mode, data transceivers (Sheet data controller (Sheet control data flow between data master QUICC devices QUADS, directing data proper lines. There restriction software that support both operating modes, provided that uses auto-vector function master QUICC. slave QUICC interrupts master QUICC, master read interrupt vector only mode. When programming MBAR register slave QUICC, must access transfers, must write MBARE register before each access. This restriction design QUICC, which requires writing MBARE register before accessing MBAR register, therefore when QUICC operates mode, access MBAR transfers. pins master QUICC device available unbuffered user through expansion connectors (Sheets 21), logic analyzer connectors (Sheets 19). user monitor QUICC activity connect QUADS hardware application during development stage. logic analyzer connectors connected directly logic analyzers. master QUICC pins buffered from devices QUADS, minimize their load enable easy connection user hardware application. pins master QUICC also available user through connector (Sheet 16). This connector used download code monitor functions.
Boot EPROM
boot EPROM 27C010 device sheet (200 nsec access time, 128K bit) used store debug boot programs. EPROM accessed device, using Global port master QUICC. possible user disable accesses EPROM QUADS, Global port access EPROM application board after reset. This done setting Enable EPROM switch 'OFF', thus disconnecting M_CS0~ signal from E_CS~ signal.
M68360QUADS User's Manual FUNCTIONAL DESCRIPTION
FIGURE HARDWARE BLOCK DIAGRAM
Connector QUICC (master)
Logic Analyzer Connectors
Expansion Connectors
KByte Boot EPROM bits wide) Transceivers Controller Local Arbiter
Status Register Byte Serial EEPROM
KByte Flash Memory bits wide)
QUICC (slave)
MByte DRAM with parity bits wide SIMM)
MC68160 EEST
Controller Port
Port
RS-232 Port
AppleTalk Port
Ethernet Port RJ-45 Connector
Ethernet Port Connector
Flash Memory
Four Flash Memory devices, 28F010 (128 KByte, nsec access time) used form Kbyte program storage memory. devices, sheet organized long-word bits wide). Flash Memory devices soldered board, program code updates will done board without need external EPROM programmer. programming software stored boot EPROM, which loads code through QUADS ports, erases Flash Memory, programs code.
M68360QUADS User's Manual FUNCTIONAL DESCRIPTION slave QUICC device provides F_CS~ signal Flash Memory. user must connect external power supply connector program devices. user indicate CPU32bug software initialize registers slave QUICC setting Enable Flash Memory switch OFF. This setting used disable accesses Flash Memory after hard reset, address space used user.
EEPROM
EEPROM used QUADS Motorola MCM2814 byte serial EEPROM (U33 sheet slave QUICC port (port pins used control accesses EEPROM. MCM2814 internal hardware protection against inadvertent writes EEPROM that might happen power power down time.
DRAM
QUADS supplied with Mbyte Dynamic RAM, which implemented MCM36256S80 DRAM module. module, sheet lead SIMM, nsec access time, organized 256K data parity signals. possible replace supplied DRAM SIMM with higher density module, order increase DRAM memory space Mbyte. higher density modules, such MCM36200, require using RAS1 RAS2 signals slave QUICC, because they organized memory banks. These signals supplied DRAM socket QUADS, that user does need wiring. SIMM four presence detect signals, SIMM1 SIMM4, which read software through Status Register (U61 sheet 14). CPU32bug software determines DRAM memory space access time according these signals, described Table 4-1.
Table DRAM SIMM Types
SIMM(4:1) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 SIMM Type MCM36100S10 MCM36512S10 MCM36256S10 MCM36200S10 MCM36100S80 MCM36512S80 MCM36256S80 MCM36200S80 MCM36100S70 MCM36512S70 MCM36256S70 MCM36200S70 Valid Valid Valid Valid SIMM Organization 512K 256K 512K 256K 512K 256K Access Time (nsec) Control Signals RAS1 RAS1, RAS2 RAS1 RAS1, RAS2 RAS1 RAS1, RAS2 RAS1 RAS1, RAS2 RAS1 RAS1, RAS2 RAS1 RAS1, RAS2
M68360QUADS User's Manual FUNCTIONAL DESCRIPTION DRAM controlled slave QUICC device, using DRAM Controller function normal accesses, page mode accesses, refresh accesses. DRAM accessed master QUICC, slave QUICC (the IDMA SDMA disabled), external master connected expansion connectors QUADS. user indicate CPU32bug software initialize BR1, OR1, BR2, registers slave QUICC setting Enable DRAM switch OFF. This setting used disable accesses DRAM after hard reset, address space used user. Note: CPU32bug software requires KByte space located address 00400000. DRAM disabled, user must connect external QUADS software properly.
Slave QUICC
During normal operation, slave QUICC sheet disabled, device used implement following functions QUADS: DRAM Controller Chip Select DSACK~ generator. Parallel port (ADI). UART terminal host computer connection. AppleTalk controller MacIntosh computer connection. controller other QUICC devices. Ethernet controller. Serial EEPROM interface. General Purpose signals. address MBAR register configured $0033FF04. master QUICC must write MBARE register address $0033FF08 before each access slave MBAR register. slave QUICC essential make master QUICC pins available user implementations. QUICC peripherals (such IDMA SDMA) request become master, while disabled.
4.7.1
DRAM Controller
slave QUICC device provides necessary control signals DRAM module. software QUADS reads presence detect pins SIMM, sets DRAM Controller parameters according DRAM module, access time DRAM. hardware connection slave QUICC DRAM module straight forward. External address multiplexers (U67, U62, sheet used drive DRAM address lines, enable external masters access DRAM. CPU32bug software programs PEPAR that OE~/AMUX slave QUICC configured AMUX drive address multiplexers. RAS1~ RAS2~ pins slave QUICC drive DRAM SIMM. double-drive signals RAS1DD~ RAS2DD~ also drive DRAM decrease signal load.
4.7.2
Chip Select DSACK~ generator
slave QUICC device provides Chip Select signals QUADS devices follows: CS0~ slave QUICC connected device QUADS, function used along with CS7~ control logic distinguish between accesses board devices external devices that attached board. CS1~ CS2~ connected DRAM SIMM, they RAS1~ RAS2~. CS3~ connected Flash Memory (U72, U73, U74, sheet
M68360QUADS User's Manual FUNCTIONAL DESCRIPTION CS4~ connected M68360QUADS Status Register (U61 sheet 14). CS5~ connected Abort Host registers, sheet sheet This signal used clear these registers after interrupt level CS6~ connected Enable Address register, sheet This signal used enable using A(31:28) lines master QUICC address lines QUADS. CS7~ connected Controller, sheet this signal negated, indicates that current access device QUADS. DSACK~ generator disabled this signal.
4.7.3
Port (Sheet
parallel port supplies parallel link from QUADS various host computers. This port connected line cable special board called (Application Development Interface) installed host computer. possible connect QUADS board IBM-PC/XT/AT SUN-4 SPARC station, provided that they have board with appropriate software drivers installed them. Each QUADS have possible slave addresses port, enabling QUADS boards connected same board. QUADS address selected sheet port connector pin, male, type connector. connection between QUADS host computer line flat cable, supplied with board. FIGURE below shows configuration connector.
FIGURE Port Connector
N.C. HOST_VCC HOST_VCC HOST_VCC HOST_ENABLE~ INT_ACK N.C. HST_ACK ADS_ALL ADS_RESET ADS_SEL2 ADS_SEL1 ADS_SEL0 HOST_REQ ADS_REQ ADS_ACK ADS_INT HOST_BRK~ ADS_BRK N.C.
NOTE: connected power supply, used QUADS.
M68360QUADS User's Manual FUNCTIONAL DESCRIPTION
4.7.3.1
Port Signal Description
port M68360QUADS slightly modified generate either hard reset soft reset. This feature added comply with QUICC reset mechanism. host software written M68360QUADS should able work properly with existing QUADS boards, such M68302ADS. list below, directions 'I', 'O', 'I/O' relative QUADS board. (I.E. means input QUADS) ADS_SEL(0:2) These three input lines determine slave address QUADS being accessed host computer. boards addressed board. ADS_ALL This input line used reset abort program execution QUADS development boards that connected same board. HOST_ENABLE~ This line always driven board. QUADS software uses this line determine host connected port. ADS_BRK When host connected, this line used conjunction with addressing lines with ADS_ALL line generate non-maskable interrupt (interrupt level QUICC. ADS_RESET When host connected, this line used conjunction with addressing lines with ADS_ALL line reset QUADS board. type reset, hard soft, determined INT_ACK signal. HOST_REQ This signal initiates host QUADS write cycle. ADS_ACK This signal QUADS response HOST_REQ signal, indicating that QUADS board detected assertion HOST_REQ. ADS_REQ This signal initiates QUADS host write cycle. HST_ACK This signal serves host's response ADS_REQ signal. HOST_BRK~ This open-collector signal generates interrupt host. This signal common QUADS boards that connected same ADI. ADS_INT This line polled host computer during interrupt acknowledge cycle determine which QUADS board generated interrupt. INT_ACK This line asserted host interrupt acknowledge cycle. This signal used QUADS hardware negate HOST_BRK~ signal. software QUADS must negate ADS_INT signal upon detecting assertion INT_ACK support daisy-chain interrupt structure. This line also used host generate either hard reset soft reset. this case, this line used conjunction with ADS_RESET, with either addressing lines with ADS_ALL line.
M68360QUADS User's Manual FUNCTIONAL DESCRIPTION HOST_VCC (three lines) These lines power lines from host computer. QUADS, these lines used software determine host computer powered QUADS does these lines power supply. PD(0:7) 'I/O' These eight lines parallel data bus. This used transmit receive data from host computer.
4.7.4
RS-232 Serial Port (Sheet
serial port provided slave QUICC SCC3 serial channel. M68360QUADS connected VT100 compatible terminal host computer through serial port. RS-232 serial port connector pin, female, D-type connector shown FIGURE 4-3.
FIGURE RS-232 Serial Port Connector
N.C.
4.7.4.1
RS-232 Port Signal Description
list below, directions 'I', 'O', 'I/O' relative QUADS board. (I.E. means input QUADS) Data Carrier Detect. This line always asserted QUADS. Transmit Data. Receive Data. Data Terminal Ready. This signal used software QUADS detect terminal connected QUADS board. Data Ready. This line always asserted QUADS. Request Send. This line connected QUADS. Clear Send. This line always asserted QUADS.
4.7.5
AppleTalk Port (Sheet
AppleTalk port provided slave QUICC SCC2 serial channel. AppleTalk 230.4 kbps local area network that connects multiple MacIntosh computers printers. AppleTalk port connector pin, MINI JACK connector shown FIGURE 4-4.
FIGURE AppleTalk Connector
N.C. HSKI
M68360QUADS User's Manual FUNCTIONAL DESCRIPTION
4.7.5.1
AppleTalk Port Signal Description
list below, directions 'I', 'O', 'I/O' relative QUADS board. (I.E. means input QUADS) output from QUADS through resistor. HSKI Hand Shake Input. Transmit Data (negative). Receive Data (negative). Transmit Data (positive). Receive Data (positive).
4.7.6
Controller (Sheet
slave QUICC enables M68360QUADS become controller control other QUICC devices user application. feature enables user download code provides hardware software debugging capability user application. connector utilizes five pins slave QUICC port These pins configured general purpose pins.
4.7.7
Ethernet Controller (Sheet
slave QUICC provides Ethernet port M68360QUADS connecting SCC1 Motorola MC68160 EEST device (U35 sheet 10). MC68160 provides Ethernet interfaces, twisted-pair LEDs LD3-LD8 controlled EEST, they provide indications about status Ethernet ports activity. signals between slave QUICC MC68160 appear connector debugging purposes. wire holes. socket installed internal factory testing only. proper operation EEST, this socket must empty.
4.7.7.1
Ethernet Port Signal Description FIGURE Ethernet Port Connector
ACX+ ATX+ ACX10 ATX11 ARX+12V N.C.
port connector pin, female, D-type connector shown FIGURE 4-3.
ARX+ N.C.
M68360QUADS User's Manual FUNCTIONAL DESCRIPTION list below describes port signals. directions 'I', 'O', 'I/O' relative QUADS board. (I.E. means input QUADS) ACX+ Collision Input (positive). ATX+ Transmit Data (positive). ARX+ Receive Data (positive). ACX- Collision Input (negative). ATX- Transmit Data (negative). ARX- Receive Data (negative). +12V +12V power supply from QUADS.
4.7.7.2
Ethernet Twisted-Pair Port Signal Description FIGURE Ethernet Twisted-Pair Port Connector
TPTX+ TPTXTPRX+ N.C. N.C. TPRXN.C. N.C.
twisted-pair port connector pin, RJ-45 connector shown FIGURE 4-3.
list below describes port signals. directions 'I', 'O', 'I/O' relative QUADS board. (I.E. means input QUADS) TPTX+ Transmit Data (positive). TPTX- Transmit Data (negative). TPRX+ Receive Data (positive). TPRX- Receive Data (negative).
4.7.8
Serial EEPROM Interface (Sheet
MCM2814 serial EEPROM (U33 sheet bytes EEPROM with interface. controlled port slave QUICC (pins port general purpose output (pin port port operates master mode.
4.7.9
Slave QUICC General Purpose Pins
slave QUICC three ports, whose pins individually configured software general purpose dedicated peripheral function. QUICC also another port, whose pins general purpose I/O, they configured operate possible modes. following subsections describe slave QUICC ports. Refer section page required programming information.
M68360QUADS User's Manual FUNCTIONAL DESCRIPTION
4.7.9.1
Slave QUICC Port
Port pins port. Table describes configuration port
Table Port Pins Description
Name Ethernet Ethernet AppleTalk AppleTalk RS-232 RS-232 Enable DRAM Description This connected receive data output EEST. configured receive data SCC1 slave QUICC. This connected transmit data input EEST. configured transmit data SCC1 slave QUICC. This connected receive data output AppleTalk transceiver U29. configured receive data SCC2 slave QUICC. This connected transmit data input AppleTalk transceiver U29. configured transmit data SCC2 slave QUICC. This connected receive data output RS-232 transceiver U23. configured receive data SCC3 slave QUICC. This connected transmit data input RS-232 transceiver U23. configured transmit data SCC3 slave QUICC. This connected switch dip-switch U52. configured input slave QUICC, level indicates CPU32bug software should enable accesses DRAM QUADS. level '0', DRAM enabled. This connected switch dip-switch U52. configured input slave QUICC, level indicates CPU32bug software should enable accesses Flash Memory QUADS. '0', Flash enabled. This connected transmit clock output EEST. configured transmit clock SCC1 slave QUICC. This connected receive clock output EEST. configured receive clock SCC1 slave QUICC. This connected port logic. configured output slave QUICC, used logic control data transceiver. This connected port signal ADS_INT through buffer U16. configured output slave QUICC, also used logic interrupt host computer. This connected port signal ADS_ACK through buffer U16. configured output slave QUICC. This connected port signal ADS_REQ through buffer U16. configured output slave QUICC. This configured input pin, used sense +12V power supply. '1', +12V applied QUADS. This connected switch dip-switch U46, configured input slave QUICC. function ADS, reserved future applications.
Enable Flash
Ethernet TCLK Ethernet RCLK INT~
ACK~ REQ~ Spare
M68360QUADS User's Manual FUNCTIONAL DESCRIPTION
4.7.9.2
Slave QUICC Port
Port pins port. Table describes configuration port
Table Port Pins Description
Freeze Data Data Data Data Data Data Data Data Name EEPROM Select EEPROM EEPROM Serial EEPROM Serial Reset Data Data Description This connected select input EEPROM, configured output slave QUICC. This connected clock input EEPROM, configured clock slave QUICC. This connected serial data input EEPROM, configured MOSI slave QUICC. This connected serial data output EEPROM, configured MISO slave QUICC. This connected Controller connector configured output slave QUICC. This connected Controller connector configured output slave QUICC. This connected Controller connector configured output slave QUICC. This connected Controller connector configured input slave QUICC. This connected QUADS board. This connected Controller connector configured input slave QUICC. This connected port signal through data transceiver configured pin. This connected port signal through data transceiver configured pin. This connected port signal through data transceiver configured pin. This connected port signal through data transceiver configured pin. This connected port signal through data transceiver configured pin. This connected port signal through data transceiver configured pin. This connected port signal through data transceiver configured pin. This connected port signal through data transceiver configured pin.
M68360QUADS User's Manual FUNCTIONAL DESCRIPTION
4.7.9.3
Slave QUICC Port
Port pins port. Table describes configuration port
Table Port Pins Description
Name TENA AppleTalk Enable EEST Description This connected TENA input EEST. configured signal SCC1 slave QUICC. This connected enable input AppleTalk transceiver U29. configured signal SCC2 slave QUICC. this '0', transceiver output AppleTalk port enabled. This connected input EEST, configured output slave QUICC. this '1', EEST operates standby mode, '0', EEST normal operation mode. This connected TPEN EEST, configured slave QUICC. TPEN (Twisted-Pair Port Enable) EEST determines which port selected operate, This connected CLSN output EEST. configured signal SCC1 slave QUICC. This connected RENA output EEST. configured signal SCC1 slave QUICC. This connected HSKI signal AppleTalk port through transceiver U29. configured signal SCC2 slave QUICC. This connected APORT input EEST, configured output slave QUICC. this '1', EEST automatically select port based receive input. '0', TPEN selects operating port. This connected TPAPCE input EEST, configured output slave QUICC. this '1', automatic polarity correction enabled port. This connected TPSQEL input EEST, configured output slave QUICC. this '0', enables testing EEST internal collision detect circuitry. This connected TPFULDL input EEST, configured output slave QUICC. this '0', allows simultaneous transmit receive operation port without indicated collision. This connected LOOP input EEST, configured output slave QUICC. This enables diagnostic loopback EEST.
TPEN
CLSN RENA HSKI APORT
TPAPCE
TPSQEL
TPFULDL
LOOP
M68360QUADS User's Manual FUNCTIONAL DESCRIPTION
4.7.9.4
Slave QUICC Port
Port pins configured operate dedicated peripheral functions. PEPAR register configures operation mode, described section 3.5.5 page
LOCAL ARBITER (Sheet
local master following: master QUICC. External Master connected QUADS through expansion connectors. slave QUICC peripherals (One channels, DRAM refresh, etc.). master QUICC local master during normal operation. Local Arbiter, sheet PAL16R4 device that uses master QUICC arbitration logic transfer mastership other masters. M68360QUADS provision user connect External Master device local through Expansion Connectors relevant control signals (EXTBR~, EXTBG~, BGACK~) appear connector arbitration priority from highest lowest slave QUICC, External Master, master QUICC. Arbiter output signal A_DIR controls direction address transceivers (U7, U28, U14, sheet between master QUICC other devices QUADS. also generates output signal A28_31, which used data controller determine direction data transceivers.
DATA CONTROLLER (Sheet
data parity transceivers (U20,U15, U32, U12, U25, U13, U11, U18, sheet controlled GAL22V10 device, sheet also generates Byte Enable signals according accessed address data size. signals CS7~ slave QUICC A28_31 used indicate current access devices QUADS. CS7~ signal programmed address range 00000000 0FFFFFFF hexadecimal, with DSACK generator disabled. signal CS0~ slave QUICC programmed cover address range Boot EPROM, that CS7~ asserted EPROM accessed. CS7~ asserted none slave QUICC chip-select signals asserted, CS7~ asserted (low), this indicates that accessed device QUADS board. A28_31 signal high upper four address bits high, external EPROM accessed instead M68360QUADS Boot EPROM. A28_31 high, indicates that accessed device QUADS board. GAL22V10 device also control data swapping master QUICC configured operate bits mode.
4.10
Status Register (Sheet
M68360QUADS Status Register consists 74LS373 devices (U61 sheet that form read-only device. register controlled CS4~ slave QUICC.
M68360QUADS User's Manual FUNCTIONAL DESCRIPTION Status Register bits described Table below:
Table Status Register Description
Description Data Configuration This indicates operation mode master QUICC data bus. '1', data mode. '0', data mode. Interrupt Enable This indicates interrupts from QUADS devices master QUICC enabled. this '0', master QUICC interrupted QUADS resources, such ABORT switch slave QUICC peripherals. Clock Source This indicates source clock QUADS. '1', clock supplied QUADS through expansion connector '0', clock supplied QUADS clock generator. A(31:28) Pins Configuration These bits indicates CPU32bug software required configuration master QUICC A(31:28) pins. '1', pins configured write enable signals. '0', pins configured address lines. SIMM1 This connected DRAM SIMM presence detect signals. Refer Table complete description available DRAM types, their SIMM(4:1) codes. SIMM2 This connected DRAM SIMM presence detect signals. Refer Table complete description available DRAM types, their SIMM(4:1) codes. SIMM3 This connected DRAM SIMM presence detect signals. Refer Table complete description available DRAM types, their SIMM(4:1) codes. SIMM4 This connected DRAM SIMM presence detect signals. Refer Table complete description available DRAM types, their SIMM(4:1) codes. Host This connected port. '0', indicates that host computer powered Host Enable This connected port. '1', indicates that port connected host computer. Host This connected port. '0', indicates that host responded signal. Host This connected port. '0', indicates that host requesting write QUADS. Select This connected port. '1', indicates that host computer selected QUADS current data transfer. Interrupt This connected port. '0', indicates that host responded interrupt signal from QUADS. Host This connected port. '0', indicates that host generated level interrupt QUADS. DTR~ Data Terminal Ready indication. This indicates terminal connected RS-232 Serial Port.
M68360QUADS User's Manual FUNCTIONAL DESCRIPTION
4.11
Interrupt Logic
slave QUICC configured CPU32bug software assert interrupt requests IOUT(2:0)~ pins. 74F538 decoder (U70 sheet accepts IOUT signals decodes them select master QUICC IRQ(7:1)~ signals. signals master QUICC driven open-collector devices, that user application connected expansion connectors assert them along with interrupt logic QUADS board. possible disable from driving signals, that master QUICC only interrupted internal peripherals user application. This done setting Enable Interrupt switch 'OFF'.
FIGURE Interrupt Logic Configuration
ABORT Switch Host Port Activity IRQ7~ IRQ2~ slave QUICC IOUT(2:0)~ 74F538 Decoder Enable Interrupt Dip-Switch Expansion Connectors 74LS05 Open-Collector Device IRQ(7:1)~ master QUICC
slave QUICC accepts interrupts from ABORT switch, Host register, port logic. These interrupt sources encoded slave QUICC, along with interrupts from internal peripherals, highest interrupt level driven IOUT(2:0)~ pins. slave QUICC supply interrupt vector during interrupt acknowledge cycle internal interrupts, that external interrupts. Therefore, master QUICC must programmed provide auto-vector interrupts levels QUADS configured operate mode, master QUICC read interrupt vector generated slave QUICC during interrupt acknowledge cycles. this case auto-vector function must used. external interrupting device connected QUADS, auto-vector function must used handle interrupts. This because interrupt acknowledge address space occupied slave QUICC, external interrupter drive data during interrupt acknowledge cycles.
4.12
Disable Logic Slave QUICC (Sheet
slave QUICC must configured work with disabled, global disabled, MBAR reside address 3FF04. this, encoding configuration pins CONFIG(2:0) must enable more than clocks during hard reset, then they must encoded '110' before hard reset signal negated (high level). CONFIG2 CONFIG1 pins connected pull-up resistors QUADS. CONFIG0 driven PAL22V10-25 device, sheet during hard reset. drives CONFIG0 high level clock cycles after hard reset signal asserted. This makes encoding CONFIG(2:0) pins equals '111' which enables CPU. After clocks, CONFIG0 driven long hard reset signal asserted.
M68360QUADS User's Manual FUNCTIONAL DESCRIPTION When hard reset signal negated, slave QUICC disabled, stops driving CONFIG0 pin.
M68360QUADS User's Manual SUPPORT INFORMATION
CHAPTER SUPPORT INFORMATION
INTRODUCTION
This chapter provides interconnection signals, parts list, schematic diagrams M68360QUADS board.
INTERCONNECT SIGNALS
M68360QUADS board interconnects with external devices through following connectors: five pin, male connectors, compatible with logic analyzer connectors, that provides signals master QUICC monitoring. pin, male, logic analyzer connector providing remaining signals master QUICC. pin, female, expansion connectors providing signals master QUICC connection user hardware application. male connector connected pins master QUICC. pin, male type connector, port. pin, female type connector, RS-232 port. pin, MINI JACK connector, AppleTalk port. pin, female type connector, connection Ethernet port. pin, RJ-45 connector, twisted-pair connection Ethernet port. male connector. controller connector that enables QUADS control activity external QUICC mounted user application board. wire holes board. signals between slave QUICC EEST appear internal factory debugging purposes. connector power supply input: (x2) connector power supply input: +12V
5.2.1
Connector Interconnect Signals
Connector double-row, pin, male connector. lower address lines master QUICC appear this connector easy monitoring logic analyzer. Table describes connector signals.
Table Connector Interconnect Signals
Signal Name CLK1 Description connected connected operating clock M68360QUADS, MHz. Address line master QUICC (unbuffered). Address line master QUICC (unbuffered). Address line master QUICC (unbuffered). Address line master QUICC (unbuffered). Address line master QUICC (unbuffered). Address line master QUICC (unbuffered).
M68360QUADS User's Manual SUPPORT INFORMATION
Table Connector Interconnect Signals
Signal Name Description Address line master QUICC (unbuffered). Address line master QUICC (unbuffered). Address line master QUICC (unbuffered). Address line master QUICC (unbuffered). Address line master QUICC (unbuffered). Address line master QUICC (unbuffered). Address line master QUICC (unbuffered). Address line master QUICC (unbuffered). Address line master QUICC (unbuffered). Address line master QUICC (unbuffered). Ground signal M68360QUADS.
5.2.2
Connector Interconnect Signals
Connector double-row, pin, male connector. higher address lines master QUICC appear this connector easy monitoring logic analyzer. Table describes connector signals.
Table Connector Interconnect Signals
Signal Name DSACK0~ Description connected connected DSACK0~ line master QUICC. Address line master QUICC (unbuffered). Address line master QUICC (unbuffered). Address line master QUICC (unbuffered). Address line master QUICC (unbuffered). Address line master QUICC (unbuffered). Address line master QUICC (unbuffered). Address line master QUICC (unbuffered). Address line master QUICC (unbuffered). Address line master QUICC (unbuffered). Address line master QUICC (unbuffered). Address line master QUICC (unbuffered). Address line master QUICC (unbuffered). Address line master QUICC (unbuffered). Address line master QUICC (unbuffered). Address line master QUICC (unbuffered). Address line master QUICC (unbuffered). Ground signal M68360QUADS.
M68360QUADS User's Manual SUPPORT INFORMATION
5.2.3
Connector Interconnect Signals
Connector double-row, pin, male connector. lower data lines master QUICC appear this connector easy monitoring logic analyzer. Table describes connector signals.
Table Connector Interconnect Signals
Signal Name DSACK1~ Description connected connected DSACK1~ line master QUICC. Data line master QUICC (unbuffered). Data line master QUICC (unbuffered). Data line master QUICC (unbuffered). Data line master QUICC (unbuffered). Data line master QUICC (unbuffered). Data line master QUICC (unbuffered). Data line master QUICC (unbuffered). Data line master QUICC (unbuffered). Data line master QUICC (unbuffered). Data line master QUICC (unbuffered). Data line master QUICC (unbuffered). Data line master QUICC (unbuffered). Data line master QUICC (unbuffered). Data line master QUICC (unbuffered). Data line master QUICC (unbuffered). Data line master QUICC (unbuffered). Ground signal M68360QUADS.
5.2.4
Connector Interconnect Signals
Connector double-row, pin, male connector. higher data lines master QUICC appear this connector easy monitoring logic analyzer. Table describes connector signals.
Table Connector Interconnect Signals
Signal Name Description connected connected Data Strobe line master QUICC. Data line master QUICC (unbuffered). Data line master QUICC (unbuffered). Data line master QUICC (unbuffered). Data line master QUICC (unbuffered). Data line master QUICC (unbuffered).
M68360QUADS User's Manual SUPPORT INFORMATION
Table Connector Interconnect Signals
Signal Name Description Data line master QUICC (unbuffered). Data line master QUICC (unbuffered). Data line master QUICC (unbuffered). Data line master QUICC (unbuffered). Data line master QUICC (unbuffered). Data line master QUICC (unbuffered). Data line master QUICC (unbuffered). Data line master QUICC (unbuffered). Data line master QUICC (unbuffered). Data line master QUICC (unbuffered). Data line master QUICC (unbuffered). Ground signal M68360QUADS.
5.2.5
Connector Interconnect Signals
Connector double-row, pin, male connector. master QUICC control signals appear this connector easy monitoring logic analyzer. Table describes connector signals.
Table Connector Interconnect Signals
Signal Name BERR~ PERR~ IFETCH~ IPIPE0~ IPIPE1~ FREEZE DSACK1~ DSACK0~ SIZ1 SIZ0 R/W~ BGACK~ Description connected connected Address Strobe Error Parity Error Instruction Fetch Instruction Pipe Instruction Pipe Freeze Function Code Data Size Acknowledge Data Size Acknowledge Function Code Function Code Function Code Transfer Size Transfer Size Read Write Grant Acknowledge Ground signal M68360QUADS.
M68360QUADS User's Manual SUPPORT INFORMATION
5.2.6
Connector Interconnect Signals
Connector triple-row, pin, male connector. remaining signals master QUICC appear this connector. Table describes connector signals.
Table Connector Interconnect Signals
A22, Signal Name PA15 PRTY0 PRTY3 IRQ1~ IRQ7~ AVEC~ PB17 PC11 CAS0~ CAS3~ CS0~ CS7~ HALT~ AMUX TRST~ BKPT~ RESETH~ RESETS~ CONFIG0 CONFIG1 TRIS~ MODCK0 MODCK1 CLKO2 CLK2 Description Port pins master QUICC Parity lines Ground signal M68360QUADS Interrupt request signals master QUICC Auto vector master QUICC Ground signal M68360QUADS Port pins master QUICC Ground signal M68360QUADS Port pins master QUICC Ground signal M68360QUADS signals master QUICC Chip select signals master QUICC HALT~ master QUICC AMUX/OE~ master QUICC master QUICC master QUICC master QUICC master QUICC TRST~ master QUICC Breakpoint master QUICC Hard reset master QUICC Soft reset master QUICC RMC~/CONFIG0 master QUICC CONFIG1 master QUICC TRIS~ master QUICC Clock mode select master QUICC Clock mode select master QUICC Ground signal M68360QUADS System clock master QUICC, MHz. Ground signal M68360QUADS operating clock M68360QUADS, MHz.
M68360QUADS User's Manual SUPPORT INFORMATION
5.2.7
Connector Interconnect Signals
Connector triple-row, pin, female connector. expansion connectors provide signals master QUICC. Table describes connector signals.
Table Connector Interconnect Signals
Signal Name AMUX SIZ0, SIZ1 EXTBR~ EXTBG~ BGACK~ R/W~ CONFIG0 CONFIG1 DSACK0~ DSACK1~ BERR~ HALT~ RESETH~ RESETS~ PERR~ TRIS~ MODCK0 MODCK1 CLK1 CLK2 Description Address lines master QUICC Data lines master QUICC Function code lines master QUICC AMUX/OE~ master QUICC Transfer Size lines master QUICC External master request input Local Arbiter External master grant output from Local Arbiter grant acknowledge line Address strobe line Ground signal M68360QUADS Data strobe line Read/Write~ line RMC~/CONFIG0 master QUICC CONFIG1 master QUICC Data size acknowledge line master QUICC Data size acknowledge line error line master QUICC HALT~ master QUICC Hard reset master QUICC Soft reset master QUICC Parity error master QUICC TRIS~ master QUICC Clock mode select master QUICC Clock mode select master QUICC Ground signal M68360QUADS operating clock M68360QUADS, MHz. Ground signal M68360QUADS operating clock M68360QUADS, MHz.
M68360QUADS User's Manual SUPPORT INFORMATION
5.2.8
Connector Interconnect Signals
Connector triple-row, pin, female connector. expansion connectors provide signals master QUICC. Table describes connector signals.
Table Connector Interconnect Signals
A22, Signal Name PA15 PRTY0 PRTY3 IRQ1~ IRQ7~ AVEC~ PB17 PC11 CAS0~ CAS3~ CS0~ CS7~ FREEZE TRST~ BKPT~ RESETH~ RESETS~ IFETCH~ IPIPE0~ IPIPE1~ CLKO2 CLK2 Description Port pins master QUICC Parity lines Ground signal M68360QUADS Interrupt request signals master QUICC Auto vector master QUICC Ground signal M68360QUADS Port pins master QUICC Ground signal M68360QUADS Port pins master QUICC Ground signal M68360QUADS signals master QUICC Chip select signals master QUICC Ground signal M68360QUADS FREEZE master QUICC master QUICC master QUICC master QUICC master QUICC TRST~ master QUICC Breakpoint master QUICC Hard reset master QUICC Soft reset master QUICC Instruction fetch master QUICC Instruction pipe master QUICC Instruction pipe master QUICC +12V Ground signal M68360QUADS System clock master QUICC, MHz. Ground signal M68360QUADS operating clock M68360QUADS, MHz.
M68360QUADS User's Manual SUPPORT INFORMATION
5.2.9
Connector Interconnect Signals
Connector double-row, pin, male connector. provides signals master QUICC, that controlled external controller. Table describes connector signals.
Table Connector Interconnect Signals
Signal Name BKPT~ FREEZE RESETH~ IFETCH~ IPIPE0~ Description Ground signal M68360QUADS Breakpoint master QUICC Ground signal M68360QUADS FREEZE master QUICC Hard reset master QUICC Instruction fetch master QUICC Instruction pipe master QUICC
5.2.10
Connector Interconnect Signals
Connector pin, male type connector. port M68360QUADS. Table describes connector signals.
Table 5-10 Connector Interconnect Signals
Signal Name INT_ACK HST_ACK ADS_ALL ADS_RESET ADS_SEL2 ADS_SEL1 ADS_SEL0 HOST_REQ ADS_REQ ADS_ACK ADS_INT HOST_BRK~ ADS_BRK Description Interrupt Acknowledge input signal from host connected Host Acknowledge input signal from host QUADS input signal from host QUADS Reset input signal from host QUADS Select input signal from host QUADS Select input signal from host QUADS Select input signal from host HOST Request input signal from host QUADS Request output signal from M68360QUADS host QUADS Acknowledge output signal from M68360QUADS host QUADS Interrupt output signal from M68360QUADS host HOST Break open collector output signal from M68360QUADS host QUADS Break input signal from host connected port data port data port data port data Ground signal M68360QUADS connected. host supplies +12V this pin, connected M68360QUADS
M68360QUADS User's Manual SUPPORT INFORMATION
Table 5-10 Connector Interconnect Signals
Signal Name HOST_VCC HOST_ENABLE~ Description HOST input from host. M68360QUADS does these inputs power supply. HOST Enable input signal from host. Ground signal M68360QUADS port data port data port data port data
5.2.11
Connector Interconnect Signals
Connector pin, female type connector. RS-232 serial port M68360QUADS. Table describes connector signals.
Table 5-11 Connector Interconnect Signals
Signal Name (N.C.) Description Carrier Detect output from M68360QUADS. Transmit Data output from M68360QUADS. Receive Data input M68360QUADS. Data Terminal Ready input M68360QUADS. Ground signal M68360QUADS. Data Ready output from M68360QUADS. Request Send. This line connected M68360QUADS. Clear Send output from M68360QUADS. connected
5.2.12
Connector Interconnect Signals
Connector pin, MINI JACK connector. AppleTalk port M68360QUADS board. Table describes connector signals.
Table 5-12 Connector Interconnect Signals
Signal Name HSKI TXGND RXTX+ Description output from M68360QUADS through resistor. Hand Shake Input signal. Transmit Data negative output from M68360QUADS. Ground signal M68360QUADS. Receive Data negative input M68360QUADS. Transmit Data positive output from M68360QUADS. connected Receive Data positive input M68360QUADS.
M68360QUADS User's Manual SUPPORT INFORMATION
5.2.13
Connector Interconnect Signals
Connector pin, female type connector. Ethernet port M68360QUADS board. Table describes connector signals.
Table 5-13 Connector Interconnect Signals
Signal Name ACX+ ATX+ ARX+ ACXATXGND ARXVPP Description Ground signal M68360QUADS. Collision detect positive input M68360QUADS. Transmit Data positive output from M68360QUADS. Ground signal M68360QUADS. Receive Data positive input M68360QUADS. Ground signal M68360QUADS. connected Ground signal M68360QUADS. Collision detect negative input M68360QUADS. Transmit Data negative output from M68360QUADS. Ground signal M68360QUADS. Receive Data negative input M68360QUADS. +12V power supply from M68360QUADS. Ground signal M68360QUADS. connected
5.2.14
Connector Interconnect Signals
Connector pin, RJ-45 connector. twisted-pair Ethernet port M68360QUADS board. Table describes connector signals.
Table 5-14 Connector Interconnect Signals
Signal Name TPTX+ TPTXTPRX+ TPRXDescription Twisted-Pair Transmit Data positive output from M68360QUADS. Twisted-Pair Transmit Data negative output from M68360QUADS. Twisted-Pair Receive Data positive input M68360QUADS. connected connected Twisted-Pair Receive Data negative input M68360QUADS. connected connected
M68360QUADS User's Manual SUPPORT INFORMATION
5.2.15
Connector Interconnect Signals
Connector double-row, pin, male connector. controller port, that enables M68360QUADS control external QUICC devices. slave QUICC general purpose pins connected Table describes connector signals.
Table 5-15 Connector Interconnect Signals
Signal Name BDMCLK BDMFRZ BDMRST BDMDSI BDMDSO Description Ground signal M68360QUADS. This signal connected Port slave QUICC. should connected breakpoint external QUICC device. Ground signal M68360QUADS. This signal connected Port slave QUICC. should connected FREEZE external QUICC device. This signal connected Port slave QUICC. should connected Hard reset external QUICC device. This signal connected Port slave QUICC. should connected Instruction fetch external QUICC device. This signal connected Port slave QUICC. should connected Instruction pipe external QUICC device.
5.2.16
Connector Interconnect Signals
Connector double-row, wire holes M68360QUADS. provides signals between slave QUICC EEST. This connector used internal factory testing board. Table describes connector signals.
Table 5-16 Connector Interconnect Signals
Signal Name Ethernet TENA Ethernet TCLK Ethernet RENA Ethernet RCLK CLSN EEST EEST Description This connected Port slave QUICC transmit data input EEST. This connected Port slave QUICC TENA input EEST. This connected Port slave QUICC TCLK output EEST. This connected Port slave QUICC receive data output EEST. This connected Port slave QUICC RENA output EEST. This connected Port slave QUICC RCLK output EEST. This connected Port slave QUICC CLSN output EEST. This connected EEST input pin. This signal driven slave QUICC, connected pull-up resistor. This connected EEST input pin. This signal driven slave QUICC, connected pull-up resistor.
M68360QUADS User's Manual SUPPORT INFORMATION
Table 5-16 Connector Interconnect Signals
Signal Name EEST TPEN APORT TPAPCE TPSQEL TPFULDL LOOP Description This connected Port slave QUICC input EEST. This connected Port slave QUICC TPEN EEST. This connected Port slave QUICC APORT input EEST. This connected Port slave QUICC TPAPCE input EEST. This connected Port slave QUICC TPSQEL input EEST. This connected Port slave QUICC TPFULDL input EEST. This connected Port slave QUICC LOOP input EEST.
5.2.17
Connector Interconnect Signals
Connector connector power supply. connector supplied with plug convenient connection power supply. Table describes connector signals.
Table 5-17 Connector Interconnect Signals
Signal Name Description connection power supply. Ground connection power supply. Ground connection power supply.
5.2.18
Connector Interconnect Signals
Connector connector power supply. connector supplied with plug convenient connection power supply. Table describes connector signals.
Table 5-18 Connector Interconnect Signals
Signal Name Description +12V connection power supply. Ground connection power supply.
M68360QUADS User's Manual SUPPORT INFORMATION
M68360QUADS Parts List
components M68360QUADS their reference designation listed Table 5-19.
Table 5-19 Parts List
Reference Designation U15, U20, U25, U28, U17, U26, U38, U49, U50, U55, U60, U31, U39, U53, U62, Part Description Resistor Network, pins, I.C. 74LS245 I.C. MC68360 QUICC I.C. 74F245 Notes socket mounted
I.C. 74LS240 I.C. 74LS85 Resistor Network, pins, 4700
I.C. 74ACT244 I.C. 74ACT74 I.C. MC145407 Factory testing socket Clock Oscillator I.C. MC34050 I.C. PE64503 I.C. 74LS74 I.C. MCM2814 serial EEPROM I.C. MC68160 EEST I.C. 74LS373 LAF10T-3B Ethernet filter LAF10T-7B Ethernet filter I.C. Programmed PAL16R4-7 I.C. Programmed PAL22V10-25 I.C. PE65263 I.C. PE65260 Dip-Switch SPST4, I.C. 74F04 I.C. 27010-20 EPROM I.C. Programmed GAL22V10-7 Dip-Switch SPST8, I.C. 74F157A
socket mounted TQFP socket mounted socket mounted socket mounted socket mounted
M68360QUADS User's Manual SUPPORT INFORMATION
Table 5-19 Parts List
Reference Designation U56, U58, U57, U64, U72-U75 C35, C40, C41, C51, C55, C95, C36, C53, R2,R25 R11, R23, R10, R16, R19, R20, R24, R29, RS1, Part Description I.C. 74LS00 I.C. 74F32 I.C. 74F08 I.C. 74F00 I.C. 74LS05 I.C. 74F538 SIMM DRAM MCM36256S80 I.C. 28F010-120 Flash Memory I.C. Programmed PAL22V10-25 Capacitor ceramic Capacitor electrolytic Capacitor electrolytic Capacitor Notes with SIMM socket PLCC T.H. T.H. T.H.
Capacitor Capacitor Capacitor Capacitor 4700 Capacitor 3900 Capacitor Capacitor 0.039 Capacitor mounted. Used factory testing. Resistor Resistor Kohm Resistor Resistor Resistor Resistor Resistor Resistor Kohm Resistor Resistor Resistor Kohm
M68360QUADS User's Manual SUPPORT INFORMATION
Table 5-19 Parts List
Reference Designation LD1, LD7, XT1, XT3, Part Description Resistor mounted. Used factory testing. Connector female degrees. Compatible wirewrap connectors supplied with M68360QUADS. Connector Connector type male Connector type female Connector mini jack Connector type female Connector RJ-45 wire holes EEST signals Power connector, with plug Power connector, with plug Connector male. Compatible with logic analyzers Connector male straight GREEN YELLOW MBRD620CT diode 1SMC5.0AT3 1SMC12AT3 Fuse block with Fuse Fuse block with Fuse Switch, push-button, SPDT Switch, push-button, SPDT Switch, push-button, SPDT mounted. Used factory testing. Notes
pins
power supply power supply
Fuse supply Fuse supply with with Orange with Black
M68360QUADS User's Manual BOARD INSTALLATION
APPENDIX BOARD INSTALLATION
INTRODUCTION
This appendix describes hardware installation board into various host computers. installation instructions cover following host computers: IBM-PC/XT/AT (SBus interface)
IBM-PC/XT/AT M68360QUADS Interface
board should installed IBM-PC/XT/AT motherboard system expansion slots. single control eight M68360QUADS boards. address computer configured memory addresses 100-102 (hex), reconfigured alternate address space.
A.2.1
CAUTION BEFORE REMOVING INSTALLING EQUIPMENT IBM-PC/XT/AT COMPUTER, TURN POWER REMOVE POWER CORD. Installation IBM-PC/XT/AT
Refer appropriate Installation Setup manual IBM-PC/XT/AT computer instructions removing computer cover. board address block should configured free address space computer. address must unique must fall within address range another card installed computer. board address block configured start three following addresses: $100 This address unassigned IBM-PC $200 This address usually used game port $300 This address defined prototype port board factory configured address decoding 100-102 IBM-PC/XT/AT address map. These undefined peripheral addresses.
M68360QUADS User's Manual BOARD INSTALLATION
FIGURE Physical Location jumper
NOTE: Jumper should left unconnected. following figure shows required jumper connection each address configuration. Address recommended, usage might cause problems.
FIGURE Configuration Options
properly install board, position front bottom corner plastic card guide channel front IBM-PC/XT/AT chassis. Keeping board level ribbon cables way, lower board until connectors aligned with computer expansion slot connectors. Using evenly distributed pressure, press board straight down until seats expansion slot. Secure board computer chassis using bracket retaining screw. Refer computer Installation Setup manual instructions reinstalling computer cover.
M68360QUADS User's Manual BOARD INSTALLATION
SUN-4 M68360QUADS Interface
board should installed SBus expansion slots Sun-4 SPARCstation computer. single control eight M68360QUADS boards.
A.3.1
CAUTION BEFORE REMOVING INSTALLING EQUIPMENT SUN-4 COMPUTER, TURN POWER REMOVE POWER CORD. Installation SUN-4
There jumper options board Sun-4 computer. board inserted into available SBus expansion slot motherboard. Refer appropriate Installation Setup manual Sun-4 computer instructions removing computer cover installing board expansion slot.
FIGURE board SBus
Connector
SBus Connector
Following summary Instructions manual: Turn power system, keep power cord plugged sure save open files then following steps should shut down your system: hostname% /bin/su Password: mypasswd hostname# /usr/etc/halt wait following messages. Syncing file systems. done Halted Program Terminated Type b(boot), c(continue), n(new command mode) When these messages appear, safely turn power system unit. Open system unit. sure attach grounding strap your wrist metal casing power supply. Follow instructions supplied with your system gain access SBus slots.
M68360QUADS User's Manual BOARD INSTALLATION Remove SBus slot filler panel desired slot from inner surface back panel system unit. Note that board slave only board thus will function available SBus slot. Slide board angle into back panel system unit. Make sure that mounting plate board hooks into holes back panel system unit. Push board against back panel align connector with mate gently press corners board seat connector firmly. Close system unit. Connect interface flat cable board secure. Turn power system unit check proper operation.
M68360QUADS User's Manual PORT HANDSHAKE DESCRIPTION
APPENDIX PORT HANDSHAKE DESCRIPTION
INTRODUCTION
this appendix, port signals handshake procedure explained. M68360QUADS port connected board mounted host computer. There boards following host computers: IBM-PC/XT/AT (SBus interface)
Port Concept Operation Description
Each board connected M68360QUADS boards. Each M68360QUADS address which fixed setting Dip-Switch board. Refer section 2.3.1 page following operations performed using port host computer write byte M68360QUADS M68360QUADS write byte host computer M68360QUADS interrupt host computer host computer interrupt M68360QUADS (interrupt level host computer reset (soft hard) M68360QUADS more than M68360QUADS connected same board, host computer perform following operations simultaneously M68360QUADS boards Abort boards (interrupt level Reset boards
M68360QUADS User's Manual PORT HANDSHAKE DESCRIPTION
Handshake Description
Every action between M68360QUADS host asynchronous implemented asserting negating handshake signals software. signals have levels. control signal asserted driven logic level, negated driven logic level. connection between host computer M68360QUADS shown FIGURE below.
FIGURE Host Computer (ADI) M68360QUADS Connection
HOST_REQ ADS_ACK ADS_REQ HST_ACK ADS_BRK HOST_BRK~
HOST COMPUTER
board
ADS_INT INT_ACK ADS_RESET ADS_ALL ADS_SEL(0:2) PD(0:7) HOST_ENABLE~ HOST_VCC
M68360QUADS
M68360QUADS User's Manual PORT HANDSHAKE DESCRIPTION
B.3.1
Write Cycle from Host M68360QUADS
application software Host uses handshake signals coordinate data transfer across parallel link. CPU32bug software M68360QUADS responsible accepting data responding handshake signals. signals shown FIGURE B-2. sequence events during byte write M68360QUADS follows: Host selects M68360QUADS board putting board's address ADS_SEL(0:2) signals. Host places data byte data latch (buffer high-impedance state). Host asserts HOST_REQ signal (the data buffer enabled, data appears bus). M68360QUADS detects HOST_REQ signal reads data byte. M68360QUADS asserts ADS_ACK signal. Host detects ADS_ACK signal negates HOST_REQ signal (data buffer disabled). M68360QUADS detects negation HOST_REQ signal negates ADS_ACK cycle.
FIGURE Host Write M68360QUADS ADS_SEL(0:2) HOST_REQ ADS_ACK PD(0:7) DATA VALID ADDRESS VALID
M68360QUADS User's Manual PORT HANDSHAKE DESCRIPTION
B.3.2
Write Cycle from M68360QUADS Host
signal handshake during M68360QUADS Host write cycle shown FIGURE B-3. sequence events follows: M68360QUADS places data byte parallel port data (buffer disabled) asserts ADS_REQ signal. (the ADS_REQ signal will appear port until board selected Host) Host polls each M68360QUADS address detects ADS_REQ signal from requesting board. Host asserts HST_ACK signal response, which enables data buffer M68360QUADS. M68360QUADS negates ADS_REQ signal. data appears long HST_ACK signal asserted. Host reads data. Host negates HST_ACK signal cycle. M68360QUADS ends cycle.
FIGURE M68360QUADS Write Cycle Host ADS_REQ PD(0:7) DATA VALID
ADS_SEL(0:2) HST_ACK
ADDRESS VALID
B.3.3
M68360QUADS Interrupt Host
M68360QUADS generate interrupt Host. interrupt request acknowledge sequence shown FIGURE B-4. sequence follows: M68360QUADS places service request code parallel port data (buffer disabled) asserts ADS_INT HOST_BRK~ signals. HOST_BRK~ signal open-collector signal, asserted low, common M68360QUADS boards which will appear immediately port. ADS_INT signal will appear port until board selected Host. Host detects HOST_BRK~ signal polls each M68360QUADS address determine interrupting board. Host asserts HST_ACK signal, enabling data buffer M68360QUADS. Host reads service request code data bus. Host negates HST_ACK signal. Host asserts INT_ACK signal, which resets HOST_BRK latch M68360QUADS negates HOST_BRK~ signal. HOST_BRK~ signal still (asserted) another M68360QUADS board driving low.
M68360QUADS User's Manual PORT HANDSHAKE DESCRIPTION selected M68360QUADS detects INT_ACK signal negates ADS_INT signal. Host negates INT_ACK signal ends cycle.
FIGURE M68360QUADS Interrupt Host hardware ADS_INT PD(0:7) ADS_SEL(0:2) HST_ACK INT_ACK ADDRESS VALID DATA VALID software
HOST_BRK~
B.3.4
Host Interrupt M68360QUADS
Host interrupt M68360QUADS (interrupt level abort execution programs running board. This done selecting address required M68360QUADS momentarily asserting ADS_BRK signal, which sets latch M68360QUADS. output latch interrupts master QUICC M68360QUADS. latch cleared interrupt handling software M68360QUADS.
B.3.5
Host Reset M68360QUADS
Host perform either hard reset soft reset M68360QUADS. Soft reset done selecting address required board asserting ADS_RESET signal more than microseconds. Hard reset done selecting address required board, asserting INT_ACK signal, asserting ADS_RESET signal more than microseconds.
B.3.6
Addressing M68360QUADS
Host reset interrupt M68360QUADS boards that connected same ADI. Host should assert ADS_ALL signal conjunction with either ADS_RESET ADS_BRK. contents ADS_SEL(0:2) lines have affect.
M68360QUADS User's Manual SUPPORT INFORMATION
APPENDIX PLDs DESCRIPTION
DATA CONTROLLER
chip schematic sheet GAL22V10-7 device. This device generates required byte enable signals according data width master QUICC, accessed address, data size. device also controls operation data transceivers, data swapping. module BUS_CNTL title 'BUS CONTROL AMIR YEHOSHUA MOTOROLA SEMICONDUCTOR ISRAEL LTD. 12/12/92 device 'P22V10'; 1,2,3,4,5 6,7,8,9 10,11,13 14,15,16,17 18,19 20,21,22,23 Node 25,26
RSTH~,AS~,DSK1~,A0,A1 SIZ0,SIZ1,A_DIR,B32_16~ S_CS7~,A28_31,R~ HI_EN~,SWAP~,LO_EN~,D_DIR MDSK0~,SDSK0~ BE3~,BE2~,BE1~,BE0~ reset,preset H,L,X,Z,C equations reset preset 1,0,.X.,.Z.,.C.
ENABLE BE0~ !BE0~ !AS~ !AS~ ENABLE BE1~ !BE1~ !AS~ SIZ1 !AS~ !SIZ0 !AS~ !AS~
M68360QUADS User's Manual SUPPORT INFORMATION ENABLE BE2~ !BE2~ !AS~ !SIZ0 !SIZ1 !AS~ !A_DIR !SIZ0 !SIZ1 !AS~ B32_16~ SIZ0 SIZ1 !AS~ !A_DIR SIZ0 SIZ1 !AS~ B32_16~ !SIZ0 !AS~ !A_DIR !SIZ0 !AS~ B32_16~ !AS~ ENABLE BE3~ !BE3~ !AS~ SIZ1 !AS~ A_DIR !B32_16~ !SIZ0 !AS~ A_DIR !B32_16~ SIZ0 SIZ1 !AS~ !A_DIR SIZ0 SIZ1 !AS~ B32_16~ !SIZ0 !SIZ1 !AS~ !A_DIR !SIZ0 !SIZ1 !AS~ B32_16~ SIZ1 !AS~ !A_DIR SIZ1 !AS~ B32_16~ !AS~ ENABLE MDSK0~ !SDSK0~ A_DIR RSTH~ !MDSK0~ !SDSK0~ B32_16~ !AS~ !SDSK0~ !B32_16~ !AS~ DSK1~ ENABLE SDSK0~ !MDSK0~ !A_DIR RSTH~ !SDSK0~ !MDSK0~ B32_16~ !AS~ !MDSK0~ !B32_16~ !AS~ DSK1~ ENABLE D_DIR !D_DIR S_CS7~ !A28_31 !A_DIR ENABLE LO_EN~ !LO_EN~ B32_16~ !AS~ RSTH~
M68360QUADS User's Manual SUPPORT INFORMATION
ENABLE SWAP~ !SWAP~ !B32_16~ !AS~ RSTH~ A_DIR !B32_16~ !AS~ RSTH~ A_DIR S_CS7~ !A28_31 !DSK1~ !SDSK0~ !B32_16~ !AS~ RSTH~ A_DIR S_CS7~ !A28_31 !DSK1~ !MDSK0~
ENABLE HI_EN~ !HI_EN~ B32_16~ !AS~ RSTH~ !B32_16~ !AS~ RSTH~ !A_DIR !B32_16~ !AS~ RSTH~ A_DIR !B32_16~ !AS~ RSTH~ A_DIR S_CS7~ !A28_31 !B32_16~ !AS~ RSTH~ A_DIR S_CS7~ !A28_31 !DSK1~ SDSK0~ MDSK0~ !B32_16~ !AS~ RSTH~ A_DIR S_CS7~ !A28_31 DSK1~ !SDSK0~ !B32_16~ !AS~ RSTH~ A_DIR S_CS7~ !A28_31 DSK1~ !MDSK0~
BUS_CNTL
M68360QUADS User's Manual SUPPORT INFORMATION
ARBITER
chip schematic sheet PAL16R4-7 device. This device uses master QUICC arbitration logic transfer mastership slave QUICC external master. Grant signals slave QUICC external master asserted after BGACK~ signal negated. This ensure that address transceivers opened correctly before requesting master takes control bus. This device also generates signal A28_31 which used Data Controller determine current access device QUADS board. module ARBITER title 'BUS ARBITER AMIR YEHOSHUA MOTOROLA SEMICONDUCTOR ISRAEL LTD. 18/3/93 device 'P16R4'; 1,11 2,3,4,5 6,7,8,9,12,13 14,15,16,17,18,19
SCLKO1,OC~ EXTBR~,M_BG~,S_BR~,BGACK~ A28,A29,A30,A31,M_CS0~,E_CS~ H,L,X,Z,C equations !A_DIR !S_BG~ !BGACK~ !A_DIR !M_BR~ !EXTBR~ !S_BR~ 1,0,.X.,.Z.,.C.;
!EXTBG~ EXTBG~ S_BR~ !M_BR~ S_BG~ !M_BG~ BGACK~ !EXTBG~ !EXTBR~ S_BG~ !M_BG~ !S_BG~ S_BG~ !S_BR~ !M_BR~ EXTBG~ !M_BG~ BGACK~ !S_BG~ !S_BR~ EXTBG~ !M_BG~ ENABLE M_CS0~ ENABLE E_CS~ ENABLE ENABLE A28_31
M68360QUADS User's Manual SUPPORT INFORMATION !A28_31 !A28 !A29 !A30 !A31 M_CS0~ !A28 !A29 !A30 !A31 !E_CS~ M_CS0~ !E_CS~ ARBITER
M68360QUADS User's Manual SUPPORT INFORMATION
PORT CONTROLLER
chip schematic sheet PAL22V10-25 device used controlling port. module title 'ADI AMIR YEHOSHUA device
MOTOROLA SEMICONDUCTOR ISRAEL LTD. 12/12/92 'P22V10'; 1,2,3,4 5,6,7,8 9,10,13 14,15,16 20,21,22,23 Node 25,26
ADS_G~,RSTS~,HSVCC~,ADRST~ ADALL~,ADBRK~,HSTEN,HSACK~ HSREQ~,INACK~,ADSSEL ADIRD~,CK_NMI,BKCLR~ ADIAC~ H_RSTH,H_RSTS,ADI_G~,ADIDIR reset,preset H,L,X,Z,C equations reset preset ENABLE ADIDIR ENABLE ADI_G~ ENABLE H_RSTS ENABLE H_RSTH ENABLE ADIAC~ ENABLE CK_NMI ENABLE BKCLR~ ENABLE ADIRD~ 1,0,.X.,.Z.,.C.
H_RSTS HSTEN !HSVCC~ !ADRST~ ADSSEL HSTEN !HSVCC~ !ADRST~ !ADALL~ H_RSTH HSTEN !HSVCC~ !ADRST~ ADSSEL !INACK~ HSTEN !HSVCC~ !ADRST~ !ADALL~ !INACK~
CK_NMI HSTEN !HSVCC~ !ADBRK~ ADSSEL HSTEN !HSVCC~ !ADBRK~ !ADALL~
M68360QUADS User's Manual SUPPORT INFORMATION !BKCLR~ !RSTS~ !INACK~ HSTEN !HSVCC~ ADSSEL !ADIRD~ HSTEN ADSSEL !HSVCC~ !ADI_G~ !HSTEN !HSVCC~ (ADSSEL !ADALL~) (!HSACK~ !ADS_G~) !ADIAC~ HSTEN !HSVCC~ !HSREQ~ !ADALL~ HSTEN !HSVCC~ !HSREQ~ ADSSEL HSTEN !HSVCC~ !HSACK~ ADSSEL !ADIDIR !HSTEN ADS_G~ (ADSSEL !HSACK~)
M68360QUADS User's Manual SUPPORT INFORMATION
Disable Configuration Slave QUICC
chip schematic sheet PAL22V10-25 device that operates during hard reset used configure slave QUICC disable operation mode. disable QUICC device, encoding configuration pins must enable more than clocks during hard reset, then they must encoded according required operation mode before hard reset signal negated (high level). device drives configuration slave QUICC high level clocks, then signal CONF2 drives level long hard reset signal asserted (low level). When hard reset signal negated, CONF2 three-state stops driving configuration TITLE DISCPU PATTERN dis_cpu.pds Revision AUTHOR Yair Liebman COMPANY MOTOROLA SEMICONDUCTOR ISRAEL DATE 14/3/93 CHIP DIS_CPU PAL22V10 ;********************** RESETH S_RST DD_RST D_RST
CONF2
GLOBAL EQUATIONS D_RST RESETH D_RST.TRST DD_RST D_RST DD_RST.TRST /S_RST /D_RST DD_RST S_RST S_RST /CIN Q0.TRST
M68360QUADS User's Manual SUPPORT INFORMATION
S_RST S_RST S_RST /CIN Q1.TRST S_RST S_RST S_RST S_RST /CIN Q2.TRST S_RST S_RST S_RST S_RST S_RST /CIN Q3.TRST S_RST S_RST S_RST S_RST S_RST S_RST /CIN Q4.TRST S_RST S_RST S_RST S_RST S_RST S_RST S_RST /CIN Q5.TRST
M68360QUADS User's Manual SUPPORT INFORMATION /CONF2 CONF2.TRST /RESETH
GLOBAL.SETF GLOBAL.RSTF
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