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MAEC TECHNICAL NEWS

Setting procedure of processor mode bits

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MAEC TECHNICAL NEWS
Setting procedure of processor mode bits
No.M16C-71-0105
Classification Corrections and supplementary explanation of document Notes Knowhow Others
Products Effected
M16C / 80 Series M16C / 60 Series
1. Precautions
Processor mode bits are allocated to bits 1 and 0 of the processor mode register 0. Regardless of the level of the CNVSS pin, changing the processor mode bits selects the mode. Therefore, never change the processor mode bits when changing the contents of other bits. Do not change the processor mode bits simultaneously with other bits when changing the processor mode bits "012" or "112". Change the processor mode bits after changing the other bits. Figure 1 shows the processor mode register 0 of M16C / 62A group, and figure 2 shows the setting procedure of processor mode bits.
Processor mode register 0 (Note 1)
Symbol PM0
Address 000416
When reset 0016 (Note 2)
Bit symbol
PM00 PM01 PM02 PM03
Bit name
Processor mode bit
Function
0 0: Single-chip mode 0 1: Memory expansion mode 1 0: Do not set 1 1: Microprocessor mode 0 : RD, BHE, WR 1 : RD, WRH, WRL The device is reset when this bit is set to "1". The value of this bit is "0" when read.
R / W mode select bit Software reset bit
PM04 PM05 PM06
Multiplexed bus space select bit
0 0 : Multiplexed bus is not used 0 1 : Allocated to CS2 space 1 0 : Allocated to CS1 space 1 1 : Allocated to entire space (Note4)
Port P40 to P43 function select bit (Note 3) BCLK output disable bit
0 : Address output 1 : Port function (Address is not output) 0 : BCLK is output 1 : BCLK is not output (Pin is left floating)
Note 1: Set bit 1 of the protect register (address 000A16) to "1" when writing new values to this register. Note 2: If the VCC voltage is applied to the CNVSS, the value of this register when reset is 0316. (PM00 and PM01 both are set to "1".) Note 3: Valid in microprocessor and memory expansion modes. Note 4: If the entire space is of multiplexed bus in memory expansion mode, choose an 8bit width.The processor operates using the separate bus after reset is revoked, so the entire space multiplexed bus cannot be chosen in microprocessor mode. P31 to P37 become a port if the entire space multiplexed bus is chosen, so only 256 bytes can be used in each chip select.
Figure 1. Processor mode register 0
When changing into the following state after reset · Memory expansion mode · Entire space multiplexed bus
MOV.B
#00110001B, PM0
MOV.B MOV.B
#00110000B, PM0 #00110001B, PM0
Setting other bits except the processor mode bits
Figure 2. Setting procedure