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SELECTING CONVERTER
Larry Gaddy
Mailing Address: 11400 Tucson, 85734 Street Address: 6730 Tucson Blvd. Tucson, 85706 Tel: (520) 746-1111 Twx: 910-952-111 Telex: 066-6491 (520) 889-1510 Immediate Product Info: (800) 548-6132
Selecting converter digitizing system seem arduous task. There plethora converters available marketplace from wide variety manufacturers. process selection simplified means checklist, organized importance. This bulletin intended walk reader through this checklist, describe factors some detail, learn which manufacturer's specifications apply these factors interpret those specifications. selection checklist broken into areas- primary facts which cannot compromised, secondary factors which allow designer some flexibility. Primary What required level system accuracy? many bits resolution required? What nature analog input signal? fast must converter operate (conversion speed)? What environmental conditions? track-and-hold circuit required? Secondary Does system have multiple channels? Should reference internal external? What What What What drive amplifier requirements? digital interface requirements? type digital output format required? timing conditions? they critical system's performance. Understand test conditions specifications, making certain they closely match operating conditions digitizing system.
PRIMARY FACTORS
ACCURACY accuracy overall system must considered. most cases, converter only element digitizing system. example, overall system accuracy requirement 0.012% (12-bits), converter usually needs more accurate, perhaps 0.006% (13-bits) which would allow analog front error budget (least significant bit). good rule thumb follow when selecting analog components digitizing system each component five times more accurate than total system accuracy. Resolution should confused with accuracy-these terms somewhat exclusive. Resolution simply refers theoretical number states (2n) which analog input resolved into, where number bits resolution. Accuracy indicates close converter comes theoretical limits. this section, accuracy will examined time domain, where specifications static (DC). four static accuracy specifications differential nonlinearity (DNL), integral nonlinearity (INL), offset error gain error. ideal transfer function 3-bit converter shown Figure OFFSET ERROR transfer function 3-bit converter with offset error +1LSB shown Figure Output code shown Y-axis analog input amplitude shown X-axis. Offset error amount which first code transition (from 001) deviates from ideal position input equivalent 0.5LSB. Another consider offset error examine distance between intercept graph where straight line drawn through actual transfer function intercepts X-axis. Offset error will cause entire transfer function shift along Y-axis (output code dependent variable). Offset error commonly expressed LSBs, volts percentage full-scale range (%FSR).
shown converter checklist most important element process. first step complete definition design objectives digitizing system. converter checklist used guideline insure important factors considered. objective find converter which fits into system design, vice versa. Secondly, very important once converter selection process begun have complete understanding specifications. Understand what absolute requirements are, insist guaranteed specifications those parameters. Although most reputable manufacturers' typical specifications have some measure validity, never depend those values
1995 Burr-Brown Corporation
AB-098
Printed U.S.A. April, 1995
SBAA004
Ideal Transfer Function
Output Code
Output Code
Actual
Analog Input
Analog Input
FIGURE Ideal 3-Bit Converter Transfer Function.
FIGURE Offset Error LSB.
Actual Gain Error
Output Code
Missing Code Output Code
Ideal Gain Error Slope
Analog Input
Analog Input
FIGURE Positive Gain Error.
FIGURE Differential Nonlinearity.
GAIN ERROR Figure illustration 3-bit converter transfer function with gain error. From this figure, gain error described deviation straight line through transfer function intercept full scale. also expressed deviation from ideal gain slope Gain error usually expressed percentage full scale range (%FSR), also specified volts LSBs. Gain error dominated errors converter's reference voltage, since value reference determines full scale range device.
DIFFERENTIAL NONLINEARITY Differential nonlinearity used describe deviations from ideal transition voltages converter's transfer function. Figure illustrates example error. Each code transition should occur interval equal LSB. example, with 3-bit A/D, first transition occurs full scale (0.125 FSR), second transition will ideally occur 0.250 FSR. deviation from that ideal transition differential linearity error that unique code. specification converter should describe worst case transition possible transitions
Bits
Bits
Nonlinearity Referred Points
Output Code
Output Code
Nonlinearity Referred "Best Fit" Straight Line
Ideal Straight Line Transfer Function Bits Analog Input Bits
Ideal Straight Line Transfer Function
Analog Input
FIGURE Integral Nonlinearity referred Inputs. converter. When referred resolution converter, error -1LSB implies code missing. Most converters specified with missing codes" some level accuracy, typically equivalent resolution A/D. some cases, missing codes specified less than resolution given converter. example, many 16-bit converters guaranteed have missing codes 15-bits. 16-bit converter with missing codes would have 65,535 possible output codes. specified with missing codes 16-bits, possible output codes must exist. Note missing codes" specification does give user information about code width; simply that some portion every output code will present. 16-bit converter specification -1LSB, output only guaranteed have 15-bits information given output state. converter specified with missing codes 15-bits, then output only guaranteed have 15-bits information given output size. Positive errors indicate long codes, have real limit their value, irrespective resolution. simple test servo input voltage until transition detected, then measure voltage required force that transition. input voltage required force next transition then measured, with difference between transitions -1LSB defined error that transition. caution testing presence noise converter. Since noise usually Gaussian, averaging values transition will yield true results. INTEGRAL NONLINEARITY Integral nonlinearity used describe overall shape transfer function converter. This error sometimes referred static linearity absolute linearity. Figure illustrates example integral nonlinearity
FIGURE Integral Nonlinearity Referred Best-Fit Straight Line. ferred points Figure example integral nonlinearity referred best-fit line. point linearity, straight line drawn between converter's offset gain intercept points, transfer function plotted against that straight line. maximum deviation from line worst case integral nonlinearity. best-fit example, transitions used least squares calculation, line best-fit drawn, transfer function plotted against that line. example point linearity, maximum deviation from best-fit line describes integral nonlinearity converter. Integral nonlinearity also found summing integrating errors that occur with same polarity. strict definition measure maximum deviation actual transition points A/D's transfer function from chosen straight line (ideal, best-fit endpoint).
Magnitude (dBFSR)
-100 -120
640k
1.28M Frequency (Hz)
1.92M
2.56M
FIGURE Dynamic Specifications.
DYNAMIC SPECIFICATIONS Dynamic specifications expressed frequency domain, often using Fast Fourier Transforms (FFTs) derive specifications. order easily recognize where these specifications found FFT, refer Figure This particular derived from ADC614, 14-bit 5.12MHz sampling converter. input frequency this test 2.35MHz sine wave. fundamental input signal shown 2.35MHz, which frequency analog input. Note that power down from full scale. This known headroom (E), which used avoid clipping input signal case offsets from converter input signal generator. Headroom most testing typically 0.5dB. purposes illustration, headroom been expanded Figure Spurious-free dynamic range (SFDR) converter defined distance from fundamental amplitude peak spur level output frequency spectrum, necessarily limited harmonic components fundamental. average noise floor derived from both average noise converter itself. ideal noise floor expressed 6.02n 1.76 10log(m/2), where resolution, points noise performance converter itself expressed signal-to-noise ratio, SNR. signal power input fundamental, noise nonfundamental harmonics Nyquist band, excluding Theoretical 6.02n 1.76, where resolution good rule thumb acceptable converter multiply resolution six. example, good 8-bit should 48dB, 12-bit A/D, 72dB. Because very difficult scale down noise amplifiers used internal circuitry high resolution (12-bits) converters, "times rule thumb does hold these higher resolution converters. such high resolution converters, also somewhat dependent upon input signal frequency. given sampling frequency, theoretical quantization noise bandwidth input frequencies from given q/n, where weight number bits. When ratio input signal frequency sampling rate frequency decreased, quantization noise dispersed over narrower bandwidth, resulting increase noise over analog input bandwidth. Figure plot versus input frequency Burr-Brown's ADS602, 12-bit 1.0MSPS sampling converter. There very little degradation input frequency increases this converter. higher speed higher resolution converters, there will more degradation with increasing input frequencies. This primarily difficulties reducing wideband noise sample-and-hold well problems reducing internal noise.
Other dynamic specifications interest include total harmonic distortion (root-sum-square power fundamental's harmonics), signal-to-noise ratio with distortion (SINAD) which includes harmonic power calculation effective bits (ENOB), alternative expression SNR. useful approximation ENOB given ENOB (SNR 1.76dB)/6.02
(dB)
Input Frequency (kHz)
Figure Input Frequency ADS602. SYSTEM ACCURACY RESOLUTION selection process should normally start with determining required accuracy converter, which indicated overall accuracy requirements complete digitizing system. First all, fundamentally important define difference between resolution accuracy. Resolution only indicates what theoretical accuracy does imply accuracy given level. n-bit converter capable converting infinite range analog input values into finite range digital steps, where resolution converter. Table illustrates relationship between number bits values LSBs some common input ranges.
VALUE BITS CODES 1024 4096 16384 65536 262144 1048576 RANGE 78.1mV 19.5mV 4.88mV 1.22mV 305µV 76.3µV 19.1µV RANGE 19.5mV 4.88mV 1.22mV 305µV 76.3µV 19.1µV 4.78µV RANGE 7.81mV 1.95mV 488µV 122µV 30.5µV 7.63µV 1.91µV
TABLE Values Resolution Input Range. Accuracy used describe close converter comes meeting theoretical resolution. Accuracy converter limited theoretical quantization noise, discrete nonlinearities transfer function, additional sources noise converter circuitry. example determining system accuracy time domain, assume goal measure temperature with span 1000°C within accuracy 0.25°C. required
system resolution will 1000/.25, 4000 codes. Selecting 12-bit converter will provide resolution 4096 codes. accuracy, assuming error converter one-half LSB, will 0.244°C. Unfortunately, converter only element affecting accuracy digitizing system. Often contained front-end analog signal conditioning pathway instrumentation amps, op-amps, multiplexers drive amplifiers. total error budget found computing root-sum-square errors signal conditioning components. example 12-bit system described above, assume following errors shown Table first order approximation, total error this system would 0.0147%. ±10V input range, this would imply error 2.93mV. Considering (20V) need have 4000 increments (1000°C/0.25°), system must accurate (20/4000). This data acquisition system adequate (typically) application requirements. case frequency domain accuracy, there will pre-existing requirements maintaining spectral purity which will user selecting proper converter.
ERROR SOURCE Instrumentation Multiplexer Drive Converter TYPICAL PART INA114 MPC508 OPA602 ADS7806 TYPICAL ERROR 0.003% 0.0025% 0.01% 0.01%
sample rate, problems must considered. First, analog input bandwidth sampling mechanism inadequate process signal without introducing distortion. second problem with Nyquist rate sampling aliasing. Most input signals contain harmonics fundamental, which will digitized converter. Additionally, there interactions between highfrequency input harmonics clock signals inside converter, causing unwanted harmonics digitized. usually necessary filter input harmonics using low-pass band-pass filter. Passing input signal close Nyquist while attempting filter harmonics above Nyquist requires rigorous "brick wall" type filter, which prohibitively expensive. preferable select converter whose sample rate several times greater than analog input bandwidth, avoid expensive highorder input filters. When designing multiple channel system, cost beneficial single higher speed place multiple converters. cost higher speed monolithic industrial converters come down considerably, enabling user realize large cost reduction multiple channels systems. There also benefits reducing cost input filtering, discussed previous paragraph. ANALOG INPUT SIGNAL obviously necessary know nature analog input signal prior selecting proper converter. Some important considerations include: signal Does signal contain discontinuities? What signal's characteristic source impedance? signal noisy? What signal amplitude? First all, consider whether signal slowly varying rapidly varying. Very slowly varying signals also considered especially conversion rate high. example, 100kHz input looks like 10MSPS converter. Slowly varying signals will generally require input sample-and-hold circuit, also will work well with many different architectures. signals, more effective consider frequency domain performance, since digitizing waveforms opposed voltage levels (DC). many applications, absolute scale errors unimportant, possibly saving money user. Does signal contain discontinuities? choice architecture usually limited "single-shot" type converters (such SAR, subranging, flash) since converters which continuous (delta-sigma, integrating, VFC, dual slope) tend integrate signal discontinuities, giving false outputs. What characteristic source impedance signal? Most converters require dynamic source impedance, which discussed detail "Drive Require5
TABLE Typical Errors 12-Bit Data Acquistion System. CONVERSION SPEED Conversion speed indicates fast converter will operate. sampling converters, conversion rate often expressed samples second. example, ADS7804 accepts conversion clock 100kHz, said have sample rate 100kSPS. Conversion time also expressed terms frequency units time. 100kHz converter conversion time 10µs. main elements consider when selecting sample rate input signal bandwidth required update rate. When digitizing signal, Nyquist rule must followed. Nyquist rule states that sampling rate must least twice that input signal bandwidth interest. This does mean fundamental input frequency must limited one-half sample rate; only refers bandwidth input signal. ability process fundamental input signals which greater than Nyquist allow undersampling. Techniques undersampling discussed detail article, Benefits Undersampling, published magazine, July 1994. Exercising converter close Nyquist rate some drawbacks. Although converter capable digitizing signal bandwidths between one-half
ments" section this application bulletin. There some advantages matching converter's input impedance source impedance reduce distortion problems caused reflections. input signal noisy, best consider using integrating type A/D, since integration acts reduce noise. However, most integrating converters have fairly slow sample rates analog input bandwidth. input signal both fast noisy, user some options, such driving with integrating amplifier, using bandpass filter reduce input noise, using high speed averaging results, digitally filtering results DSP. Generally speaking, slow input signals, using type integrating converter very cost-effective solution. signal amplitude should closely matched analog input range A/D. This done maximize dynamic range converter. example, 12-bit converter with input range selected, value 4.88mV. would ineffective only small part that range, example, input signal better solution would select converter with more optimal input range, insert gain block front (keep mind errors which gain block will introduce). Many high speed converters, process voltage breakdown limitations, have small input ranges. signal bandwidth small high degree accuracy needed, advantageous consider using lower speed with larger input range. ENVIRONMENTAL CONDITIONS Environmental conditions digitizing system often predetermined. Since generally possible compromise those conditions, important select converter which will guaranteed operate required accuracy levels within system environment. addition environmental conditions, system have limited power supplies, terms voltage current. frequency systems, specifications interest include offset drift, gain drift, linearity drift. Offset drift often specified bipolar zero error drift case converters with bipolar input ranges. dynamic systems, system will have wide temperature variation under operation, must have dynamic specifications such SFDR guaranteed over required temperature range.
PARAMETER Temperature Range Gain Error Gain Drift Offset Error Offset Drift Error ADS7803BP -40°C +85°C 0.25 0.2ppm Typical 0.25 0.2ppm Typical ADS7804PB -40°C +85°C 5ppm Typical 2ppm Typical 0.45
possible solution obtaining good performance over wide temperature range would select with autocalibrating architecture. These converters contain internal calibration circuitry which allows very small offset, gain linearity errors. However, autocalibrating converters guarantee performance over full temperature range without additional calibration cycles. Also, when using this type converter, user must allow certain period allow calibration take place. strong argument made using standard converter with external offset gain adjustment, those adjustments stable over long periods time. Table compares typical 12bit autocalibrating A/D, ADS7803, with 12-bit nonautocalibrating device, ADS7804. Although initial errors ADS7804 appear large, should noted very easy null these errors out, life tests have shown errors very stable over long periods. Another point consider when selecting converter specific temperature range whether temperature specified ambient (TA), case (TC). Most low-power CMOS converters specified tested ambient temperatures, while faster bipolar converters specified with case temperatures. converters which specified with case temperatures, very helpful heat sink provide improved temperature performance, since case specification negates heat dissipation benefits gained through heat sink. Finally, should noted that older converters typically specified only room temperature, with drift coefficients given only gain offset parameters. Most modern converters have single specification-full temperature range, which provides user with excellent worst-case specification. Another area concern related environmental conditions package type. Hermetic packaging, whether metal bucket CERDIP package, generally provide most resistance hostile environments where high temperatures humidity pose threat long term reliability silicon circuits. However, with advent hermetic passivation, many plastic packages offer very good moisture endurance. well worth time consult detailed reliability report plastic packaged device, cost savings substantial. should assumed hermetic package always more reliable. SAMPLING MECHANISM Track hold circuits used enhance dynamic performance converters, where input signal changing rapidly converter maintain good linearity. Track hold circuits often referred sample hold. circuits identical when hold command direct-coupled. term "sample hold" used when hold command coupled. practical purposes, terms interchangeable. discussion converters, function thought sample mechanism front converter.
TABLE III. Comparison Errors Over Temperature Between Autocalibrating Non-Calibrating Devices. ADS7803BP, errors shown after calibration cycle.
SFDR MODEL ADC774/SHC5320 ADS774 ADC1674 ADS7804 1kHz 10kHz 45kHz 1kHz
SINAD 10kHz 45kHz 70.5
TABLE Examples Sampling Distortion Input Frequency. track hold circuit used reduce aperture time sample system (sampling mechanism combination with converter). Converters industrial high speed ranges (12-bits, >10kSPS) usually built with architecture which requires input held constant during conversion cycle. Architectures employing iterative conversion include successive approximation (SAR) subranging. Parallel converters such flashes also benefit from sampling mechanisms, since time delays comparators identical. tolerance iterative architecture changes input levels very limited. example, 12-bit 1MSPS converter theoretical Nyquist rate 500kHz. However, without track hold circuit, accuracy level one-half limits input frequency only 38.9Hz! excellent detailed explanation track hold circuits specifications found Burr-Brown Application Bulletin AB-027, "High Speed Data Conversion". remainder this discussion will focus socalled "sampling converters". CMOS converters said inherently sampling. This function architecture, which traps charge from input signal capacitor array. Details this architecture found Burr-Brown Application Bulletin AB-178, "CDAC Architecture Plus Resistor Divider Gives ADC574 Pinout With Sampling, Power, Input Ranges". technique seems straightforward, unfortunately, bulletproof. quick glance data sheets many these converters reveals distortion problems high input frequencies. This distortion inherent nonlinearities converter. problem lies with nonlinearities switches capacitor array, primarily problems matching RON. These problems manifest themselves higher input frequencies, dV/dt across switches increase. This distortion inherent nonlinearities converter, since track hold circuit guarantees converter will always signal (assuming there reasonable droop rate associated with track hold circuit). Early recognition this phenomenon some clever design techniques allowed BurrBrown provide sampling CMOS converters with very good Nyquist rate performance. These parts called "ADS78xx Family", starting with part number ADS7804. Table shows comparison distortion several generations sampling systems. more detailed explanation sampling distortion phenomena, refer Burr-Brown's "Application Seminar Fall 1994" handbook, pages 5.71 through 5.80.
AD1674 monolithic BiCMOS device manufactured Analog Devices which included this table demonstrate another implementing sampling converter. that architecture, track hold circuit been designed with bipolar devices, yielding "true" track hold with good performance. bottom line when selecting sampling certain converter will meet distortion goals system's input frequencies.
SECONDARY CONSIDERATIONS
MULTIPLE CHANNEL SYSTEMS selection process converter begins with elements compromise, where systems needs must met. investigated secondary considerations, where designer ability combine elements both system design selection. first point consider cost complexity tradeoff multiplexing. system multiple channels, immediate assumption should made that multiplexed system best approach. traditional multiplexed system, many errors introduced. simple diagram multiplexed system shown Figure When designing this type system, care must taken reduce errors caused mismatches different channels. example, minimize errors caused multiplexer, components must selected with proper impedances. input multiplexer needs driven with source impedance, outputs should drive
Analog Inputs
MPC508 OPA671 ADS7804
Digital Data
Channel Select Timing Circuit Convert Command
FIGURE Traditional Analog Multiplexing System.
RSWITCH
RSWITCH CHOLD
CHOLD
+2.5V Typical CMOS Sample ADS7804 Sampling
FIGURE Comparison Input Structures. very high load impedance. Additionally, bias current load interact with multiplexer causing voltage offset errors. error budget system limited, more cost effective multiple converters. 1995, quantities, price 12-bit 100kHz converters under $10, while 16-bit 100kHz converters priced under $30. REFERENCE converters require voltage reference. reference determines full scale range A/D. voltage reference either internal external. some cases, manufacturer allows user access reference, either drive external circuitry input user-defined reference. general, internal reference valuable function user. addition cost saving, there will less board "real estate" such converter. case multiple channel systems, beneficial external reference, since drift reference dominates gain drift converter. However, references created equally. Particularly, some CMOS converters, requirements reference least reference value where part specified) unusual value, available off-the-shelf reference. these cases, user will need implement voltage divider, which takes board space, allows additional noise could introduce drift problems. There also some components which different reference values specify performance. recommended reference some common value, which will hold down cost complexity. DRIVE REQUIREMENTS Several points must considered when driving converter, impedance matching, charge injection, noise reduction accuracy. bipolar input without track hold circuit, input summing junction comparator which connected internal digital-to-analog converter. This node essentially dynamic impedance that changing throughout conversion. drive amplifier must have enough output impedance fairly high frequencies introduce errors. CMOS sampling converter, input basically driving switch. switch changes from hold mode track mode, there some amount charge injection. drive amplifier must have sufficient output current fast settling time drive charge injection pulse. Figure models different CMOS input structures, showing both "traditional" type used Burr-Brown's ADS7804. Note resistor divider input ADS7804. divider combination with more efficiently designed switch greatly reduces charge injection. typical value current spike traditional structure 20mA, where ADS7804 structure approximately 250µA. This will lessen requirements (and cost) drive amplifier. input structure ADS7804 typical "ADS78xx Family" with different resistor values providing different input ranges. order introduce excess noise into system, drive amplifier noise sources should considered. minimum, drive amplifier must have better than theoretical limit converter. Fortunately, virtually modern amps have noise performance much better than 12-bits, finding amps with good 16bit noise performance difficult task. However, important keep mind noise power sources additive. determine noise power, convert values from voltage (divide calculate 10x). Then calculate root-sum-square return values This calculation will show that will cause degradation converter. with improvement over converter will reduce overall 1.8dB, while with 12dB improved will cause overall drop 0.27dB. amplifier also cause gain accuracy problems does have adequate open-loop gain. There must substantial amount gain over input signal bandwidth. simple example need wide-bandwidth drive seen Figure which plots ratio pole frequency input frequency needed maintaining 0.25LSB accuracy. This particular plot applies only simple, single-pole system. inspection, bandwidth requirements increase substantially high-resolution converters. Wide bandwidth amps improve accuracy maintaining output impedance over entire input signal bandwidth.
1500
digital data from converter controller include following: Data Output Status (Busy) Data Output intuitive; however, with some devices, output coding programmed into straight binary, two's complement binary, others. detailed explanation coding formats found Burr-Brown's Application Bulletin AB-175, "Coding Schemes Used with Data Converters".
Number Bits
1200
FIGURE Ratio First Pole Input Frequency Required Maintain 0.25 Accuracy. INTERFACE OUTPUT FORMATS Another secondary consideration which merits advance planning digital interface. There control lines converter well digital output information which have many different possible configurations. primary signals which used control sampling converters include: Convert Command (Read/Convert) Chip Enable Chip Select Byte Select Convert Command, often referred Read/Convert, used initiate conversion. Modern converters internally clocked, converter only requires digital transition begin converting. Chip Enable control line, used ADC574 type converters, which must active state allow conversion. disable mode, commands convert ignored. Chip Select inverse Chip Enable. These somewhat redundant lines used combination next generation converters, such ADS78xx. single line, such Chip Select, internally OR'd with convert command. Byte Select used control data comes converter. `574 series, this referred 12/8. This line allows `574 used either 12-bit 8-bit converter. ADS78xx Family, Byte Select parallel output versions controls which data bits which pins. addition these standard control lines, converters with serial output formats require data clock.
Status Busy) line indicates controller when conversion being performed. When Status line changes states, data from previous conversion becomes valid. Once designer good understanding types signals which will necessary complete digital interface, process selection again reduced checklist: What logic format (TTL, ECL, CMOS)? Some converters specified multiple compatibility. However, designer advised consult logic level specifications ensure true compatibility. Also beware converter interpret undefined states. What width data bus? type controller used indicate 8-bit 16-bit bus. presence 16-bit controller does indicate 16-bit converter. accuracy converter only tied system accuracy requirement. 16-bit needed with 12-bit converter, consider unused inputs avoid introducing errors. there need isolation? analog front connected environment with large common mode voltages transients, usually advisable isolate digital side from possible damage. Analog isolation devices linear 12-bits, 16-bit accuracy goal, best consider isolated digital couplers, either capacitive optical. usually much less expensive isolate single channel data, which preclude answer next question. Should output data serial, parallel, bytes? large extent, answer this question determined questions output data format should compatible with controller bus, isolation needed, serial data format usually presents most cost effective solution. Another advantage serial converter reduced board space. also possible multiplex control signals where space absolute premium.
EXTERNAL DATACLK
BUSY
SYNC
DATA
(MSB)
(LSB)
FIGURE Conversion Read Timing with External Clock. (EXT/INT Tied HIGH). Read After Conversion.
CONVERSION TIMING element often overlooked selection process timing conversion system. often assumed that simply applying convert command, data valid immediately following conversion. However, many converters operate with pipelined timing. This type timing requires second conversion order have valid output data. This type converter would conducive "single shot" conversions. `574 series allows valid data after completion conversion, provided four specific logic conditions simultaneously. therefore important provide synchronous logic converter operated continuous mode. pipelined timing, second conversion must initiated have valid data. Burr-Brown's ADC603 ADC614 configured have valid data with preset pipeline delays, either conversions later. digitizing
system will have non-continuous conversions, selected converter must have pipelined data outputs, some external circuitry must designed simulate subsequent conversions required obtain valid data. Figure illustrates timing serial pipelined converter. Figure illustrates timing non-pipelined condition, such ADS7800. Figure illustrates pipelined timing parallel converter, ADC614. SUMMARY This bulletin examined process selecting converter digitizing system. checklist both primary secondary factors presented, with detailed explanations parameters. Other application bulletins will provide more detail examples those selection factors. Through checklist, designer should able narrow down choices fast logical manner.
BUSY tDBC Converter Mode Acquire Convert tHDR Data Data Valid Hi-Z State tDBE Acquire Data Valid Hi-Z State Convert
FIGURE Convert Mode: Pulse Outputs Enabled After Conversion.
Nanoseconds
Convert Command Start Conversion tCID Data Output High High
Start Conversion tDSU(5) tCID tCVD
Start Conversion tCID tDSU tCVD
tCVD(2)
Valid Data
Invalid Data
Valid Data
Invalid Data
Valid Data
Invalid Data
Data Output High
Valid Data
Invalid Data
Valid Data
Invalid Data
Valid Data
Invalid Data
Internal Sample/Hold Command
Hold
Sample
Hold
Sample
Hold
FIGURE Basic Conversion Timing.
REFERENCES Burr-Brown Databook: 1995 Data Conversion Products, Burr-Brown Corporation, Tucson, 1994 Clayton: Data Converters, Halsted Press, York, 1982 Michael Demler: High-Speed Analog-to-Digital Converters, Academic Press Inc., Diego, 1991 Burr-Brown Applications Handbook, Burr-Brown Corporation, Tucson, 1994 George Hill: Autocalibration Fact Fiction, EDN, Cahners Publishing, 1992 Burr-Brown Applications Seminar, Burr-Brown Corporation, Tucson, 1994 Watson Swager: Evolving ADCs Demand More From Drive Amplifiers, EDN, Cahners Publishing, Sept 1994
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