NUD3048 simple versatile MircoIntegrationdevice, containing power MOSF

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NUD3048 simple versatile MircoIntegrationdevice, containing power MOSF

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AND8166/D Power Good Circuits Using NUD3048
NUD3048 simple versatile MircoIntegrationdevice, containing power MOSFET, zener gate clamp, gate resistor. MOSFET rated increasing versatility. This application note details design Power Good circuits swap controllers that don't have internal circuit, drain referenced circuits side controllers. schematic NUD3048 shown Figure
Drain NUD3048 Gate
Gate
Source
Figure Basic Circuit Diagram
Power Good Circuits
swap controllers normally provide power switching power supply. often desirable hold operation switching supply until input capacitor been fully charged. This signal called Power Good
signal. Many swap controllers contain such signal, however, some not. side controllers that have Power Good signals, have them referenced side input bus. This done practical considerations integrated circuit design. Unfortunately, this useful feature power converter, since this same ground that converter will operation. Figure shows such system. system ground lower side current sense resistor, approximately same potential source power FET. ground power converter connected drain FET, when conducting, power converter ground essentially same system ground. However, when off, power converter ground same potential input voltage. Since converter ground potential vary with respect system ground, desirable have Power Good signal that referenced converter ground. method achieving this opto coupler which driven Power Good signal, driving with output generate "floating" Power Good signal that referenced converter ground. alternate solution that more cost effective circuit proposed this application note.
DC-DC Converter System UVLO Drain MOSFET Sense Resistor
OVLO
Controller Gate Sense
Figure Side Swap Controller
Semiconductor Components Industries, LLC, 2004
September, 2004 Rev.
Publication Order Number: AND8166/D
AND8166/D
standard definition Power Good will used this application note that signal will high impedance state when output capacitor fully charged Power Good, signal will impedance when output capacitor fully charged.
Power Good Referenced Drain (for controllers with Power Good signal)
NUD3048 used simple, inexpensive Power Good, drain referenced circuit. following schematic shows device with existing Power Good signal. This circuit uses Power Good signal drive NUD3048. This recommended, that controller Power Good signal will high when drain power high. Power Good signal used, controller Power Good will when drain power
high will require roughly flow through input side disabled converter. Using Power Good signal keeps control signal high impedance state until drain near ground. Therefore, leakage current through dc-dc converter essentially zero. this configuration, while dc-dc converter off, Power Good signal converter, should impedance state. completely this can't occur, since there gate voltage, however, problem since there voltage input power converter. When unit turns drain will capacitor charges. time there drain, Power Good signal will correct state. This will occur before converter adequate input voltage start. Power Good signal converter second inversion stage required shown Figure
Power Good
Power Good
DC-DC Converter
NUD3048
Gate
Figure Drain Referenced Power Good Signal
Power Good Power Good DC-DC Converter
NUD3048
NUD3048
Gate
Figure Drain Referenced Power Good Signal
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Power Good Referenced Drain (for controllers without Power Good signal)
Some controllers come with Power Good signal. Semiconductor NIS5101 integrated swap device falls into this category. This device integrated which switching device.
Power Good signal added this part using slightly different circuit. this circuit zener diode sets reference voltage NUD3048. When drain NUD3048 several volts lower than reference voltage, will turn
Power Good Input Drain NIS5101 Current Limit Input MM3Z5V1 Cdelay DC-DC Converter
NUD3048
Figure Drain Referenced Power Good Circuit
Input Drain NIS5101 Current Limit Input Cdelay Power Good DC-DC Converter
NUD3048
NUD3048
Figure Drain Referenced Power Good Circuit
This circuit requires roughly leakage through input stage power converter operate. some cases necessary bypass input terminals with resistor greater. Since this device will change states when there several volts across drain source leads power desirable time delay assure that capacitor fully charged before turning dc-dc converter. characteristics capacitor input voltage time delay shown Figure This graph shows time delay from time that drain voltage reached final value time that Power Good signal reached final value. general, Power Good signal much higher rise fall time than drain signal, level chosen that signal.
1000
tdelay (ms)
0.01
DRAIN CAPACITANCE (mF)
Figure Time Delay Power Good Referenced Drain Capacitance
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AND8166/D
Note that there minor change delay time level input voltage. Using curve equations, value required capacitor given time delay based family curves approximated following equation:
tdelayb
Where:
3e-6 VIN2 0.0004 0.0165 -0.0002 VIN2 0.0198 0.793
Where timing delay capacitor (mF) tdelay time delay (ms). Figure shows waveforms input, with delay capacitor.
Figure Drain Referenced Power Good Signals
Power Good Referenced Negative Supply (for controllers without Power Good signal)
NUD3048 also used ground referenced Power Good signal controllers without Power Good. These circuits shown Figures
Power Good Input Drain NIS5101 Current Limit Input DC-DC Converter
Cdelay
NUD3048
NUD3048
Figure Ground Referenced Power Good Circuit
Power Good Input Drain NIS5101 Current Limit Input DC-DC Converter
Cdelay NUD3048
Figure Ground Referenced Power Good Circuit
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AND8166/D
time delay added this circuit also, including capacitor shown schematic. gate drive this configuration needs understood order realize that there limitation maximum capacitance allowed delay. waveforms Figure show gate Power Good signals input capacitor. When power applied swap device, there short delay then drain begins change voltage from zero negative input supply voltage. Initially, gate charged, comes quickly. seen waveform that when gate approximately Power Good signal goes low. gate then charges from resistor that internal NUD3048. time constant based this resistance total gate capacitance. When drain voltage equal gate voltage this case), gate begins discharge. When gate voltage drops below Power Good signal goes high. gate capacitor large, gate voltage will before drain reduced that level therefore, Power Good will never change states. recommended that capacitor value exceed this circuit configuration. Figure shows relationships between delay time, capacitance input voltage ground referenced circuits.
1000
DELAY (ms)
0.001
0.01
CAPACITANCE (mF)
Figure Time Delay Power Good versus Capacitance
calculation purposes, curve fitting equations were used quantify relationship between timing delay capacitance this family curves. This solution requires positive solution quadratic formula, with following variables:
Where:
-0.553 2.55 -0.029 6.24 tdelay
Figure Ground Referenced Gate Power Good Signal
delay capacitor value (mF) tdelay drain Power Good time delay (ms). This equation valid values greater than data used this application note were taken with NIS5101 loaded with capacitor. current reach current limit level slow di/dt power FET. Data taken with load capacitances 1000 cause substantial changes timing. variations devices used load differences, timing vary slightly from that shown this document, should verified with actual circuit.
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MicroIntegration trademark Semiconductor Components Industries, LLC.
Semiconductor registered trademarks Semiconductor Components Industries, (SCILLC). SCILLC reserves right make changes without further notice products herein. SCILLC makes warranty, representation guarantee regarding suitability products particular purpose, does SCILLC assume liability arising application product circuit, specifically disclaims liability, including without limitation special, consequential incidental damages. "Typical" parameters which provided SCILLC data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. SCILLC does convey license under patent rights rights others. SCILLC products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure SCILLC product could create situation where personal injury death occur. Should Buyer purchase SCILLC products such unintended unauthorized application, Buyer shall indemnify hold SCILLC officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that SCILLC negligent regarding design manufacture part. SCILLC Equal Opportunity/Affirmative Action Employer. This literature subject applicable copyright laws resale manner.
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NUD3048 simple versatile MircoIntegrationdevice, containing power MOSF

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