Application Note January 2002 AN9992 Author: LaFontaine Func
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HC55185 Ringing SLIC AK2306/2306LV CODEC Evaluation Board User Guide Supplement
Application Note January 2002 AN9992
Author: LaFontaine
Functional Description
This application note intended supplement AMK's Evaluation Board User's Guide. user's guide describes Evaluation Board System software. system includes evaluation board control software 2306.exe. good understanding material user's guide prerequisite this application note. detailed engineering analysis reference design using HC55185 AK2306/2306LV, Application Note AN9991. primary focus this application note illustrate system performance using Wandel Golterman (W&G) PCM4. Reference AKM's users guide additional testing methods. AK2306/2306LV Evaluation Board divided into areas, CODEC area other SLIC area, shown Figures CODEC area consists two-channel AK2306 /2306LV CODEC, switches setting operating mode, on-board clock generation circuit I/F, various serial access modes FPGA creating serial signals. SLIC area consists switches operation modes SLICs (six switches SLIC), jumpers changing signal path terminal connectors connection two-wire port.
This application note will first evaluate performance system configuring jumpers hardware External Clock/PC Control mode. Figure shows required connection between Evaluation Board, PCM4 tester. user prefers evaluate performance first, then skip Test
Verifying Basic Operation
operation Evaluation Board verified performing following tests: Normal Loop Feed Verification Ring Voltage Forward Active State, Hook Ring Voltage Forward Active State, Hook Ring Voltage Reverse Active State, Hook Ring Voltage Reverse Active State, Hook
Loop Supervisory Detection Hook Hook Test Open State, Ground Test Forward Loopback Test Ringing Verification Emulation Phone Conversation Gain Verification-Total System Gain (Digital Digital) Variable Gain/Frequency Receive Gain (Digital Analog) Transmit Gain (Analog Digital) Total Distortion-Receive Gain (Digital Analog)
SLIC
CODEC
PCM4
HC55185 RING
Tip_A/B
AK2306/2306LV
FPGA
External Frame Clock
Ring_A/B
RING HC55185
TX/RX Interface SLIC LOGIC CONTROL PC/ATComputer
Tip_A/B Ring_A/B
FIGURE AK2306/2306LV EVALUATION BOARD CONNECTION PCM4 COMPUTER
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. 1-888-INTERSIL 321-724-7143 Intersil (and design) trademark Intersil Americas Inc. Copyright Intersil Americas Inc. 2002. Rights Reserved PS/2are trademarks Corporation.
Application Note 9992
SLIC PART CODEC PART
J1_A
JP6_A
GND2
VXMT_A
VREC_A
VRS_A
GND2
VCCIO
VCCINT
GND1
Power JP1_A JP2_A SLIC JP4_A JP5_A
J2_A
LOOP
Channel
J3_A S1_A J4_A
JP3_A S2_A S3_A S4_A S5_A
SLIC operation mode S6_A control SWJP7_A
CODEC
FPGA
TSYNC
RSYNC
J15_A J15_B J4_B
BCLK JP7_B
JP3_B
Terminal 2-wire analog port J1_B
JP2_B
SLIC
JP4_B
SR_IF PCM_IF
SYNC
BCLK_FRQ
Channel
J3_B S1_B
S2_B S3_B S4_B
S5_B S6_B JP6_B JP5_B
Analog FPGA control
J2_B
JP1_B
VRS_B
VREC_B
VXMIT_B
Serial access
FIGURE AK2306/2306LV MOTHER BOARD CONNECTIONS
HC55185 SLIC
HC55185 optimized match line impedance, have ring trip threshold 90mA, switch hook threshold 12mA, loop current limit 24.6mA transient current limit 100mA. Programming logic state HC55185 performed toggle switches through SW6. Table lists switch name (referenced SLIC data sheet), switch number (reference board layout), switch function. logic states HC55185 shown Table
TABLE TOGGLE SWITCHES SLIC SWITCH NAME SWITCH BSEL FUNCTION Logic control input Logic control input Logic control input Selects between SHD,GKD detectors (Table Logic control uncommitted switch. Logic switch Selects either high battery supply HC55185 Logic selects battery Logic selects high battery TABLE HC55185 OPERATING MODES MODE Power Standby Forward Active Unbalanced Ringing Reverse Active Ringing Forward Loop Back Open Power Denial E0=1 E0=0
AK2306/2306LV Evaluation Board
AK2306/2306LV Evaluation Board provides evaluate operation AKM's CODEC Intersil's HC55185 Ringing SLIC. Figure shows AK2306/2306LV evaluation board component locations. programming interface illustrated this application note once again External Clock/PC Control mode. function jumpers JP1_A/B through JP7_A/B explained Table
Application Note 9992
AK2306 (5V) Circuit Configuration:
TABLE JUMPER CONNECTIONS JUMPER JP1_A/B JP2_A/B FUNCTION Connects uncommitted switch HC55185 (SW-) directly Ring terminal loopback testing. Connects uncommitted switch HC55185 (SW+) through test load diode terminal loopback testing. Connects supply terminal supply terminal single supply applications. Short Connects external input HC55185 input. Short Connects external input through TRAP network) HC55185 input. Short Connects AK2306/2306LV ringing output HC55185 input. Short Connects AK2306/2306LV receive output HC55185 input. JP5_A/B Short Shorts receive input HC55185 ground. AK2306LV operation only. Short Connects receive output AK2306/2306LV input HC55185. JP6_A/B JP7_A/B Connects HC55185 transmit output AK2306/2306LV amplifier transhybrid balance. Connects GRS_0/1 output AK2306/2306LV VFTN_0/1 input internal transhybrid amplifier (AMPT).
Verify that resistor RIN_A/B open (left JP6_A/B). Verify that capacitor CIN_A/B open (left JP6_A/B). Jumper JP5_A/B shorted Verify RA_A/B 120k. Verify RF_A/B 120k. Verify R8_A/B 49.9k.
JP3_A/B JP4_A/B
AK2306LV (3.3V) Circuit Configuration:
Verify that resistor RIN_A/B 45.3k (left JP6_A/B). Verify that capacitor CIN_A/B 0.47µF (left JP6_A/B). Jumper JP5_A/B 1shorted Verify RA_A/B 42.2k. Verify RF_A/B 30.1k. Verify R8_A/B 36.5k. following evaluation applies both AK2306 (5V) AK2306LV (3.3V). Data presented taken with AK2306 (5V) evaluation board.
Configuring board operation:
Connect PC/AT pin) cable between evaluation board your computer (Figure Microsoft® Windows® higher should installed (Microsoft® Windows supported). Connect PCM4 evaluation board shown Figure Connect power supplies supply jacks evaluation board. Configure SW1, SW2, SW3, SW4, shown Table
TABLE FPGA CONTROL SWITCHES SWITCH Selects mode data format Long Frame (LF) Sets SYNC timing Selects internal BCLK frequency(2.048M) Selects normal operation, selects BCLK from external source (BNC) POSITION
Getting Started
following steps will configure Evaluation board testing AK2306/2306LV HC55185 with PCM4. operation mode selected access AK2306/2306LV internal function registers External Clock Mode (PCM interface operation) Control Mode (Serial interface operation) using proprietary software. other methods control interface serial interface please reference AKM's user's guide. circuit schematics AK2306 AK2306LV different (reference Figures reason different circuits voltage (3.3V) operation CODEC need provide sufficient gain two-wire loop. smaller signal coming from AK2306LV (3.3V operation) needs gained through SLIC, thus variation circuits. evaluation board built with either AK2306 (5V) CODEC AK2306LV (3.3V) CODEC (see Figure placement CODEC board). following check list verify correct components jumper placement CODEC your board.
Application Note 9992
Verify JUMPER positions shown Table
TABLE AK2306 (5V) JUMPER CONNECTIONS JUMPER (CODEC side) (CODEC side) JP4_A/B JP5_A/B JP6_A/B Other Jumpers open Short Short Short Short Open FUNCTION
General Parameters PCM4 shown Table (see Test #5). Initialize software clicking file 2306.exe. internal register data AK2306/2306LV will initialized Register will displayed (reference Table Table lists Register functions more detail. computer terminal, entering will enable user program AK2306/2306LVs: Receive Transmit gains, exercise CODECs power down controls, mute control, interface select, data channel select, A/µ-law select Tone frequency select (reference Table 10). Input register address (column Table decimal form (0-7) function wish program. example, wanted change receive gain channel would type press return.
NOTE: default receive gain 0dB.
TABLE AK2306LV (3.3V) JUMPER CONNECTIONS JUMPER (CODEC side) (CODEC side) JP4_A/B JP5_A/B JP6_A/B Other Jumpers Open Open Short Short Short Open FUNCTION
Configure HC55185 Forward Active mode using SLIC Operation Mode Control Switches S1_A/B through S6_A/B. Reference Table switch positions. (Note: Switch position logic towards board logic towards bottom.)
TABLE PROGRAMING HC55185 OPERATING MODES HC55185 MODE Power Standby Forward Active Unbalanced Ringing Reverse Active Ringing Forward Loopback Open Power Denial (F2) (F1) (F0) (E0) (SWC) (BSEL)
change default values CODEC's functions (Table 10), user must input corresponding number two-digit hexadecimal number. Table used quick reference guide programming gains through CODEC using hexadecimal numbers. lists available programming gains lists corresponding two-digit hexadecimal number that gain three lists binary number that will appear computer screen after user inputs two-digit hexadecimal number. SLIC ready tested.
Microsoft®, Windows® Windows registered trademarks Microsoft Corporation
Application Note 9992
TABLE REGISTER TST13 TST11 TST9 TST7 TST5 TST3 TST12 TST10 TST8 TST6 TST4 TST2 MTCH1 TST1 GA0R4 GA1R4 GA0T4 GA1T4 MTCH0 TST0 GA0R3 GA1R3 GA0T3 GA1T3 TNFQ GA0R2 GA1R2 GA0T2 GA1T2 PDTN ALAWN GA0R1 GA1R1 GA0T1 GA1T1 PDCH1 SEL2B GA0R0 GA1R0 GA0T0 GA1T0 PDCH0 PCMIF
Reserved Reserved
TABLE RERERENCE GUIDE CONVERT GAIN CORRESPONDING HEXADECIMAL NUMBER Gain (dB) Binary
TABLE REGISTER FUNCTIONS Address Name GA0R0 GA0R1 GA0R2 GA0R3 GA0R4 GA1R0 GA1R1 GA1R2 GA1R3 GA0R4 Test mode Please write "0". Test mode Please write "0". Receive gain adjustment -18dB steps 00000: +6dB 11xxx: -18dB Default Function Receive gain adjustment -18dB steps 00000: +6dB 11xxx: -18dB
Application Note 9992
TABLE REGISTER FUNCTIONS (Continued) Address Name GA0T0 GA0T1 GA0T2 GA0T3 GA0T4 GA1T0 GA1T1 GA1T2 GA1T3 GA1T4 PDCH0 PDCH1 PDTN MTDX0 MTDX1 PCMIF SEL2B ALAWN TNFQ Reserved Reserved Test mode Please write "0". CODEC CH0,1 Power down control Power Power RING TONEGEN Power down control Power Power Full Power down Power Power Mute control: VR0.VR1,DX Normal output Mute Test mode Please write "0". Interface select LF/SF data channel select A/µ-law select A-law µ-law Tone frequency select 16Hz 20Hz Test mode Please write "0". Test mode Please write "0". Transmit gain adjustment -18dB steps 00000: +6dB 11xxx: -18dB Default Function Transmit gain adjustment -18dB steps 00000: +6dB 11xxx: -18dB
Application Note 9992 Test Normal Loop Feed Verification
This test verifies correct ring voltages both onhook offhook forward active reverse active states. Loop current ground also verified on-board LEDs. When forward loop back mode initiated internal switches connect load across outputs Ring amplifiers shown Figure
Discussion
HC55185 designed have most positive two-wire terminal (tip forward active state ring reverse active state) fixed voltage. most negative two-wire terminal voltage dependent upon load across ring programmable current limit. Loop supervision provided either switch hook ground detectors. Loop status observed monitoring CR2_A/B board. device operated from either high battery on-hook transmission, during ringing battery loop feed. When operating from high battery, voltages Ring compliant. typical voltage Ring voltage function battery voltage battery voltages less than -60V shown Equation
RING (EQ.
HC55185
RING
RING
FIGURE FORWARD LOOP BACK INTERNAL TERMINATION
When internal signal path provided, current will flow from Ring. current will force causing current flow through CR2_A/B, turning diode.
Measuring Ring Voltages
Configure Hardware Software described section titled Getting Started. Configure HC55185 forward active mode using SLIC operation mode control switches S1_A/B through S6_A/B. Reference Table switch positions. (Note: Switch position logic towards board logic towards bottom.) Measure ring voltages (reference Figure compare those Table (onhook). Terminate RING with load banana jacks RJ11 jack. Measure ring voltages with respect ground compare those Table (offhook 600). Configure HC55185 Reverse Active mode using SLIC Operation Mode Control Switches S1_A/B through S6_A/B. Reference Table switch positions. Disconnect load from across ring. Repeat steps
TABLE RING VOLTAGES Onhook Offhook Onhook Offhook VOLTAGE REFERENCED -3.6 -4.6 -4.6 -5.6 RING VOLTAGE REFERENCED -17.2 -21.1.0 -16.2 -19.7
Most applications will operate device from battery while hook. feed characteristic device will drive Ring towards half battery regulate loop current. light loads, will near Ring will near VVBL Figure shows feed characteristic.
VTR(OC) (VTR /IL) 11.1k
ILOOP (mA)
ILIM
FIGURE FEED CHARACTERISTIC
point y-axis labeled VTR(OC) open circuit Ring voltage defined feed battery voltage.
(EQ.
LOGIC STATE Forward Active -48V Reverse Active -48V
Ground detector operation verified configuring HC55185 open state grounding ring pin. Grounding ring results current that triggers internal detector that pulls output causing current flow through CR2_A/B, turning diode. Forward Loop Back mode provides test capability device. internal signal path enabled allowing both verification. internal terminating resistor tolerance ±20%. HC55185 intended operate from only battery during this mode.
-17.2 -21.1.0 -16.2 -19.7
-3.6 -4.6 -4.6 -5.6
Application Note 9992 Test Loop Supervisory Detection
Verification Switch Hook Detect
previous test Test skip step Configure Hardware Software described section titled Getting Started. Configure HC55185 forward active mode using SLIC operation mode control switches S1_A/B through S6_A/B. Reference Table switch positions. With SLIC either forward active state (Active reverse active state (Active CR2_A/B when ring terminated with when ring open circuit. Disconnect load from across ring.
RING 600K
(EQ. (EQ.
Verification Ground Detect
Configure HC55185 Open mode using SLIC operation mode control switches S1_A/B through S6_A/B. Reference Table switch positions. Grounding ring terminal will verify ground detect when CR2_A/B diode turns
FIGURE LINEAR RINGING MODEL
When input signal zero, Ring amplifier outputs centered half battery. device provides auto centering easy implementation sinusoidal ringing waveforms. Both control Ring outputs available during ringing. This feature allows offsets part ringing waveform.
Verification Forward Loopback
Configure HC55185 forward loop back mode using SLIC operation mode control switches S1_A/B through S6_A/B. Reference Table switch positions. Verification forward loopback operation when both CR2_A/B (SHD) CR1_A/B (ALM) diodes turn
Ringing Input
ringing input, high impedance input. high impedance allows value capacitors coupling ring signal. input enabled only during ringing mode, therefore free running oscillator connected times. When operating from battery -100V, each amplifier, Ring, will swing maximum 95VP-P Hence, maximum signal swing achieve full scale ringing approximately 2.4VP-P signal levels compatible with output voltage range CODEC. digital nature CODEC ideally suits function programmable ringing generator.
Test Ringing Verification
This test will demonstrate ability AK2306/2306LV ring phone through HC55185. telephone only additional hardware required complete this test.
Discussion
HC55185 provides linear amplification support variety ringing waveforms. programmable ring trip function provides loop supervision auto disconnect upon ring trip. device designed operate from high battery during this mode.
Ringing Phone
previous test either Test skip Step Configure hardware software described section titled Getting Started. Configure HC55185 Ringing mode using SLIC Operation Mode Control Switches S1_A/B through S6_A/B. Reference Table switch positions. Keep BSEL this point. Press write CODEC resisters. Then decimal followed This will power ring tone generator. Press write CODEC resisters. Then decimal followed This will ring tone generator 20Hz. Connect phone Channel using RJ11 jack board. Toggle BSEL switch S6_A/B from battery high battery phone will start ring.
Architecture
device provides linear amplification signal applied ringing input, differential ringing gain device 80V/V. circuit model ringing path shown Figure voltage gain from input output 40V/V. resistor ratio provides gain eight current mirror provides gain five. voltage gain from input Ring output -40V/V. equations Ring outputs during ringing given Equations
Application Note 9992
When test completed, BSEL switch S6_A/B low. also need power down ring generator. Press write CODEC resisters. Then decimal followed 04.This will prevent tone from interfering with subsequent tests. Configure HC55185 forward active mode using SLIC operation mode control switches S1_A/B through S6_A/B. Reference Table switch positions.
Connect terminal (connected port PCM4) terminal (connected port PCM4). Verify that Ring tone generator turned off. Press write CODEC resisters. Then decimal followed
Test Emulation Phone Conversation
This test will demonstrate phone conversation between Channel Channel Setting phone conversation accomplished configuring AK2306/2306LV swap mode connecting terminals together (Figure previous test either Test skip step Configure hardware software described section titled Getting Started. Configure both HC55185s forward active mode using SLIC operation mode control switches S1_A/B through S6_A/B. Reference Table switch positions. Configure switch swap mode toggling position shown.
Verification Phone Conversation
Verify phone connection between both channels picking receivers talking. Return switch initial position (Table Reconnect PCM4.
Test Gain Verification
This test will verify gains through AK2306/2306LV HC55185 operating properly. test will show, with receive transmit gains programmed 0dB, Digital Analog gain across both CODEC SLIC equal -1.0 (0dB), Analog Digital gain across both SLIC CODEC also equal (0dB). Both gains will verified performing Digital Digital gain using PCM4.
G4-2
0dBm0(600) 0.7745VRMS
SYSTEM REQUIREMENTS: IMPEDANCE: TRANSMIT GAIN (A/D): +5.0dB RECEIVE GAIN (D/A): INTERSIL HC55185
0dBm0(600) 0.7745VRMS 0.47µF 0.47µF 120K
AK2306 RECIEVE PATH GAIN
0dBm0 (600) 0.7745VRMS
RING
AMPT AMPLIFIER VFTN VFTP TRANSMIT PATH GAIN
66.5K 4.7µF
49.9K 0.47µF
120K
0dBm0(600) 0.7745VRMS
-7.619dBm0(600) 0.32219VRMS
G2-4
0dBm0(600) 0.7748VRMS
FIGURE REFERENCE DESIGN HC55185 AK2306 WITH LOAD IMPEDANCE
Figure shows reference design HC55185 AK2306 with load impedance. Reference Application Note AN9991 detailed engineering analysis reference design.
AMPR AMPLIFIER
0dBm0(600) 0.7748VRMS
Application Note 9992
Total System Gain (D/D)
previous test Test skip Step Configure hardware software described section titled Getting Started. Configure HC55185 forward active mode using SLIC operation mode control switches S1_A/B through S6_A/B. Reference Table switch positions. Terminate ring with load. general parameters PCM4 shown Table PCM4 Interface (port TX/RX. RX-Impedance/ (port 600. TX-Impedance/ (port 600. PCM4 transmit receive channels channel This will enable PCM4 receive transmit data Channel time slot. test channel PCM4 channel Configure PCM4 MODE test. PCM4 D-D, SWP/S (single sweep). Press start test network.
TABLE PCM4 GENERAL PARAMETERS SETTINGS (Continued) General Parameter Special Parameter: Level Display wire Term. Digital Channel Tolerance mask Clock display Mark cont. Setting dBm0 Infinite Time Slot Mark cont. Parm
Verification
Compare results Graph
TABLE PCM4 GENERAL PARAMETERS SETTINGS General Parameter Digital Configuration: General configuration Digital Loop Frame Selection: frame type frame type CRC-4 Multiframe Digital Interface: Line Code Output Impedance Clock Digital nterface: Line Code Input Impedance Digital Words Frame: Frame Words Send Signal Error Insertion Coding: Encoding Setting TX/RX 2M/2Mbps selected OPEN/AUX.SIGN. teleph teleph unbalanced Int. 2048kHz Reset standard values CHAN. Must match address Table Default setting µ-law Parm GRAPH TOTAL SYSTEM GAIN (D/D)
Test Variable Gain Frequency
This test will configure HC55185 loopback mode evaluate AK2306/2306LV HC55185's performance across frequency.
Discussion
Most SLICs HC55185 family feature two-wire loopback testing. During two-wire loopback test, internal resistor switched across ring terminals SLIC. This allows function four-wire four-wire transmission, right subscriber loop, tested.
Variable Gain Frequency (D/A) Test
previous test Test skip Step previous test Test skip Step Configure hardware software described section titled Getting Started.
Encoding Scanner Parameter: VF-Input VF-Output
Must match encoding
Configure HC55185 forward loop back mode using SLIC operation mode control switches S1_A/B through S6_A/B. Reference Table switch positions.
Application Note 9992
general parameters PCM4 shown Table PCM4 Interface (port TX/RX. RX-Impedance/ (port 600. TX-Impedance/ (port 600. PCM4 transmit receive channels channel This will enable PCM4 receive transmit data Channel time slot. test channel PCM4 channel Remove load from across ring. Configure PCM4 MODE test. PCM4 D-A, SWP/S (single sweep). Press start test network.
Test Total Distortion
This test will configure HC55185 loopback mode evaluate AK2306/2306LV HC55185's total distortion.
Total Distortion (D/A) Test
previous test Test skip Step previous test Test skip Step previous test Test #76a/b skip Step Configure hardware software described section titled Getting Started general parameters PCM4 shown Table PCM4 Interface (port TX/RX. RX-Impedance/ (port 600. TX-Impedance/ (port 600. PCM4 transmit receive channels channel This will enable PCM4 receive transmit data Channel time slot. test channel PCM4 channel Configure HC55185 forward loop back mode using SLIC operation mode control switches S1_A/B through S6_A/B. Reference Table switch positions. Remove load from across ring. Configure PCM4 MODE test. PCM4 D-A, SWP/S (single sweep). Press start test network.
Verification
Compare results Graph
Verification
Compare results Graph
GRAPH (D/A) VARIABLE GAIN FREQUENCY
Variable Gain Frequency (A/D) Test
Configure PCM4 MODE test. PCM4 A-D, SWP/S (single sweep). Press start test network.
Verification
Compare results Graph
FIGURE (D/A) TOTAL DISTORTION
GRAPH (A/D) VARIABLE GAIN FREQUENCY
Application Note 9992 Board Schematic
RSENSE FEED AMPLIFIER RSENSE 49.9K 120K VFTN VFTP AMPT AMPLIFIER
RING
INTERSIL HC55185 RECEIVE BLOCK 0.47µF 0.47µF 120K
AK2306 RECEIVE PATH
AMPR AMPLIFIER
FEEDBACK AMPLIFIER IM30 SENSE AMPLIFIER
0.47µF
TRANSMIT PATH
66.5K
FIGURE HC55185 SIMPLIFIED TRANSMISSION CIRCUIT AK2306
FEED AMPLIFIER
BCLK
Application Note 9992 Board Schematic (continued)
RSENSE FEED AMPLIFIER RSENSE 36.5K AMPT AMPLIFIER 30.1K VFTN VFTP
RING
INTERSIL HC55185 RECEIVE BLOCK 0.47µF
AK2306LV RECEIVE PATH
0.47µF 42.2K
FEEDBACK AMPLIFIER IM30 SENSE AMPLIFIER
0.47µF 66.5K
TRANSMIT PATH
45.3K
0.47µF
RECEIVE GAIN FROM +3.3dB TRANSMIT GAIN FROM -9.3dB AK2306LV
VOLTAGE CONNECTION
FIGURE HC55185 DEMO DAUGHTER BOARD SCHEMATIC
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FEED AMPLIFIER
AMPR AMPLIFIER
BCLK
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