Intersil Intelligent Power 50W, 500kHz, Full-Bridge, Phase-Shift,

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AN9506
Intersil Intelligent Power
50W, 500kHz, Full-Bridge, Phase-Shift, Isolated Converter Using HIP4081A
Author: David Hamo
Introduction
Many articles papers have been published recently promoting performance benefits Phase-Shift, Full-Bridge Topology rightly This topology productively utilizes same elements that have been plaguing power supply designers decades, those infamous parasitic components. topology enables designers advantageously employ transformer leakage inductance, MOSFET output capacitance MOSFET body diode, enabling designers easily move their designs upwards frequency. topology offers additional advantages like zerovoltage-switching constant switching frequency, which substantially reduces switching losses. This significant enough eliminate heatsinking power MOSFETS and/or enabling less expensive power devices. Reduced additional benefits, since voltage current switching waveforms much "cleaner" waveform edges switch softly compared conventional pulse width modulation (PWM) techniques. ability move upwards frequency will ultimately reduce overall size lower cost supply. megahertz operation beyond possible with this topology. This truly major advancement topological architecture. requirements this design full bridge configuration, additional inductor resonant operation output structure consisting dual diode rectifier filter. Special thermal substrates required. result, cost savings realized utilizing inexpensive printed circuit board material place elaborate thermal designs. What's more, EMI/RFI filtering requirements heatsinking less rigorous further reducing costs. Therefore, focusing overall system cost, demonstrated that employing this topology does have merit. Presently, there limited phase-shift controllers market, those that available still expensive. Having faced this problem, investigation designing discrete solution performed. What discovered proved encouraging. With cost single ended controller cost logic ICs, generate gating delay functions necessary derive phase-shift control waveforms. What makes this possible Intersil HIP4081A MOSFET driver. HIP4081A capable independently driving four MOSFETs directly, eliminating need traditional drive transformers. HIP4081A also allows additional drive control capabilities unavailable with conventional gate drive transformers. This includes
1-888-INTERSIL 321-724-7143 Copyright
ability vary turn-on delays both upper lower MOSFET switches. This essential feature realizing zero voltage switching (ZVS). result flexibility capacity derive control logic drive signals necessary phase-shift switching. voltage rating HIP4081A 80V, which ideal telecom converters. With added overvoltage protection circuit which turns lower MOSFETS turns upper MOSFETS, further protection supplied system. block diagram full-bridge phase-shift power supply described this application note shown Figure circuit discussed here output power capability 50W, operation scaled upwards 500W range with appropriate power component changes.
HIP4081A Features
HIP4081A member HIP408X family high frequency H-Bridge driver ICs. HIP4081A H-Bridge driver ability operate from 80VDC driving N-channel MOSFET H-Bridges. HIP4081A packaged both Lead Lead SOIC, provide peak gate current drive 2.5A switch 1MHz. combination bootstrap charge-pumping techniques used power circuitry which drives upper halves HBridge. bootstrap technique supplies high instantaneous current needed turning power devices, while charge pump provides enough current "maintain" bias voltage upper driver sections MOSFETs. Since voltages upper bias supply "float" along with source terminals upper power switches, design this family provides voltage capability upper bias supply terminals 95VDC. resistors tied pins HDEL LDEL provide precise delay matching upper lower propagation delays. programmable delay range this device 10ns 100ns. This variable delay capability imperative zero voltage switching will described shortly. Phase-Shift Control Overview number well written papers theory concepts phase-shift conversion, will limit discussion implementation technology. Several papers listed reference section that address phase-shift conversion topics further. full bridge drive control logic required this topology conceptually complex. Figure shows full bridge with
Intersil Corporation 1999
Application Note 9506
FILTER -36VDC -72VDC START-UP CIRCUITRY CURRENT SENSOR
CONTROLLER
PHASE SHIFT CONVERTER LOGIC
HIP4081A
REFERENCE ISOLATION
FIGURE FULL-BRIDGE, PHASE-SHIFT POWER SUPPLY BLOCK DIAGRAM
POWER DELIVERY INTERVAL LEFT TRANSITION INTERVAL
iPRI
FREE WHEEL INTERVAL RIGHT TRANSITION INTERVAL
VPRI
SLEW INTERVAL DRIVE SIGNALS
VPRI iPRI
FIGURE
FIGURE
associated parasitic components essential operation. Figure shows waveforms associated with circuit Figure During phase-shift operation there five states intervals time, that take place half cycle operation. These states will briefly discussed only half cycle bridge will described circuits symmetric operation. Refer Figure during following descriptions time interval identifications. Slew Interval (t0-t2) slew interval time takes primary current reverse directions. This time established level input voltage across primary, load current total inductance primary path, referred resonant inductance. This inductance includes leakage inductance transformer additional inductance primary path. Additional inductance required store enough energy displace capacitive charge COSS
provide realistic transition delay times. term resonant inductance will refer combination transformer leakage inductance additional inductance primary path. Power Delivery Interval (t2-t4) gate drive signals timing diagram associated with full bridge shown Figure power delivery interval phase shift topology similar traditional full bridge converter, that diagonal switches (A&D B&C). This applies full input voltage across primary results power transfer load. amount time these switches directly proportional phase shift between sets waveforms phase between these sets waveforms will change required, regulate output voltage. 100% phase shift will result 100% duty cycle. Conversely, phase shift will result duty cycle.
Application Note 9506
MOSFET output capacitance COSS multiplied approximate average capacitance value during varying drain-to-source voltage. derivation this equation listed appendix Right Transition Interval(t3- second delay called right (C&D) transition time which terminates power delivery interval. This time required displace charge output capacitance leg. converters output inductor current reflected primary therefore source energy which will displace this charge. displacement this charge forces voltage across MOSFET zero (MOSFET occurs during cycles second half), enabling zero voltage switching take place. this case however, mechanism displacement charge resonant, linear since this transition modelled current source reflected output current driving output capacitance. time given
TIME TIME
FIGURE
Freewheel Interval (t4-t5) Notice following from Figure There time when switches will conduct simultaneously switches will conduct simultaneously. This state called "freewheel" interval. This phase-shift controller perform control without changing frequency, unlike other quasi-resonant topologies. load requirements change, freewheel time changes accordingly. freewheel time increases with light loads decreases with heavy loads. other words, freewheel time controller idle until next appropriate state comes along. During freewheel time, reflected load current circulated through switches voltage across primary zero. Figure shows droop primary current during this time. This caused conduction losses circulation path output inductor ripple current.
(EQ.
Voltage applied full bridge Peak primary current Resonant capacitance Transition time right interval Both energy sources required displace charge drain-to-source capacitances MOSFETs load dependant. This makes difficult maintain zero-voltageswitching light loads. However, this fact does pose serious problem described later section titled Design Considerations.
Transition Intervals (ZVS Delay)
Left Transition Interval (t0- method involves displacement charge drain-to-source capacitances MOSFETs occurs differently legs bridge. left (A&B) transition interval begins after freewheel state initiate power delivery interval. This time required displace charge output capacitance leg. left leg, source energy that displaces this charge stored transformer's leakage inductance plus additional inductance primary path (the total being resonant inductance). displacement this charge forces voltage across MOSFET zero (MOSFET occurs during cycles second half), enabling zero voltage switching take place. Here MOSFETs output capacitances form resonant circuit with resonant inductance. charge displaced time equal one-fourth resonant period. result, left transition time given
Phase-Shift Drive Derivation
Deriving phase-shift drive control logic from standard off-the-shelf controller straight forward. controller chosen Unitrode UC3823A. This chosen high speed operation start-up current. However, low-cost, high-speed controller could used. Figure shows logic circuit used derive phase-shift control logic. timing diagram this circuit shown Figure Notice that clock output from UC3823A shown only reference purposes. clock signal used circuit, however, many following equations will include clock period tCLK their composition. clock period tCLK 2µs. output from controller clocks flip-flop which outputs waveforms outputs, which become a&b. same time logic signal exclusive ORed with outputs flip-flop. This generates waveforms shown timing diagram. Normally "slivers" developed waveforms. They come about from time delay caused clock signal propagation time through flip-flop. Using advanced CMOS logic maximum sliver width will approximately 15ns. While possible generate sliverless waveforms with additional circuitry, this does present problem since small capacitors filter slivers
(EQ.
Transition time left interval Transformer leakage inductance additional inductance Resonant capacitance resonant capacitance given
XFMR
(EQ.
COSS MOSFET output capacitance CXFMR Transformer capacitance
Application Note 9506
shown Figure signals passed through gate which configured non-inverting buffer become a&b. This match timing drive outputs with drive outputs. These signals then input into HIP4081A which turn drives MOSFET H-Bridge. drive signals drive Left-Leg bridge while drive signals drive Right-Leg bridge.
74ACT86
VREF 74ACT86 HIP4081A 74ACT86 INPUT 74ACT86 VREF
timing delays determined Equation Equation Once requirements known HIP4081A turn delay times accordingly resistor values HDEL LDEL pins. Normally, left right would like controlled independently. With HIP4081A upper lower device delay times controlled independently. This causes requirement that both delay times identical. Typically left delay slightly longer than right delay. this case HDEL LDEL longer two. This concept will explained further section titled Design Considerations.
FROM CONTROLLER
74ACT74
Design Process
that proper control signals phase-shift topology have been realized time begin working through design power supply Figures begin, overall power supply requirements have been defined Input Voltage -36V -72V Output Voltage Output Current Switching Frequency 500kHz
FIGURE
flip-flop gates receive their power from controllers VREF terminal UC3823A, which outputs +5V. power requirements logic devices well within reference output current capabilities. However, reference should properly by-passed.
tCLK CONTROLLER CLOCK OUTPUT
74ACT74 OUTPUT
DELAY (EQ. DELAY (EQ.
HIP4081A OUTPUT DELAY (EQ. DELAY (EQ.
FIGURE PHASE SHIFT TIMING DIAGRAM
POWERRTN BOOT
BF720T1 T37-8 100V
BZX84C75LT1
ILIM
1N4148 VREF VREF 0.1µF VREF OUTA OUTB ILIM RAMP PGND
0.1µF 100V
0.1µF 100V
BZX84C12LT1
Application Note 9506
74ACT86
470pF VREF
74ACT86 74ACT86
2.2K -36V -72V
UC3823A
0.1µF
0.22µF 470pF
74ACT74
74ACT86 2200pF 2200pF
47µF 6.49K
MMBT3904LT1 619K 0.1µF
4.7K
VREF
POWERAIL
FDBK
FIGURE
+5.0V ILIM 0.470 POWERRTN BOOT MBRS1100T3 MBRS1100T3 0.1µF HDEL LDEL 0.1µF 10µF 100K 100K 5.11K POWERAIL 33µF 470µH DT1608-474 VREF ISO1 PS2701-1 IRFR120 BAV70LT1 IRFR120 MBRB2535CTL 0.1µF IRFR120 100V EPC-19 T44-6 2.0µH 2200pF MMBT5401LT1 MOLEX 22-59-1310
-36V -72V MOLEX 22-59-1310
IRFR120
T50-8 100µF
+5V/10A 0.47µF
Application Note 9506
4.99K 0.1µF COLL ISET UC39432
FDBK
HIP4081A
FIGURE
Application Note 9506
Power Semiconductor Selection overall goals this supply maintain lowest profile size possible. This important module manufacturers, well board level OEMs. selected form factor close standard along with minimum profile. voltage current requirements along with size constraints lead choice four Intersil IRFR120s full-bridge switches. They have rDSON 0.27, breakdown voltage 100V available surface mount TO-261(D-PAK)package. output rectifier diode chosen Motorola MBRB2535CTL available (D2-PAK)TM. This rectifier chosen because very forward voltage drop, slightly over 0.3V 10A. This important consideration since most power loss output rectifier. Transformer Design Maintaining form factor requirements mentioned earlier lead choice EPC-19 ferrite core from TDK. this application transformer size limited core loss. transformer will designed temperature rise 50oC. That coupled with maximum ambient temperature 50oC, transformer reach maximum temperature 100oC. PC40 material chosen since curie temperature excess 215oC, core loss switching frequency. Design curves given with core material (TDK catalog #BAE-030D) show temperature rise given core loss. design curves indicate that core temperature will rise 50oC with core dissipating 800mW. This value core loss only excludes copper losses. core losses copper losses were equally distributed transformer core loss will 400mW. Therefore, determine maximum core loss limitation this design:
CORE CLOSS 400mW CLOSS 1.047cm
EPC-19 transformer operating 250kHz, 25oC rise will occur operating with peak flux density 1200G. maximum primary duty cycle reach maximum time will 0.8t, then maximum flux density change within time span 0.8t/2 will 2400G. voltage across transformer been reduced anticipated voltage drop caused MOSFET switches rDS(ON). minimum primary turns from Equation
10Turns 0.227 2400
most ideal case:
non-ideal case:
MOSDROP RECT
Rearranging solving secondary turns ratio:
RECT MOSDROP 2Turns
(EQ.
(EQ.
Using curves once again PC40 material, core loss flux density curves indicate that peak flux density core loss mW/cm3 approximately 1200 gauss. switching frequency 500kHz with full-bridge topology core flux swings half switching frequency. Therefore transformer switching frequency will 250kHz while operating first third quadrants hysteresis curve. remaining transformer design procedure straight forward. From Faraday's Law:
(EQ.
Where voltage across transformer windings (Volts) number primary turns Iron area core (cm2) Core flux density (Gauss) time which flux changed
transformer turns ratio been designed yield given flux density excursion, thereby maintaining limits temperature range. Next, wire size must determined copper losses must exceed 400mW limit rise core temperature 50oC. primary windings current density circular mils ampere used. secondary current density approximately circular mils ampere used because higher current fact that there only windings side required secondary. Using these current densities, wire size requirements become 20AWG primary 19AWG secondary. secondary, eight strands 28AWG magnet wire will used, yielding equivalent circular area 19AWG. With wire selected, copper loss including skin effects increased wire resistance 100oC, approach 300mW. Therefore expect maximum temperature rise slightly less than 50oC. transformer wound interleaving secondary halves between primary. first half secondary will wound first primary will wound next. remaining secondary half will wound finally, auxiliary will wound.
Design Considerations
that transformer been designed good time determine transition times. This will allow turn delays properly zero-voltage-switch-
D-PAKand D2-PAKis registered trademark Motorola
Application Note 9506
take place. However, choosing left transition time requires much thought because this time function many variables. Therefore, before going further some concepts need clarified equation will derived that will allow this value chosen quickly correctly. Figure primary bridge voltage, primary current secondary voltage waveforms shown. Notice that primary secondary duty cycles different. From these waveforms following relationship determined:
From Figure
Performing substitution multiplying since there such transitions period, loss duty cycle secondary then equal
LOAD
(EQ.
Solving
LOAD
Loss duty cycle secondary side. Primary voltage duty cycle. Secondary voltage duty cycle effective duty cycle. loss duty cycle secondary side concept. This loss caused time takes change direction primary current (t2-t1). Therefore imperative that resonant inductance value excessive. Otherwise, this might require larger turns ratio, since primary duty cycle could reach maximum value while secondary duty cycle incapable sustaining appropriate output voltage. This concept could stumbling block unsuspecting. This leads importance deriving equation terms this loss duty cycle which enables bounded properly. This turn, will lead correct value chosen left transition tLL. Deriving equation t2-t1 equal time takes primary current slew. Since know slope sluing primary current, following equation determined from Figure
LOAD
(EQ.
have expression total resonant inductance terms loss duty cycle that value easily determined. From beginning design maximum secondary duty cycle been chosen 80%. Using this value selecting duty cycle loss 15%, will yield maximum primary duty cycle 95%. leakage inductance transformer approximately 500nH total resonant inductance calculation becomes:
0.15 2.55µH RINDUCTOR 2.05 0.5µH 2.05µH
Before determining left transition time resonant capacitance must calculated. IRFR120 MOSFET switches have COSS capacitance equal 130pF transformer primary capacitance approximately equal 10pF. Using Equation resonant capacitance calculated:
183pF
left transition then calculated using Equation1:
2.55
LOAD
34ns
VPRI
DtCLK
previous calculation alternative expression could have been used:
LOAD
(EQ.
SLOPE tCLK VSEC DtCLK DetCLK
making left transition 34ns will cause maximum primary duty cycle approximately full load with minimum input voltage applied. This allows margin variations assuming nearly 100% duty cycle possible. These numbers adjusted easily previous equations your particular needs. that resonant inductor left transition time have been selected, right transition time needs determined. turns that maximum right transition time occurs during maximum input voltage load boundary called operational limit. operational limit point which power supply longer maintains zero-voltage-switching. This normal function this topology. mentioned earlier, energy sources (resonant inductance output inductance) required dis-
FIGURE
Rearranging:
LOAD
Application Note 9506
place charge drain-to-source capacitances MOSFETs load dependant. Therefore some load value less than maximum, energy stored these sources will less than adequate displace this charge. This point which converter will longer operate mode. This best exemplified Figure Figures show left transition formed. Figure shows that energy larger than energy required displace capacitance charge. Figure shows operational limit where energy equal energy required displace capacitance charge. Figure shows energy capable fully displacing capacitance charge. same scenario true right transitions they will ramp linear rate their energy source output inductance stated earlier.
power which supply stops zero-voltage-switching 16.6W, well below Po(max), which within design goal requirements. right transition determined using Equation
20ns 0.662
left-leg transition takes 34ns right-leg transition takes 20ns. These values programmed turn delays HDEL LDEL resistor values HIP4081A. previously mentioned, since HIP4081A controls upper lower delay times, both HDEL LDEL should equal longest delay time. This time will 34ns. Resonant Component Selection core material selected resonant inductor chosen high core loss characteristics. Micrometals powdered iron core T44-6 resonant frequency interest, 7MHz (FRES=1/(4xtLL)).
FIGURE
more important maintain higher loads reasons. first more obvious that switching losses greatly reduced. second reason because free-wheel time minimum during full load. Therefore circulation reflected load current during free-wheel time shortened thereby reducing losses free-wheel circulation path. During lighter loads power dissipation MOSFET switches should significant switching losses begin manifest smaller primary currents during lighter load values. this reason, design goal maintain operation down half maximum output power (25W). should noted that higher converter power levels (>200W) necessary place saturable inductors series with anode leads output rectifier. This extends range zero-voltage-switching very power levels further improving efficiency. This concept discussed great detail several listed references. equation which determines minimum current required operation
output filter inductor another Micrometals powdered iron core, T50-8 chosen core loss 500kHz. This material lowest core loss other material they offer. result, also most expensive. Another core which used T50-52. material slightly higher core loss less expensive.
Effects Variations MOSFET Parasitic Output Capacitance
MOSFETs parasitic output capacitance, COSS vary from part part, from manufacturer manufacturer. However, this variability does cause severe aberration operation converter. only noticeable effect slight decrease efficiency. This loss efficiency factors. first most significant capacitive turn-on losses. This caused energy required displace charge output capacitance when there insufficient energy resonant inductor perform this task. This indicated first term Equation other losses simply turn-on turn-off losses which normally occur zero voltage switching effect. These turn-on turn-off switching losses caused slight movement resonant peak with respect programmed delay time COSS varies from nominal value. This cause drain-to-source voltage occur simultaneously with drain current during portion switching time, thereby decreasing efficiency. This indicated second third terms Equation Figure shows curve output capacitance function drain-to-source voltage. COSS measured drain-to-source voltage 25V. This voltage point designated VOSS. this voltage point COSS equal 162pF indicated curve. Maximum variations COSS Intersil IRFR120 ±20% measured value shown Figure However, changes COSS much more significant when select-
critical
(EQ.
critical
0.662A 2.55
minimum primary current maintain switching 0.662A. what this means terms output power following calculation performed:
Critical 0.662 0.662 3.31A Critical 3.31A 16.6W
Application Note 9506
same MOSFET from different manufacturer. This because each MOSFET manufacturer different processes, resulting changes from typical value. This value significantly different from typical value shown data sheets. Therefore, good idea work closely with your supplier obtain measured value COSS. measured value COSS VOSS 162pF shown Figure Therefore, expect worst case variation ±20% from this value indicated Figure will shown that even large changes COSS, total power dissipation converter will impacted greatly. should pointed that initial design proceeded with COSS 130pF stated data sheet typical value. later determined that measured value 162pF. This difference noticeable effect converter performance confirming that moderate variations COSS have little effect converter performance.
1000
efficiency will slightly degraded only COSS value turns larger than target design. counter this effect possibly larger COSS, could simply program delays slightly longer than calculated values. should pointed that chosen 10ns Equation generate curves Figure conclusion this topic, once measured value COSS known, expect worst case change ±20%. This change insignificant converters performance shown Figure Once vendor selected transition delays determined, delays forgotten about.
COSS +20%
405pF PSWLOSS, (COSS, VIN)
COSS
162pF 195pF 405pF
405pF +150%
COSS CAPACITANCE (pF)
195pF 405pF 162pF 195pF 162pF 195pF 162pF OUTPUT CURRENT
+20% -20% DRAIN-TO-SOURCE VOLTAGE
FIGURE NON-ZVS OPERATION
FIGURE COSS CURVE INTERSIL IRFR120
Performance
Figures show primary voltage current waveforms converter taken load current input voltage 48V. indicated below, frequency primary side 250kHz while secondary side frequency will twice primary 500kHz. primary current scale 0.5A division yielding 3AP-P waveform. Notice clean these waveforms are. This significant benefits zero voltage switching. Additionally, primary current rectified secondary voltage shown Figure illustrate erosion secondary duty cycle mentioned earlier. erosion approximately 200ns, yielding reduction secondary side time. calculated value input difference This exemplifies importance using Equation calculate erosion secondary. secondary side have same problem with more classic topologies. moderate snubber added rectifier reduce ringing. graphs Figures show percent regulation percent efficiency. Percent regulation excellent. Over full input voltage load range, maximum change output voltage 54mV. During moderate high output current efficiency predominately range. actual measurements correlated very closely with loss analysis performed this converter prior design. While this topology offers lossless switching, conduction
Figure shows effects increased switching losses varying COSS input voltage (essentially VDS). Equation used determine these curves derived appendix From curves Figure11, seen that even large variations impact switching losses that great, especially converter operating near full load. Again, needs understand their application determine much variation COSS tolerated. Hopefully Figure11 will help give understanding impact COSS variation converter switching losses.
COSS VOSS SWLOSS tCLK
(EQ.
SWLL SWLL SWRL SWRL -tCLK tCLK
From Equation seen that switching loss zero resonant inductance enough energy displace output capacitance switching losses zero operation. first term Equation, decreasing values output capacitance advantage. Here resulting energy resonant inductance exceeds energy needed displace capacitance charge. Decreasing capacitance also means that delay time transition will longer than necessary. This significant effect converter efficiency.
Application Note 9506
losses increase. What this topology offers this configuration input output voltage ability increase switching frequency, while same time, providing much cleaner waveforms. breakdown power loss data given Table From these figures target specific areas optimize converter greater efficiency. instance, current sense resistor replaced with current transformer improved efficiency.
RUN: 50.0ms/s AVERAGE FREQ 250.26kHz
RUN: 100ms/s AVERAGE FREQ 251.52kHz
MATH2
20.0V
500ns
10.0mV 0.5A/DIV
500ns
FIGURE
FIGURE
RUN: 100ms/s AVERAGE FREQ 252.403kHz REGULATION FREQ 506.033kHz
10.0 0.5A/DIV 10.0V 500ns
OUTPUT CURRENT
FIGURE
FIGURE
EFFICIENCY
OUTPUT CURRENT
FIGURE
Application Note 9506
TABLE LOSS ANALYSIS 48V, IOUT MOSFET Full-Bridge Conduction Losses Output Diode Losses Switching Losses Power Transformer Losses Output Inductor Losses Resonant Inductor Losses Current Sense Resistor Losses Snubber Losses Miscellaneous Losses Total Power Loss Efficiency 0.8W 0.75W 0.57W 1.2W 0.38W 1.24W 11.94W
plots shown Figure illustrate progression zero voltage switching. first second plots show that delay time skewed from nominal value. This because HIP4081A delay made excessively large illustrate resonant half sinusoid. Ideally want delay period resonant frequency. This delay time determined Equation final plot shows delay optimum point proper zero voltage switching. Notice absence ringing compared when non-zvs operation taking place! plots Figures illustrate zero voltage switching switch switch first plot Figure voltage across zero during turn-on switch Here HIP4081A driving high side FET. Notice step this waveform. This step voltage being supplied HIP4081A bootstrap capacitor which turns switch second plot shows gate drive switch along with same phase node, switch Here, voltage across switch zero during turn-on switch remaining plots Figure mechanism same, here MOSFETS being turned off. these waveforms that delay time nearly 34ns calculated application note.
RUN: 1.00GS/S AVERAGE
Operating converter with load greater than will require heatsink attached output rectifier. addition, full bridge require larger copper area small heatsink heat removal.
RUN: 1.00GS/S AVERAGE
20.0V
50.0ns
20.0V
50.0ns
FIGURE 17A. HIP4081A DELAY LARGE SKEW
FIGURE 17B. HIP4081A DELAY MODERATE SKEW
RUN: 1.00GS/S AVERAGE
20.0V
50.0ns
FIGURE 17C. HIP4081A DELAY PROPER OPERATION FIGURE NON-ZVS PROGRESSION, SWITCH 48V, IOUT
Application Note 9506
RUN: 2.00GS/S AVERAGE RUN: 2.00GS/S AVERAGE
VOLTAGE PHASE NODE VGATE SWITCH
VOLTAGE PHASE NODE
VGATE SOURCE SWITCH
20.0V
20.0V
25.0ns
20.0V
5.00V 25.0ns
FIGURE 18A. VOLTAGE ACROSS SWITCH DURING TURN-ON SWITCH
FIGURE 18B. VOLTAGE ACROSS SWITCH ZERO DURING TURN-ON SWITCH
FIGURE ZERO VOLTAGE SWITCHING SWITCH TURN-ON
RUN: 2.00GS/S AVERAGE VOLTAGE PHASE NODE VOLTAGE PHASE NODE RUN: 2.00GS/S AVERAGE
VGATE SWITCH 20.0V 20.0V 25.0ns
VGATE SOURCE SWITCH
5.00V
20.0V
25.0ns
FIGURE 19A. VOLTAGE ACROSS SWITCH ZERO DURING TURN-OFF SWITCH
FIGURE 19B. VOLTAGE ACROSS SWITCH ZERO DURING TURN-OFF SWITCH
FIGURE ZERO VOLTAGE SWITCHING SWITCH TURN-OFF
Conclusion
This topology exciting surprisingly simple implement. been shown that HIP4081A used successfully realize phase shift full-bridge topology. only does HIP4081A drive H-bridge also capable delivering needed transition delay times required this topology. addition, simple logic block used convert single ended output into required phase shift logic drive signals. design process developed enable designers accomplish their designs. This achieved deriving essential equations exposing concepts. Following these procedures should allow designers obtain success when incorporating this topology. What's more, much mystery this topology been removed, especially area parasitic functionality within design. shown that output capacitance variation does have great impact overall performance. shown that effects this variation determined easily with graphical methods.
References
Guicho Hua, Fred Lee, Milan Jovanovic, Improved FullBridge Zero-Voltage-Switched Controller Using Saturating Inductor, IEEE Transactions Power Electronics, October 1993. J.A. Sabate, V.Valtkovic, R.B. Ridley, F.C. Lee, B.I. Cho, Design Considerations High-Voltage High-Power Full-Bridge ZeroVoltage-Switched Converter, IEEE APEC 1990 Dhaval Dalal, 500kHz Multi-Output Converter with Zero Voltage Switching, IEEE 1990 Abraham Pressman, Switching Power Supply Design, McGraw Hill, 1991 M.M. Walters, W.M. Polivka, Extending Range SoftSwitching Resonant-Transition DC-DC Converters, International Telecommunications Energy Conference, October 1992. Bill Andreycak, Designing Phase Shifted Zero Voltage Transition Power Converter, Unitrode SEM-900 Power Supply Design Seminar Handbook. Edwin Oxner, Power FETS Their Applications, PrenticeHall, 1982 George Danz, HIP4081, High Frequency H-Bridge Driver, Intersil Application Note, Publication AN9325
Application Note 9506 HIP4081A Converter
Application Note 9506 Material List
C11, C17, C20, C23, C15, C18, C19, C25, C26, IS01 R21, R11, R12, R13, R14, R23, R40, 100µF 0.47µF 0.1µF 100V
Appendix
Derivation Equation equation resonant frequency:
0.1µF 100V 33µF 470pF 47µF 0.22µF 2200pF 10µF BAV70LT1 BZX84C75LT1 MBRS1100T3 MBRB2535CTL BZX84C12LT1 1N4148 PS2701-1 MOLEX 22-59-1310 MOLEX 22-59-1310 MICROMETALS T50-8 2.0µH MICROMETALS T50-6 470µH COILCRAFT DT1608 IRFR120 INTERSIL BP720T1 MMBT5401LT1 MMBT3904LT1 5.11K 4.99K 619K 6.49K 2.2K 100K 0.470 4.7K EPC-19 MICROMETALS T37-8 HIP4081A INTERSIL UC39432 UC3823A 74ACT86 74ACT74
left transition takes place within period resonant period.
Derivation Equation output capacity COSS depletion-dependant capacity whose value depends upon impressed drain-to-source voltage. Therefore drain-to-source capacitance value over varying drain-to-source voltages approximated
Where between most MOSFETs, COSS measured output capacitance drain source voltage VOSS. Most manufacturers measure this value VOSS 25V. Derive Energy substitute current:
Capacitance function drain-to-source voltage:
VDS, dVDS
Integrating:
-2-n
Evaluate INTERSIL IRFR120:
Notice that output capacitance multiplied factor 2/3. phase-shift topology there output capacitances (COSS) parallel during each resonant transition. Therefore effective energy resonant capacitance multiplied becoming:
Application Note 9506
Derivation Equation When energy resonant inductor equal energy resonant capacitance critical point operation reached. When energy resonant inductor below stored MOSFET capacitance energy there Non-ZVS operation. When above there operation. Therefore:
Determine switched Skew:
VMIN
essentially VIN, where maximum input voltage.
Where MOSFET switching time during nonzvs portion waveform. This caused delay long shown delay short.
Critical
Derivation Equation energy resonant capacitance displaced energy resonant inductance When this happens capacitive turn loss equal zero:
SWLL OSS,
Determine switched Skew: From Equation
PRICRIT SWRL
Since essentially VIN, power required displace resonant capacitance
SWLOSS XFMR
Combining:
-SWLOSS
XFMR
Substituting multiplying since there such transitions period:
SWLL OSS, SWLL SWRL SWRL
SWLOSS
From Transition times:
PRICRIT
Intersil semiconductor products manufactured, assembled tested under ISO9000 quality systems certification.
Intersil products sold description only. Intersil Corporation reserves right make changes circuit design and/or specifications time without notice. Accordingly, reader cautioned verify that data sheets current before placing orders. Information furnished Intersil believed accurate reliable. However, responsibility assumed Intersil subsidiaries use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Intersil subsidiaries. information regarding Intersil Corporation products, site http://www.intersil.com

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