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Freescale Semiconductor, Inc.
Introduction HC16 HC11 Users
Ross Mitchell Applications Group Motorola Ltd., East Kilbride, Scotland
Introduction Basic Design Philosophy M68HC16
M68HC16 (HC16) highly modular device family based CPU16 16-bit core. CPU16 core true 16-bit design, with architecture that will very familiar M68HC11 (HC11) users. resemblances HC11 core design deliberate move provide upgrade path those 8-bit 68HC11 designs that require increased power 16-bit CPU. Many features HC16 CPU16 core will HC11 users, these changed features that this document aims explaining. HC16 provides software upgrade path HC11 users while giving full hardware compatibility with asynchronous address data found 32-bit microprocessors. basic HC11 easily recognizable Figure with number additional registers enhancing flexibility core. addition multiply-accumulate (MAC) block (Figure provides user with greatly improved digital signal processing (DSP) capabilities. Many architectural changes have been made improve performance CPU. hardware interface has, however, been radically changed. This compatible with asynchronous address/data interface found
Motorola, Inc., 1992, 2000
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Freescale Semiconductor, Inc. Application Note
68000, 68020, 68300 Families devices. greatly reduce external logic, module called system integration module (SIM) been designed provides signals required control external bus. HC16 built with 0.8-micron double metal HCMOS (highdensity metal-oxide semiconductor) process. following discusses various differences likely encountered user M68HC16 experienced using HC11. covers architecture, software compatibility, hardware HC16 device. detailed table contents follows. Since there number technical references available, will assumed reader these hand.
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Table Contents
Introduction Basic Design Philosophy M68HC16. Concept Intermodule (IMB) Explanation Basic Concept Basic Starting Position Modularity. Choosing Module List Designs On-Chip Peripherals CPU16 System Integration Module (SIM). General-Purpose Timer Module (GPT) Standby (SRAM) Serial Communications Interface (SCI) Serial Peripheral Interface (SPI). Analog-to-Digital Converter (ADC) Ports
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Application Note Table Contents
Basic CPU16 Core Architecture Differences Look Non-DSP Parts Core CPU16 Register Registers. Program Data Space. Examination Part CPU16 Core HC16 n-Tap Filter Bits Source Code Compatibility
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Basic Approach Source Code Compatibility. Changes Detail Addressing Modes Timing Changes Assembly Code Differences Between HC11 HC16. Enhancements CPU16 Source Code 20-Bit Addressing. Moving Data without Affecting Accumulators. RMAC. Stack Operations Difference between 16-Bit Signed Branch Pipelining 32-Bit Arithmetic Comparison HC11 HC16 Code Benchmarks Check List Changes HC11 Code Initialization HC16 Device Control SRAM Initialization Procedure Stack Initialization. Register Initialization. Mode Selection During Reset. Reset Operation Vectors, Stack Operations Exception Routine Address User-Defined Vectors. Vectors HC11 Users Reset Status Register
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Freescale Semiconductor, Inc. Application Note
Exception Handling (Interrupts) Interrupt Request Handling Module Design Influence Conversion from HC11 HC16 Code Setting Internal Exception HC11 Timer Initialization HC16 Code Interrupt Initialization. Initializing QSPI Setting External Exception.
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Periodic Interrupt Real-Time Interrupt Different Exception Levels Arbitration. Same Exception Level Multiple Exception Events Prioritization Schemes Exception Routine Entry Latency External Hardware Interfacing Asynchronous Synchronous Wait States. Fast Termination (Synchronous Timing) Using Chip Selects 8-Bit 16-Bit Read/Write Access 8-Bit Wide Memory Devices Hardware 8-Bit 16-Bit Addressing Using Single-Chip Select VDDE VDDI VDDA Minimum Required Connections Debugging Tools. Background Mode Evaluation Board Appendix Appendix Appendix
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Application Note Figures, Tables, Examples
Figures, Tables, Examples
Figure Title Page 68HC16Z1, 68HC16Y1, 68332 Block Diagrams 68HC11E9 68HC11K4 Block Diagrams QSPI Model HC11 Register Basic HC16 Register Minus Registers HC11 CPU16 Condition Code Registers. Registers Instruction Flow Instruction Operation Schematic Diagram PLL. Multiple Interrupts 16-Bit Address Read Write Access with CSBOOT. Shows Suggested Decoupling Close HC16 Pins Possible These Pairs Power Pins HC11 with External Memory. HC16 with External Memory. MC68HC11E9 Device MC68HC16Z1 Device. Simplified HC16 Timing Diagram
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Table Title Page Initial Modules Available Family. Example Baud Rates Possible with System Clock 16.78 Accumulator Instructions Compared HC11 Instructions Modified CPU16 Implementation Move Instruction Register Initialization Support Instructions HC11 Stack Control Instructions CPU16 Stack Control Instructions Registers that Must/Should Written after Reset List 1-Time Write Bits/Registers Configuration Reset Vector Table Definition HC16 Generating Autovector Initializing Watchdog Periodic Interval Timer Setup Exception Handler
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Freescale Semiconductor, Inc. Application Note
Example Title Page HC16 Code with Data Accesses Same 64-Kbyte Segment HC16 Code Data Accesses Across Adjacent 64-Kbyte Segments HC11 Code Average 10-Bit Values N-Tap Filter HC16 HC16 Moving Data from Result Register Table HC11 Code Calculate 16-Bit Times Bits Divided Bits HC16 Code Perform 16-Bit Times 8-Bit Divided Bits HC11 (8-Bit 8-Bit 8-Bit) 9-Bit. HC16 (8-Bit 8-Bit 8-Bit) 9-Bit. MC68HC16Z1 Initialization Routine HC11 Initialization Code Definition HC11 Vector Table Actual HC16 Vector Table HC11 Code Timer Initialization HC16 Initialization Interrupts Initialization QSPI HC11 Timer Output Compare Interrupt Routine HC16 Timer Output Compare Exception Handler Initialization Code 16-Bit Addressing External Memories
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Application Note Concept Intermodule (IMB)
Concept Intermodule (IMB)
Explanation Basic Concept
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HC11 device made number functionally different modules which connected together form fully operational microcontroller. These modules range from (central processor unit) (read-only memory) very complex timers communications interfaces. HC16 employs same techniques, goes step further standardizing shape interface modules another. Each module must designed that there absolute minimum change connection rest design, this means that intermodule connections external connections standardized. This achieved intermodule (IMB) which standard interface internal modules HC16 68300 Families microcontrollers. consists data lines, address lines, numerous control lines that available modules device. general terms, similar function address data computer system. This very like 68020 asynchronous uses handshaking between sending receiving modules allow data transfer occur. Thus, very large number modules accommodated simply with little design effort each variant HC16 68300. system integration module (SIM) simply logic required asynchronous address data takes care both internal external activity with little differentiation between them. also provides control interrupt events includes number systemwide functions such system monitors clock generation. thing that will notice that concept results "back bone" device, with visible track stretching across middle device. Figure showing block diagrams HC16 devices 68HC16Z1 68HC16Y1 example back bone effect. Compare these design 68HC11E9 68HC11K4 devices Figure note irregular shapes HC11 devices.
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Freescale Semiconductor, Inc. Application Note
CPU16
CPU16
CPU32
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68HC16Z1
68HC16Y1
68332
Figure 68HC16Z1, 68HC16Y1, 68332 Block Diagrams
TIMER
TIMER 24-K
12-K EEROM EEROM 68HC11E9 68HC11K4
Figure 68HC11E9 68HC11K4 Block Diagrams
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Application Note Concept Intermodule (IMB)
Basic Starting Position
couple modules always exist intermodule (IMB) device. itself course, absolutely required. good idea, then must choose system integration module suit application. After that, there free hand choosing modules.
Modularity
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HC11 HC05 customer will well acquainted with CSIC (customer-specified integrated circuit) approach. This simply where customer specifies custom integrated circuit, will often have completely module that must designed support customer's particular needs. Where design does involve module designed, complete design layout process take little three months. Most this time spent integrating customer-specified modules incorporating them into rectangular piece silicon, where each module often irregular shape. intermodule (IMB) allows even faster integration specifying standard shape interconnectivity modules. lies along center device each module fixed height such that only width silicon will vary according number width each module. Figure illustrates devices HC16 Family compares them with 68332, first CPU32-based device. relatively simple matter assemble appropriate modules give best utilization silicon, then that remains connect external pads device modules. consequence, 6-month design period turn vastly more complex devices than HC11 HC05 comparable time frame. modularity each module normally requires that there customization module that precisely same functionality that module another device. This restriction modules themselves therefore designed provide maximum flexibility user. requirements MCUs demanded, library modules increases. Currently, available many more design. Table brief list first modules become available.
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Freescale Semiconductor, Inc. Application Note
clear result this modular approach that initialization each module very important certainly more complex than would case HC11 device. majority cases, registers preinitialized value that would either safe expected normal operation. HC11 offers approach called fixed chassis customerspecified integrated circuit (FCCSIC), where basic device chassis pinout restricted combinations there area silicon known white space which available random logic design. There such equivalent Family, often flexibility modules will account much logic required these cases.
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Table Initial Modules Available Family
CPU16 CPU32 SCIM SRAM TPURAM EEROM MCCI 16-bit CPU, based HC11 core 32-bit CPU, based 68020 core System integration module (chip selects, clock, system protection) Single-chip (Address/data become port lines.) Static with low-voltage standby operation emulation SRAM Timer processor unit, 16-channel timer with RISC-type core 16-k 48-k FLASH EEROM modules 48-Kbyte module queued module SCIs single 8/10-bit, 8-channel converter
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Application Note On-Chip Peripherals
Choosing Module List Designs
Making choice modules complex task. essence, comes down choosing functionality required application building device available blocks. Since functionality each module very specific, application often broken down match these functions. choice then between three modules becomes much more obvious. Each module reference manual easy collect relevant data each module function analysis system's design application.
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Family HC16 devices grows, increasingly likely that user will find device close ideal requirements application. This makes task defining variant HC16 much simpler, since combination critical modules assessed easily.
On-Chip Peripherals
HC16 consists number different modules, each with specialist function which will combine give functionality powerful microcontroller. external interface obvious elements such device known CPU16 system integration module (SIM), this case. These connected just other module would important consider functions core separate from another, with communication intermodule (IMB). Much this document directed giving reader basic understanding features CPU16 modules since these basic blocks version HC16. Many other modules exist today, with many more design. following, therefore, will concentrate peripherals found MC68HC16Z1, since this device most closely resembles very popular MC68HC11E9 device.
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Freescale Semiconductor, Inc. Application Note
CPU16 core module like other modules. true 16-bit with some novel features. pseudo-linear address capability Mbyte user program, while data space built from banks segments Kbytes. CPU16 also boasts digital signal processor (DSP) functionality with full capability, allowing 16-bit 16-bit multiply addition into 36-bit wide accumulator single 720-ns instruction. programmer's model seen Figure Figure Figure
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System Integration Module (SIM)
system integration module most complex modules available interfaces between internal device modules external peripheral devices system. chip selects, address lines, data lines, seven interrupt pins, numerous control lines, digital (input/output) ports, periodic interval timer, arbitration logic, system monitors, system clock generation (phase-locked loop). chip selects large piece basically comparators that check bits address some control signals such address strobe, read/write, address space type. This then allows handshake signal called DSACK signalled external interface section SIM, this turn completes cycle. comparator also used generation AVEC, signal indicate presence autovector (interrupt event). monitor disabled after reset, when enabled will flag (BERR) long delay cycle completion, possibly write read from non-existent memory. allows 32.78-kHz crystal connected external oscillator pins then multiply frequency prescaler feedback circuit from phase detector. this multiplied clock that becomes system clock. prescaler 6-bit modulus prescaler with separate divide-by-2 divide-by-4 selections generate system clock ranging from 16.78 from 32.78-kHz input clock. This allows
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Application Note On-Chip Peripherals
user arrange exact frequency timers, periodic timer, SCI, etc., suit application. Figure block diagram PLL. significant portion this document aims explain operation SIM. basic blocks external pins seen Appendix following very brief overview HC11-like peripherals found HC16 device. These peripherals offer many improved features over HC11 equivalent, user must refer appropriate reference manuals take full advantage increased functionality.
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General-Purpose Timer Module (GPT)
general-purpose timer (GPT) module based mainly HC11F1 HC11E9 timer. three input captures, four output compares, input capture output compare channel, pulse accumulator input, 8-bit (pulse-width modulation) outputs clock input. similar 68HC05B6's PWM. differences are: Maximum (240 timer clock (2-MHz HC11 maximum 500-kHz timer clock) pulse accumulator input separate from channel. PWMs additional. These more sophisticated than HC05B6 PWMs, since they have prescaler addition fast/slow mode. They not, however, have modulus counters HC11G5 device. 8-bit PWMs from maximum 32.78 down just These cannot, however, concatenated case with HC11G5. clock come from external called PCLK. input capture output compare pins have alternate functions digital capability, pins used discrete output pins.
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Freescale Semiconductor, Inc. Application Note
Standby (SRAM) SRAM mapped anywhere 1-Mbyte addressable program data space. move SRAM, STOP (RAM enable/disable) must set, meaning that disabled, RLCK (RAM base address lock) must have been written state. (This write-once register bit.) write base address registers RAMBAR ($FFB04) ($FFB06) will allow user place base address anywhere memory. good place SRAM address $F0000, since this accessed same instructions that access module registers they, too, situated bank SRAM either program program data space. This allows user decide whether code used data storage. using only program space, initialization important. Since there write data from registers program space, necessary initialize program data space first then copy user code into RAM. RASP (RAM array space) then will only execute code from until RASP cleared once more. application running code from would possibly where user slow maybe 8-bit wide external memory system wishes internal 16-bit wide fast termination execution critical piece code that requires short cycle times. Remember that program space-only mode there possibility storing data from registers.
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NOTE:
SRAM disabled standby mode which operates whenever VSTBY approximately volts higher than VDDI supply. avoid this situation, VSTBY grounded SRAM will always powered from VDDI.
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Application Note On-Chip Peripherals
Serial Communications Interface (SCI)
queued share module registers will found together. operates almost exactly same HC11K4. This means that modulus register generate baud rate receive transmit have very wide range baud rates allow variable system clock frequency possible from PLL. HC11E9 much simpler baud rate generator that fixed divide ratios that sometimes cause problems users wishing device 3-MHz speed still require 9600 baud, example. With modulus baud rate divider, simple equation used generate appropriate baud rate. Baud rate system clock where divide ratio selected baud rate register ($FFC08).
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Table Example Baud Rates Possible with System Clock 16.78
Nominal Baud Rate 500,000 38,400 19,200 9600 4800 2400 1200 Actual Baud Rate 524,288 37,449 19,418 9533 4810 2405 1200 Percent Error +4.9 -2.5 +1.1 -0.7 +0.2 +0.2 Baud Rate Register Value 1748 4766
Clearly, used bring these small errors minimum.
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Freescale Semiconductor, Inc. Application Note
other features that have changed relatively minor. option wired mode output, will automatically generate parity check parity receiving data. Also, there status register called that when receiver busy, indicating that another message being received.
Serial Peripheral Interface (SPI)
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basic from HC11 recognizable after good long look QSPI. There great many additional features this module which have been grafted onto HC11 type SPI. should relatively easy convert HC11 over QSPI function, more likely that user will wish take advantage improved functionality this module particular reduce unnecessary intervention transfers. queued 16-word transmit 16-word receive storage within module. actual function remains unchanged, each words transmit/receive controlled 8-bit command register that autonomously controls operation without direct control from CPU. queue send receive number words bytes manipulate external slave select lines continuously burst then await further intervention from CPU. obvious applications control display external converter, name just external peripherals. Here there need send receive several bytes/words data regularly QSPI handle this with little control once started. case A/D, data could read from receive queue interrupt service routine would just continue collect data automatically. queue control byte associated with each sets receive transmit registers made from 4-bit fields. first field controls protocol second field determines which external devices being accessed.
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Application Note On-Chip Peripherals
Thus, possible determine number bytes transferred, whether there delay after transfer, delay from slave select transmission start, whether disable slave devices between data transfers each transfer. Also, four slave select lines changed each transfers. addition number bytes, QSPI transmit/receive number bits from eight thus making communication with 10-bit external much simpler.
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baud rate definition very similar that baud rate. Again, there modulus prescaler, 8-bit BAUD field SPCR0 (QSPI control register register $FFC18. equation follows: Baud rate system clock baud) where baud values ranging from 256. reset, baud register preset giving baud rate with 16.78-MHz system clock. maximum baud rate 4.19 minimum baud rate (with 16.78-MHz system clock).
$FFD00
$FFD20
$FFD40
RECEIVE DATA
TRANSMIT DATA
COMMAND CONTROL
$FFD1E
$FFD3E
$FFD4F
Figure QSPI Model
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Freescale Semiconductor, Inc. Application Note
Analog-to-Digital Converter (ADC) basically same MC68HC11E9 functionality, does have number significant improvements. example, module operate 8-bit 10-bit converter (taking longer convert 10-bit result). results eight channels read from their individual data registers three different data representations: right justified unsigned, left justified unsigned, left justified signed. This means that there total 16-bit wide registers eight channels 10-bit A/D. data formatting intended make application functions much simpler providing results signed form. left justified unsigned value gives easy access most significant 8-bit result, while right justified unsigned value gives easy handling 10-bit result. Conversion times eight bits bits. other features such continuous sampling, single conversion stop, grouping four eight channels much same HC11G5.
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Ports
Each module HC16 digital port lines alternate function primary module function. parallel digital port which operates precisely same port HC11. Since modules designed completely separate, port line control registers scattered across register/address map. some cases, individual control port pins completely different registers. example this timer processor unit (TPU), where digital control comes from control each timer channel.
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Application Note Basic CPU16 Core Architecture Differences
Basic CPU16 Core Architecture Differences
Look Non-DSP Parts Core CPU16 close inspection CPU16 register Figure reveals very close similarity corresponding registers HC11 Figure There several additional registers, with accumulator index register largely being duplicates accumulator index register respectively. register completely new, result extending address range CPU. condition code register changed quite support enhancements CPU.
ACCUMULATOR ACCUMULATOR INDEX REGISTER INDEX REGISTER STACK POINTER PROGRAM COUNTER FLAGS CONDITION CODE REGISTER ACCUMULATOR
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Figure HC11 Register Accumulators differ slightly from another. Accumulator only 16-bit accumulator (unlike accumulator which also considered 8-bit accumulators). seen Table most instructions apply equally accumulators logical, comparative, data movement instructions identical both accumulators; however, there some differences with arithmetic instructions. Just with HC11, there decrement increment 8-bit registers since there 16-bit decrement HC11, there such instruction CPU16. Accumulator therefore, associated decrement/increment instruction. Additionally, instruction complemented instruction CPU16; however, there instruction
NOTE:
decimal adjust only operates accumulator similar way, reading from/writing possible only from accumulators 8-bit 16-bit operation, respectively.
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Freescale Semiconductor, Inc. Application Note
implications this continue concentrate accumulator primary 16-bit accumulator accumulator results calculations. accumulator accumulator instructions take same number clock cycles execute. This further emphasized addition types instruction CPU16. These 16-bit offset indexed instruction accumulator offset indexed instruction. There only 16-bit signed offset available accumulator instructions whereas accumulator possibility unsigned 8-bit offset signed 16-bit offset index register. 8-bit offset directly compatible with HC11 normally 2-byte opcode, making very efficient normally 2-cycle (120 instruction. accumulator offset index register significant improvement over HC11. This will allow offset calculation signed 16-bit value used directly access memory location. This allows index register remain pointing data field rather than save pointer address then restore later required HC11. Example Example show this instruction might used.
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Application Note Basic CPU16 Core Architecture Differences
(EK) (XK) (YK) (ZK) ACCUMULATOR ACCUMULATOR ACCUMULATOR INDEX REGISTER INDEX REGISTER INDEX REGISTER STACK POINTER PROGRAM COUNTER EXTENSION FLAGS EXT. ADDR. EXTENSION EXTENSION EXTENSION ACCUMULATOR
DIIRECT PAGE/ INDEX REGISTER
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(SK) (PJK)
CONDITION CODE REGISTER
EXTENSION
REGISTER
STACK EXTENSION
REGISTER
Figure Basic HC16 Register Minus Registers Table also shows that there 32-bit instructions. These primarily intended with 32-bit registers found some modules bus. particular, configured have 32-bit registers which must written memory access cycle. Example example this instruction program example. shown later this section, there also special uses accumulator when using multiply accumulate functions CPU16.
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Freescale Semiconductor, Inc. Application Note
Register
first sight, there little difference between (condition code register) HC11 that HC16. Most bits from HC11 included CPU16 CCR, there number changes (see Figure Bits operate same both devices. bits HC11 replaced three bits: This result major change approach interrupt handling HC16. Rather than have single nonmaskable interrupt prioritized maskable interrupt, HC16 seven levels interrupt exception mask, highest level which non-maskable. section Exception Handling (Interrupts) covers this detail.
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NOTE:
After reset, interrupt mask level
CPU16 bits relate instruction covered later this section. field 4-bit extension register allow 20-bit addressing CPU16 program counter. When stacked during interrupt, there need special additional stack operation register. During branch subroutine, HC11 would normally stack just here need additional four bits register both registers also stacked branch-to-subroutine operation CPU16. instruction discards stacked content returning calling routine.
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Application Note Basic CPU16 Core Architecture Differences
Table Accumulator Instructions Compared
Instruction ARITHMETIC with carry subtract with carry subtract subtract from subtract from decrement increment decimal adjust clear LOGICAL complement negate exclusive arithmetic shift arithmetic shift logical shift rotate left rotate right COMPARATIVE compare test DATA MOVEMENT load store transfer exchange stack unstack OPERATIONS transfer transfer transfer transfer INDEX REGISTER CONTROL index index index AN461 MOTOROLA More Information This Product, www.freescale.com Accumulator 8-Bit ADCA ADDA SBCA SUBA DECA INCA CLRA COMA ANDA NEGA ORAA EORA ASLA ASRA LSRA ROLA RORA CMPA TSTA LDAA STAA XGAB PSHA PULA Accumulator 8-Bit ADCB ADDB Accumulator 16-Bit ADCD ADDD Accumulator 16-Bit ADCE ADDE Accumulator Accumulator 32-Bit
SBCB SUBB
SBCD SUBD
SBCE SUBE
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DECB INCB CLRB COMB ANDB NEGB ORAB EORB ASLB ASRB LSRB ROLB RORB CMPB TSTB LDAB STAB XGAB PSHB PULB CLRD COMD ANDD NEGD EORD ASLD ASRD LSRD ROLD RORD TSTD XGDE PSHM PULM CLRE COME ANDE NEGE EORE ASLE ASRE LSRE ROLE RORE TSTE XGDE PSHM PULM LDED STED
PSHM PULM
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HC11
EQUATES I2:I0 EQUATES I2:I0 1,2,3,4,5,6
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SUPPORT
CPU16
Figure HC11 CPU16 Condition Code Registers
Registers
HC11 limit Kbytes unsegmented addressable memory which clearly limitation 16-bit wide program counter other registers. CPU16 core been designed provide linear, unsegmented memory Mbyte user program. 1-Mbyte address space requires bits address and, therefore, program counter, index registers, stack pointer, accumulators must able address bits address bus. This done adding 4-bit registers normally 16-bit wide registers CPU. These additional 4-bit registers collectively known registers. There total: Three index registers called and, course, program counter 4-bit extension stack pointer 4-bit extension obviously, called sixth 4-bit extension little different, just associated with accumulator register 4-bit extension direct read write from/to memory from accumulators
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Application Note Basic CPU16 Core Architecture Differences
Figure shows registers both their symbolic location their apparent physical location. seen, index registers register grouped together single 16-bit wide register called, unsurprisingly enough, added lowest nibble CCR. This makes great deal sense when comes stacking registers interrupt subroutines. Clearly, should altered after stacking operation need accessible 16-bit wide register stacking purposes.
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registers most obvious core differences HC11 user, they normally start program after that, rarely altered. This good idea, least because value 4-bit registers must first loaded accumulator then transferred command TBnK read from command TnKB. primary reason changing registers that they normally point data either within program generated program HC16 peripheral modules. Often, registers take advantage distinguishing between data program space.
Program Data Space
NOTE:
There difference between data program address space CPU16. determines that access data that requires program counter (and, course, register) must address space known program space. Data space memory access accumulators (such read write operation with accumulator third type space space this will explained later section concerning hardware interfacing external interrupts.
Program space linear 1-Mbyte addressable space CPU16 automatically handles manipulation additional 4-bit register. Thus, there manipulate registers other than with stack operations.
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Freescale Semiconductor, Inc. Application Note
Data space segments Kbytes address space. extension registers point data space. will automatically change register contents when series data instructions crosses 64-Kbyte boundary (unlike register program space). user must, therefore, ensure that tables data within 64-Kbyte segment take care boundary conditions access data fields cross 64-Kbyte boundary. following examples illustrate small modifications required ensure data accesses will operate between adjacent segments. only takes five additional lines code bytes make Example work over bank boundary. resultant code found Example Both examples perform same task, Example restrictions where input table lies. Another interesting point std, instruction. output table gone across bank boundary, this code would still work because accumulator added YK:IY value will temporarily incremented accE exceeds $FFFF. itself never changed such instance.
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Example HC16 Code with Data Accesses Same 64-Kbyte Segment
*************** MOVE data within bank boundary ************* 64-Kbyte extends from $0000 $0FFFF Move words table from internal bank RAM_TABLE $0040 output table $F0040 (RAM bank TABLE $F000 input table starts $0F000 (bank TABLE_END $F200 input table ends $0F200 (bank TABLE_LENGTH $200 table bytes length ldab tbxk ldab tbyk moveloop adde #TABLE_LENGTH moveloop data from write increment source pointer word increment destination pointer word check past table then continue move data #$0000 #RAM_TABLE #TABLE point bank table point bank destination SRAM source
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Application Note Basic CPU16 Core Architecture Differences
Example HC16 Code Data Accesses Across Adjacent 64-Kbyte Segments
*************** MOVE data within bank boundary ************* 128-Kbyte extends from $0000 $1FFFF Move words table from internal bank RAM_TABLE $0040 output table $F0040 (RAM bank TABLE $FF80 input table starts $0FF80 (bank TABLE_END $0180 input table ends $10180 (bank TABLE_LENGTH $200 table bytes length ldab tbxk ldab tbyk moveloop check_bank new_bank txkb addb tbsk same_bank adde #TABLE_LENGTH moveloop increment destination pointer word check past table then continue move data IX=$0000 then current bank increment update bank pointer #$0000 same_bank check data runs over bank boundary $0000 then still same bank data from write increment source pointer word point bank (ROM) input table point bank (RAM) output table #$0000 #RAM_TABLE #TABLE destination SRAM source
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Freescale Semiconductor, Inc. Application Note
Examination Part CPU16 Core totally function core multiply-accumulate capability. seen from Figure there number registers that intended used multiply 16-bit numbers pointed index registers result added contents 36-bit register called single instruction (multiply-accumulate). This instruction post increment/decrement both index registers allow series commands multiply accumulate results series values very quickly. This function digital filtering complete clock cycles). registers used pointers indexed data XMASK YMASK bytes control actual addressing data. These masks, when will effectively give upper limit address range registers. This gives wrap around effect data, remember start table input data coefficient data multiple mask value. table size power XMASK maximum plus value XMASK equal will allow table values, while XMASK equal will allow four values XMASK equal will allow table eight values. algorithms found many HC11 applications CPU16 core will perform same function very much faster.
MULTIPLIER INPUT REGISTER MULTIPLIER INPUT REGISTER ACCUMULATOR ACCUMULATOR BITS 15-0 SIGN LATCH XMASK YMASK BITS 35-16
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Figure Registers
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Application Note Basic CPU16 Core Architecture Differences
READINGS
COEFFICIENTS
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ACCUMULATOR
Figure Instruction Flow
HC16 n-Tap Filter
often found that HC11 device required perform some averaging data reduce noise reading, example. Normally, this would simply buffer with last readings from channel this would updated regularly, while separate routine would results divide answer number readings averaged. effect, this making HC11 perform lowpass digital filter function. HC16 device RMAC instructions allow perform more than just averaging function incoming data. show actual operation part core, following shows simple filter performing averaging routine through what called finite response filter (FIR). results averaged, would necessary HC11 divide values average more than 10-bit result, then HC11 would have problems storing results because this would exceed bits. solution this divide each result multiple least prevent overflow, this would reduce accuracy result. only alternative perform arithmetic greater than bits which time consuming HC11.
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Freescale Semiconductor, Inc. Application Note
Example HC11 Code Average 10-Bit Values
loop addd lsrd lsrd lsrd lsrd lsrd lsrd cycles clear accumulator values averaged next value move pointer next result decrement result counter check values added loop 1216
result,x
loop
divide total left shifts) save average
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average
routine Example more general allows fairly complex filtering functions where coefficients constant averaging routine described earlier. This routine also shows initialization registers masks modulus addressing coefficients input data. There number commands especially this function. Example N-Tap Filter HC16
NTAP ENTRY: INPUT DATA (Q15 fraction) NUMBER TAPS DATA STATE NTAP STATES WORDS) COEFF_TABLE COEFF NTAP COEFFICIENTS WORDS) USER_ROM INITIALIZE START1LDX #STATE #COEFF #$3F3F TDMSK LDHI CLRM #NTAP-1 calculation LOOP RMAC
initialize input data pointer initialize coefficient pointer masks 2**6 (64) Load masks (IX) HR(m); (IY) IR(m)
loop count
accM [HR(m-1) IR(m-1)] accM IX+2 IY+2 (IX) HR(m); (IY) IR(m) accE-1 accE perform 65th slip input data pointer transfer rounded result accE from accM
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Application Note Source Code Compatibility
Bits
saturation accumulator shows that there been overflow into value greater than 0.99997 less than -0.99997. extension accumulator shows that there been overflow into that result accumulator incorrect changed from positive number negative number. This written invisible register called signlatch which will retain sign overflow.
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(saturation mode) that written CCR. When set, result accM (31:16) will either most positive ($7FFF) most negative ($8000) number, depending upon sign overflow. This simulates analogue saturation.
Source Code Compatibility
Basic Approach Source Code Compatibility
HC16 considered source code compatible with HC11. This means that user take HC11 code pass through HC16 assembler will function just before (ignoring obvious hardware differences). With exceptions, which will explained this section, this indeed case. CPU16 core fully 16-bit additional feature 20-bit addressing built into core design. This accounts many changes, these features normally affect that HC11 source code would operate. Interrupts, stack operations, communication with on-chip peripherals main areas change, these very simple make.
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Freescale Semiconductor, Inc. Application Note
Changes Detail fact, great deal effort gone into maintaining HC11 source code compatibility. example, there exception vector divide however, this does function with HC11 command IDIV FDIV. will function only with CPU16 divide instruction, EDIV EDIVS. Similarly, there direct page (page zero) addressing mode enable user code efficient 8-bit offset operations anywhere memory. quick glance, HC16 assembly code looks very much like HC11 code. most obvious difference initialization sequence start user program. Here, registers peripheral modules configured specific requirements application. Since HC11 only address Kbytes (except, course, HC11K4), registers most likely will will point lowest 64-Kbyte address space where reset vectors situated where user program most likely will start. registers peripherals, however, located very 1-Mbyte memory address. Therefore, they accessed either forcing read/write 64-Kbyte segment negative offset address.
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Addressing Modes
CPU16 core makes full signed arithmetic important remember that unsigned operation HC11 could become signed operation with HC16. 16-bit indirect offset unsigned value HC11, becomes signed 16-bit value HC16. following example should help illustrate this. Taking register TOC2 (timer output compare module) with address $FF916 example, read this with following instructions: $F916,X where $0000 signed offset signed offset
$06EA,X where $0000 $F916 $16,X where
unsigned direct address unsigned offset
where $F900
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Application Note Source Code Compatibility
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number $F916 negative number since 16-bit offset always signed, register must Indeed, Number exactly same instruction, this time negative number shown more clearly negative sign. number address mode changed from indirect 16-bit signed offset index register direct address mode. this case, address considered positive, unsigned number, register must force read from segment ($F). completeness, number shows HC11 approach this using unsigned 8-bit offset index register address. this last example, register form 20-bit address register must point segment ($F) address space. simplicity, programmer would normally utilize number access HC16 registers since this leaves index register other activities within program. Making full 16-bit offset addressing mode HC16 leads other small changes user's software. Taking previous example, look from point view HC11 user. Normally, HC11 TOC2 register would reside address $1018, HC11 program would have: $18,X $1018 Experienced users HC11 usually would example equivalent using register) because when using equates peripheral register address (for example TOC2, where TOC2 $1018), important remember that manipulation (BRSET, BRCLR) instructions only 8-bit offsets. avoid multiple definitions same register, most HC11 programmers keep register address byte value equally have TOC2,X BRSET TOC2,X,LABEL (with TOC2 $18) read register. With HC16, register allows 16-bit (2-byte) address used equate frees index register. where $1000
NOTE:
manipulation operates both 16-bit addresses. Hence, HC16, with TOC2 $F916, following would work perfectly.
BRSET TOC2 #1,TOC2,LABEL
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Timing Changes
Program delay timing loops obviously affected change cycle times instructions. There relation between HC11 instruction timing CPU16 timing. Remember also that HC16 clock speeds 16.78 (bus speed 8.39 MHz). HC11, there advantages using index register rather than index register. This because instructions using index require additional opcode take byte more memory more cycle execute. CPU16 does have such difference between index registers which have same number opcodes timing.
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Assembly Code Differences Between HC11 HC16
number HC11 instructions changed slightly allow them function with core design. list Table long one, often user create macro routine instruct assembler change HC11 code into CPU16 code. instructions ANDP, AIX, AIY, AIS, PSHM, PULM, each replace several HC11 instructions. particular, will often replace either sequential instructions (similarly, replaces sequential instructions) will make CPU16 code smaller look better. remaining changes accommodate different stack operation CPU16 (discussed later Exception Handling (Interrupts)) 20-bit addressing capability core.
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Application Note Source Code Compatibility
Table HC11 Instructions Modified CPU16 Implementation
HC11 Instruction CLC, CLI, DES,DEX,DEY INS, INX, Change CPU16 Generates different stack frame Replaced ANDP instruction Replaced AIS, AIX, instructions Replaced AIS, AIX, instructions Indirect 8-bit offset replaced 20-bit offset extended addressing (20-bit address) modes instruction generates different stack frame Replaced PSHM Replaced PULM Only unstacks registers Only unstacks registers Replaced instruction bits interrupt masking differ from HC11 Adds SK:SP before transfer XK:IX YK:IY Subtracts from XK:IX YK:IY before transfer SK:SP Transfers full bits, including registers Generates different stack frame
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PSHX, PSHY PULX, PULY SEC, SEI, TAP, TSX, TXS, TXY,
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Enhancements CPU16 Source Code
20-Bit Addressing
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16-bit signed branch long branch) limits programmer moving plus $7FFF minus $8000 bytes from current position. HC11 instructions have operand bits allow jump anywhere within 68-Kbyte address range 16-bit operand. instructions have been changed CPU16 take 20-bit address. These instructions also allow jump indexed address with 20-bit signed offset. Thus, possible calculate destination address jump with HC16 where would have required building executing instruction HC11. This instruction affected register which remains unchanged. instructions have been added CPU16 move data from specific memory location another memory range memory locations. These MOVB MOVW instructions which rather unsurprisingly move byte move word, respectively. instructions form shown Table with, course, same instructions word moves.
Moving Data without Affecting Accumulators
Table Move Instruction
MOVB offset,X(n) MOVB offset,X(n) MOVB Move byte from indexed address with post increment signed 8-bit offset extended 16-bit address. Move byte from extended 16-bit address indexed address with post increment signed 8-bit offset. Move byte from extended 16-bit address extended 16-bit address.
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Application Note Source Code Compatibility
This instruction completely orthogonal does include move from indexed address indexed address. These instructions particularly useful when capturing data from peripheral module such placing results buffer future use. interrupt routine could move data with minimum disturbance registers hence reduce interrupt execution time. Such example shown here, where interrupt routine triggered periodic interrupt timer (PIT) copies value circular buffer filter.
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Note also 32-bit load store instructions LDED STED.
Example HC16 Moving Data from Result Register Table
************************MOVEW data into **************************** Interrupt routine running from word table filter addreslt1 $F732 start_tableequ $0100 end_table $0200 RAMpoint moveAD1 pshm ldab tbek lded tbxk xgex movw xgex sted pulm 32-bit result save altered registers point 32bit value containing 20bit pointer bits 19:16 into move bits 15:0 into data from result register check pointing past table then continue yes, rest pointer start table value into accE store value again restore altered registers
PIT_exception D,E,X,K RAMpoint adres1tl, x(2); #end_table #start_table RAMpoint D,E,X,K
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Freescale Semiconductor, Inc. Application Note
RMAC
multiply-accumulate (MAC) instruction repeat (RMAC) offer substantial improvement performance over HC11. been explained previous section about core design, function number dedicated registers CPU. These registers require support number instructions, some which seen example code describing filter algorithm. instructions described here provide programmer with necessary tools perform algorithms.
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First, section must initialized.
Table Register Initialization
LDHI TDMSK CLRM TEDM Loads contents addresses pointed into registers respectively Loads modulo addressing mask registers. Zeros register clears appropriate flags Transfers contents into bits 31:16 register clears other bits register Loads register with 32-bit value accE:accD
RMAC instruction multiples registers together then adds 32-bit result lower bits register. RMAC instructions form:
offsetX offsetY RMAC offsetX offsetY post incremented offsets post incremented offsets Accumulator decremented then calculation repeated until
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Application Note Source Code Compatibility
flow instruction shown Figure
NOTE:
registers modified MAC, with exception accumulator which used RMAC instruction count number instructions performed.
MAC: AccE:AccD<-(H-Reg)x(I-Reg) AccM <-(AccM)+(AccE:AccD) <-(IX)+X-offset, qualified mask <-(IY)+Y-offset, qualified mask <-(H-Reg) H-Reg <-(IX) I-Reg <-(IY) FLOWCHART OFFSET OFFSET RMAC: AccM <-(H-Reg)x(I-Reg)+AccM <-(IX)+X-offset, qualified mask <-(IY)+Y-offset, qualified mask H-Reg (IX) I-Reg (IY) Until
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REGISTER
REGISTER
AccD
AccE
AccM
Figure Instruction Operation RMAC instruction interruptable takes cycles first calculation followed cycles iteration thereafter.
NOTE:
modulo masks must cleared allow more than indexed values multiplied RMAC instruction.
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Freescale Semiconductor, Inc. Application Note
four additional bits accumulator allow certain amount overflow without loss data. data accumulator accessed commands listed Table Table Support Instructions
TMER TEMT TMXED Transfer convergent-rounded 16-bit value M(31:0) into accE Transfer truncated 16-bit value accumulator M(31:16) into accE Transfer bits accumulator into IX(3:0):accE:accD with IX(15:4) sign extended with value Perform signed fractional multiply accE accD then shifts result left place clear accD(0) Adds accE:accD accumulator M(31:0) Adds accE accumulator M(31:16) Shifts entire bits accumulator left place (multiply Shifts entire bits accumulator right place (divide Save contents modulo masks stack Restore contents modulo masks from stack Long branch (M(31) set) Long branch (M(35) set)
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Support instructions also available: FMULS ACED ASLM ASRM PSHMAC PULMAC LBEV LBMV
Stack Operations
differences between cores mean that stack operations will quite different. HC11 number instructions stack manipulation, stack always made 8-bit values. CPU16 stack consists 16-bit values many more registers save stack. fundamental difference that only saved during exception process. left programmer decide which remaining registers must saved stack. make life simpler, there instructions perform this task:
Saves combination listed registers stack fixed order Stacks registers masks)
PSHM D,E,X,Y,Z,K PSHMAC
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Application Note Source Code Compatibility
PSHA PSHB retained from HC11 source code maintain compatibility, PSHX PSHY become PSHM PSHM respectively, performed with line code, PSHM X,Y, save time. push multiple (PSHM) instruction adds appropriate number words stack decrements stack pointer appropriately. always makes sense registers possible when writing exception (interrupt) handlers HC16 each additional stacked register takes clock cycles save onto stack using registers (any them requires clock cycles stack operation). Remember also that they must pulled from stack afterward, when routine complete ready return from interrupt. stack pointer bits CPU16 placed anywhere memory using register. registers either including their address reset vector table (see Initialization HC16 Device) TBSK instructions same HC11.
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NOTE:
Initialize stack pointer even address (see Example 10).
Table HC11 Stack Control Instructions
PSHA, PSHB PSHX, PSHY PULA, PULB PULX, PULY TSX, TXS, Interrupt event Relative branch subroutine (stack bytes reg) Decrement stack pointer byte Increment stack pointer byte Direct jump subroutine (stack bytes reg) Load stack pointer with memory immediate value Push 8-bit accumulators Push 16-bit registers Pull 8-bit accumulators Pull 16-bit registers Return from interrupt (unstack bytes) Return from subroutine (unstack bytes register) Store stack pointer value memory Software interrupt (stack registers) Transfer stack pointer register Transfer register stack pointer Stack bytes (all registers)
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Difference between
first sight, instructions look very similar, there subtle difference between them. They both pull registers stack both take clock cycles execute, stores entire register contents while only restores field register. Another small change fact that must return instruction following just completed prior taking exception. Since pipeline fetches code cycles ahead, decrements program counter thus points correct place memory after exception. Table CPU16 Stack Control Instructions
PSHA, PSHB PSHM PULA, PULB PULM TBSK TSKB TSX, TSY, TXS, TYS, Interrupt event Branch subroutine (stack bytes CCR) Compare stack pointer with memory immediate value signed 16-bit value stack pointer Jump subroutine (stack bytes CCR) Load stack pointer with memory immediate value Push 8-bit accumulators Push combination 16-bit registers list Pull 8-bit accumulators Pull combination 16-bit registers list Return from interrupt (unstack bytes CCR) Return from subroutine (unstack bytes CCR) Store stack pointer value memory Software interrupt (stack bytes CCR) Transfer accB(3:0) register Transfer register accB sign extend accB(7:4) Transfer stack pointer register Transfer register stack pointer Stack bytes registers)
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Application Note Source Code Compatibility
assumes that jump branch instruction 2-word instruction (except label) just subtracts from after restoring stacked CCR. instruction adds since single word opcode, simulates LBSR opcode instructions 2-word length. comparison, HC11 takes cycles five cycles instruction, pulls registers stack.
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16-Bit Signed Branch
overcome limitations HC11 branch instruction being limited signed 8-bit value, CPU16 instructions called long branches. These have 16-bit signed offset allow 32-Kbyte jump anywhere program space, even across 64-Kbyte boundaries. instructions simply same 8-bit signed offset with addition letter before instruction (for example, REL8 becomes LBRA REL16). Since 16-bit offset requires more data operand, opcode becomes bytes operand bytes with typical execution time four cycles compared with 8-bit relative branch which takes cycles single-byte opcode operand.
Pipelining
will notice that there were possible execution times conditional branch instructions. This function CPU16 architecture which involves pipelining data read from memory preprocessing information before actually executed. pipeline 3-stage operation which first reads 2-byte (word) value then evaluates opcodes. this stage, operands evaluated instruction executed. Finally, opcodes moved through third stage after execution complete. improvements performance approximately two-fold over more conventional approach HC11 hence HC16 roughly twice fast HC11 given speed. pipeline especially noticeable with types instructions.
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Freescale Semiconductor, Inc. Application Note
inherent instructions take clock cycles cycle HC11 terms) execute. Even instruction HC11 takes cycles execute. more important change, especially HC11 user, that conditional branch take differing execution times depending upon whether pipeline needs purging after instruction completed. take instruction. This takes three cycles HC11, irrespective whether condition true false. CPU16 pipeline read next instruction result false will read next address after instruction while instruction being evaluated executed. result false, then already fetched evaluated next instruction immediately execute thus saving possibly four clock cycles. however, instruction result true branch taken, then CPU16 must look address indicated relative offset operand fetch this instruction instead. will, therefore, need disregard first stages pipeline start again. Hence, takes cycles this time complete instruction. long branch similar, here opcode plus operand fill three stages, only stage pipeline must disregarded branch taken. Thus, LBNE takes four cycles taken cycles taken.
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NOTE:
When converting code from HC11, take special note critical timing loops faster invert logic test take advantage pipeline speed execution.
following four examples show pieces code HC11 then HC16 device. First, will striking much shorter HC16 code compared HC11 code. Clearly, speed execution another important difference. first example comes from linear interpolation table routine where limited number data points were used form complex table.
32-Bit Arithmetic
NOTE:
HC16 code uses signed multiply divide allow table have positive negative slopes.
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Application Note Source Code Compatibility
Example Example cubing 8-bit result give nonlinear function input. Since result calculated each time always positive, unsigned arithmetic been used HC16 example. Example HC11 Code Calculate 16-Bit Times Bits Divided Bits
CALC_TBL_ENTRY LDAB LDAA LDAB ADDA LDAB LDAA INCB C_SKIP TSTA FDIV XGDX CLRA C-SMALL IDIV XGDX NOMINATOR DENOMINATOR MULTIPLIER mult AMUL NOMINATOR+1 MULTIPLIER mult BMUL AMUL+1 BMUL AMUL C_SKIP AMUL DENOMINATOR AMUL+1 C_SMALL bits 24-bit result check multiply result only bits then different divide calculation 8-bit result added first multiply gives bits
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carry affected ldaa ldab
result BMUL calculation high bits (8-bit result) result
Example HC16 Code Perform 16-Bit Times 8-Bit Divided Bits
calc_tbl_entry emuls edivs xgdx multiplier nominator denominator place result accumulator
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Example HC11 (8-Bit 8-Bit 8-Bit) 9-Bit
CALCULATE NUMBER PULSES contains value calculation contains result f(x) (ad_measured cubed f(x) (AD_RESULT) (AD_RESULT) (AD_RESULT) CALC_PULSES save value temporarily STAA TEMP_AD squared CALC_SHIFT READ_5 CMPA READ_6 check greater than 8-bit value CALC_SHIFT then continue LSRD keep track divisions READ_5 divide READ_6 LDAA TEMP_AD back check 8-bit result restore original result #400 obtain cubed value IDIV offset normalized values XGDX divide offset best values READ_7 CALC_SHIFT place 16-bit result READ_8 check previously CALC_SHIFT then finish LSLD keep track multiplies READ_7 back check mults done READ_8 result
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Example HC16 (8-Bit 8-Bit 8-Bit) 9-Bit
calculate number pulses contains value calculation contains result f(x) (ad_measured cubed f(x) (ad_result) (ad_result) (ad_result) calc_pulses clra ad_result placed accE (making sure upper byte=0) multiply accA accB emul Multiply accD accE (=24 bits E:D) #400 ediv divide scale factor xgdx place result accD
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Application Note Source Code Compatibility
Comparison HC11 HC16 Code Benchmarks
rough estimate increased performance HC16 over HC11 that 16.78-MHz clock HC16 nine times faster 8-bit operations than 2-MHz HC11. Taking theoretical 8-MHz speed HC11 comparing with 16-MHz clock speed HC16 (8-MHz fast termination speed), performance differential still approximately factor This largely improved opcode efficiency pipeline CPU16 architecture. 16-bit 32-bit calculations, HC16 even faster than HC11.
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Check List Changes HC11 Code
registers correctly. Ensure registers stack interrupt routines. Remember exception routines additional vectors. Initialize peripherals register start program. Change register equate addresses using similar peripheral functions. Check actual timing software delay loops. Make interrupt arbitration priorities correctly. Remember that HC16 averages nine times speed 2-MHz HC11. Alter code that manipulates CCR. (The bits moved about.) Check misaligned stack addressing using PSHA, PSHB, etc. Indirect 16-bit offset address operations signed values.
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Freescale Semiconductor, Inc. Application Note Initialization HC16 Device
Control
significant change from HC11 control clock frequency. HC16 module phase-locked loop (PLL) "limp mode" 8-bit oscillator built into clock circuitry. normal operation, would have 32-kHz crystal connected EXTAL XTAL pins. This frequency then multiplied phase locked provide internal clock frequency theory. practice, maximum speed currently restricted 16.78 MHz.
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(NOTE
VDDSYN
0.01
EXTAL
XTAL
VDDSYN
CRYSTAL OSCILLATOR
PHASE COMPARATOR
LOW-PASS FILTER
FEEDBACK DIVIDER CLKOUT SYSTEM CLOCK CONTROL SYSTEM CLOCK
Notes: Must low-leakage capacitor. EXTAL driven with external oscillator.
Figure Schematic Diagram
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Application Note Initialization HC16 Device
After reset, preset 8-MHz clock frequency from 32-kHz crystal normally will changed initialization section HC16 code.
NOTE:
There 20-ms lock time altering W-bit will, therefore, take this amount time before frequency stabilized. Changing instantaneous effect since outside feedback loop. consequence, necessary check change will take oscillator over 16.78 before effect change takes effect. example changing oscillator from 16.78 where (SYNCR(15:8) $8F). Writing upper byte SYNCR looks same writing SYNCR(15:8), latter would cause oscillator attempt short time changes frequency would certainly cause system fatal error. correct procedure write SYNCR(15:8) then after SLOCK state later) write SYNCR(15:8).
called MODCLK controls whether enabled. Holding MODCLK logic during reset will disable system designer then external high-frequency clock driver connected EXTAL pin.
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NOTE:
possible connect 16-MHz crystal EXTAL XTAL pins directly.
SRAM Initialization Procedure
internal SRAM disabled reset. This because fully relocatable default start address same location reset vectors. SRAM base address registers should, therefore, written then module configuration register written enable SRAM.
NOTE:
SRAM base address registers cannot modified unless (STOP control) (SRAM disabled) (RLCK: base address lock) cleared. RLCK 1-time writable register after reset.
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Freescale Semiconductor, Inc. Application Note
When using HC16Z1 evaluation board, often case that memory display window will pointing after been initialized. Typing reset command will cause HC16 device reset SRAM disabled again. window will show garbage data unless pointing chip-selected address. addition, further EVB16 commands will update memory display window could cause string DSACK errors EVB16 software reads non-existent memory.
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Stack Initialization
Since SRAM placed anywhere 1-Mbyte address space, obvious that stack pointers will very likely required have same flexibility. 20-bit stack pointer reset vectors, seems good idea move SRAM this location soon possible after reset. Remember that stack will decrement bytes stack pointer always even address. example, assume that SRAM positioned $14000 since MC68HC16Z1 Kbytes SRAM, address byte addressable $143FF. stack would initialized with value $43FE. When debugging code with HC16Z1 evaluation board, user find debug code simpler adding initialization stack pointer initialization code, even though loaded after issuing RESET command EVB. Such example shown Example
Register Initialization
4-bit registers normally initialization routine HC16 along with index register initialization just would HC11 code. Since only access registers accumulator simple matter accB copy value into appropriate register. following code illustrates MC68HC16Z1 initialization SRAM, stack pointer, CSBOOT, module registers. comparison, HC11 routine quite tiny.
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Application Note Initialization HC16 Device
Example MC68HC16Z1 Initialization Routine
reset ldab tbzk tbsk ldab tbek ldab stab ldab stab ldab tbxk ldab tbyk andp $ramstart+$03fe #$0f #rambase $fb05 #ramstart $fb06 $fb00 #$78b0 csorbt #$7f $fa04 $fa21 #0000 #$000f gptmcr #$9650 gpticr #$ff1f iarb=$f overflow=highest priority, level vect=5x interrupt priority (lowest) init rambase (=1) rambah(low) (=4000) lower bits $4000 rammcr $8000 csboot with wait state 16.777 syncr sypcr movedata subroutine
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Example HC11 Initialization Code
RESET #$FF CLEAR INTERRUPT INHIBIT
Table Registers that Must/Should Written after Reset
SIMMCR QSMMCR ADCMCR GPTMCR SRAMMCR SYNCR CSPAR0 CSPAR1 CSPDR PORTF DDRF PFPAR module configuration register module configuration register module configuration register module configuration register SRAM module configuration register control register Action chip select pins Action chip select pins Chip-select port pins status port Port output status Mode operation port control status port
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Freescale Semiconductor, Inc. Application Note
Table List 1-Time Write Bits/Registers
SIMMCR bit) SRAMMCR (RAMBAR bit) SYPCR (entire register) module address SRAM base address System protection control register
Mode Selection During Reset
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configured several different ways reset. This allows basic functions asynchronous data/address bus, data/program space selection chip selects. bring HC16 reset particular mode operation, simply pull appropriate data logic during reset. best force data connect data outputs 74HC244 device enable outputs with reset signal. Alternatively, resister used condition data pins with small effect switching characteristics data bus. table possible mode options shown Table
Reset Operation
Reset HC16 much like HC11. address fetched from known area memory used determine start user's program. HC11 vector table contains reset vector interrupt vectors starting $FFFE,$FFFF (16-bit address) moving down memory bytes time with increasing priority. Example example HC11 vector table.
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Application Note Initialization HC16 Device
Table Configuration Reset
Mode Select Default Function Left High CSBOOT 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit CS7-CS6 16-bit CS8-CS6 16-bit CS9-CS6 16-bit CS10-CS6 16-bit control DSACK0, DSACK1, AVEC, SIZE IRQ7-IRQ1 MODCK Slave mode disabled system clock Background mode disabled Alternate Function Pulled CSBOOT 8-bit BGACK A20-A19 A21-A19 A22-A19 A23-A19 PORTE PORTF Slave mode enabled EXTAL system clock Background mode enabled
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DB11 MODCK BKPT
HC16 similar approach with exception that table starts $00000 moves memory bytes time. Prioritization interrupts described Exception Handling (Interrupts) differs significantly from HC11. HC16 reset vector actually consists four 16-bit values. These register values registers, 16-bit reset vector, 16-bit stack pointer address, lastly 16-bit register value. effect, this 20-bit address reset vector stack pointer plus direct page address bits. reset vector can, therefore, jump anywhere 1-Mbyte address range program space, other vectors just bits only jump directly first 64-Kbyte address segment program space. From there, 20-bit address instruction will anywhere program space memory.
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Freescale Semiconductor, Inc. Application Note
reason including register compatibility with HC11 direct page instructions. These offer code efficient 8-bit operations have added feature being anywhere memory, rather than just between addresses $0000 $00FF HC11.
Vectors, Stack Operations
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first bytes address bank (from $00000 $001FF) reserved vector exception table. first eight bytes special, since these contain reset vector data. This followed number special vectors required maintain system operation. These directly related operation. After this space user-defined vectors stored, each 2-byte (16-bit) address pointing address bank ($00200 $0FFFF). There many differences from HC11 vector table. most obvious that vector table starts beginning memory increments through compared with HC11 vector table starting $FFFE,F decrementing address bytes time each vector. HC11 fixed vectors always bits length, HC16 vectors most peripheral modules user reset vector substantially more information eight bytes. There also number vectors familiar HC11 user. These explained later.
Exception Routine Address
There many more interrupt sources possible HC16 system. allow maximum flexibility maintain compatibility with 68000 exception handling external protocol, internal peripherals have fixed predetermined exception vectors like HC11. Each peripheral have exception vector number initialized after reset, user maintain these correctly. addition, scheme allows external device initialized with vector number there restrictions peripheral devices.
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Application Note Initialization HC16 Device
User-Defined Vectors
user vector number initialized each module interrupt source. Some modules submodules have just single vector, such PIT, while others, such GPT, have vectors associated with module. vector number 8-bit value that, when multiplied becomes vector address first exception vector that module peripheral. example HC16 vector table shown Example This shows that vector number (decimal 56).
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This compared with definition HC11 HC16 vector tables that follow. Note different start addresses direction down vector table.
Vectors HC11 Users
divide-by-zero interrupt caused failure extended divide instructions from CPU16. error exception explained External Hardware Interfacing, covering hardware design basically occurs result read non-existent memory. breakpoint vector associated with background mode. This leaves spurious interrupt where cannot determine source interrupt, uninitialized interrupt, which default value interrupt 68000 peripheral devices and, finally, autovectors. latter most likely treated XIRQ pins HC11 users. These directly linked IRQ1 IRQ7 pins provide user with general-purpose interrupt vectors non-68000 peripheral devices. Remember that order vectors linked priority interrupt example, IRQ1 vector comes before IRQ2 vector. There course, hierarchy priorities exception processing, this found reference manual.
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Freescale Semiconductor, Inc. Application Note
Reset Status Register
After reset, this register checked determine source reset HC16 device. This register $FFA06. Sources reset are: External reset Power-up reset Software watchdog reset Halt monitor reset Loss clock reset System reset; from CPU32 available from CPU16 Example Definition HC11 Vector Table
VECTORS SCI_interrupt SPI_interrupt PAC_interrupt PAC_overflow OVERFLOW IC4_INT OC4_INT OC3_INT OC2_INT OC1_INT IC3_INT IC2_INT IC1_INT XIRQ swi_interrupt illegal cop_interrupt RESET RESET PULSE INPUT PULSE OVERFLOW TIMER OVERFLOW INPUT CAPTURE OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE INPUT CAPTURE INPUT CAPTURE INPUT CAPTURE REAL TIME INTERRUPT XIRQ ILLEGAL OPCODE CLOCK MONITOR RESET $FFD6
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Application Note Initialization HC16 Device
Table Vector Table Definition HC16
Vector Number Vector Address 0000 0002 0004 0006 0008 000A 000C 000E 0010 0012-001C 001E 0020 0022 0024 0026 0028 002A 002C 002E 0030 0032-006E 0070-01FE SPACE (prog/data) Exception Reset Initialize Reset Initial (start user prog) Reset Initialize Reset Initialize (direct page) Breakpoint (BKPT) error (BERR) Software interrupt (SWI) Illegal instruction Divide zero Unassigned Uninitialized interrupt Unassigned Level interrupt vector (autovector) Level interrupt vector (autovector) Level interrupt vector (autovector) Level interrupt vector (autovector) Level interrupt vector (autovector) Level interrupt vector (autovector) Level interrupt vector (autovector) Spurious interrupt Unassigned User-defined interrupt vectors
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9-14 25-55 56-255
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Freescale Semiconductor, Inc. Application Note
Example Actual HC16 Vector Table
$0110 {ramstart+$03fe} $0000 vectors reset bkpt_int bus_err swi_int illegal div_by_0 un-initialised reset int_1 int_2 int_3 int_4 int_5 int_6 int_7 spurious itic1 highest priority within module below selected used, zk=$1, sk=$1, pk=$0 stack pointer starts address $43fe index pointer registers initial initial program counter value initial stack pointer value initial direct page select (iz) breakpoint address error address interrupt address illegal instruction address divide zero uninitialised interrupt reserved level interrupt autovector level interrupt autovector level interrupt autovector level interrupt autovector level interrupt autovector level interrupt autovector level interrupt autovector spurious interrupt
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dumy1 dumy2
end_main_vect
itic1 itic2 itic3 itoc1 oc2_int itoc3 itoc4 iti4o5 ioverflow ipulse_ovr ipactl
lowest priority within module
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Application Note Exception Handling (Interrupts)
Exception Handling (Interrupts)
Interrupt Request Handling
Interrupts called exceptions HC16 world. This conforms nomenclature 68000 processor more accurately explains nature sudden change activities CPU. Interrupts will, therefore, referred exceptions from
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Module Design Influence Conversion from HC11 HC16 Code
Many HC16 modules clearly based functionality HC11 module. prime example this general-purpose timer (GPT) timer module. main difference lies interface this required some specific initialization interrupt vectors, arbitration, etc. After this, there often modulus prescaler where HC11 choice just divide-by-two options before this necessary accommodate variable system clock frequency possible with PLL. addition this, module also operate higher maximum speeds, greater functionality, generally more flexible operation. peripheral modules have 16-bit wide registers general much greater flexibility operation than equivalent HC11 module. example, will look HC16 module interrupt handled events. This module based upon timer used HC11E9 HC11F1, number important differences.
Setting Internal Exception
Both internal external exceptions basically handled same way. exception starts when interrupt source pulls external line (active state). responds with interrupt cycle (CPU space) waits acknowledgment from interrupt source. interrupt must generate interrupt acknowledge (IACK) cycle. This lets know that interrupt source still available will then take control bus.
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Freescale Semiconductor, Inc. Application Note
able determine that internal module interrupt source existence special line called IIACK. This lets know that interrupt source still available will then take control address/data bus. exception internal module, interrupt level arbitration priority must set, along with desired reset vector. Each module must uniquely programmed with this data. Remember that exception vector must doubled provide vector address since this device 16-bit vector address.
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HC11 Timer Initialization
task initializing HC11 timer relatively simple. action event such input capture output compare, output function state occurrence next event input trigger input capture, clear event flag enable interrupt. Example shows code setting cause pulse generated from pin. Example HC11 Code Timer Initialization
TIMER_SET TIMER_INITIALIZATION cylinder pulse Interrupt (falling edge pulse) timer microsecond resolution LDAA STAA LDAA STAA LDAA STAA #%01000000 OC1M+REGS #%01000000 OC1D+REGS #%01000000 TCTL1+REGS
(OC2) also controlled when compares toggles compare
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Application Note Exception Handling (Interrupts)
HC16 Code Interrupt Initialization
HC16 several different timers, design basically taken from MC68HC11E9 timer. consequence, there very little difference main part setup procedure. There some additional lines code module exception vector base address, interrupt level, arbitration, timer prescaler. code Example being initialized interrupts from output compare
NOTE:
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vector number part GPTICR register sets vector number from onward. This means vector table starts $A0. GPTICR also contains interrupt level (level used this example) highest priority vector adjustment just possible with HC11. arbitration priority maximum This required, timer usually highest priority event. remember that level much more important than arbitration level prioritization interrupts. Some registers only have half bits written this example. This because reset condition vectors used. output must specifically made output function. default would input general-purpose port line. Just with HC11, function drive pin. interrupt capability enabled finally timer fully initialized. Remember prescaler selection timer.
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Freescale Semiconductor, Inc. Application Note
Example HC16 Initialization Interrupts
*GPT registers gptmcr gptmtr gpticr gptport toc1 toc2 tct1 tmsk
$f900 $f902 $f904 $f906 $f908 $f914 $f916 $f91e $f920 ioverflow itic1 itic2 itic3 itoc1 oc2_int itoc3 itoc4 iti4o5 ioverflow ipulse_ovr ipact1
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Timer_initialization cylinder pulse oc2data interrupt (falling edge pulse) timer microsecond resolution timer_set ldab tbek ldaa ldab ldaa staa ldaa ldab staa #$000f gptmcr #$000f gptmcr #%00010000 #%00010000 #%00000001 tct1 #$1010 gptport #%00010000 #$00000001 tmsk iarb=$f overflow=highest priority level 6,vect=5x oc2data (oc2) also controlled oc2data when compares toggles oc2data compare enable output output compare interrupt enable timer prescaler divide AN461 More Information This Product, www.freescale.com MOTOROLA
Application Note Exception Handling (Interrupts)
Initializing QSPI
QSPI briefly described previously. reference manual very good explanation good examples initialization code. code Example initializes QSPI. four configuration registers start user program then normally only require changes bits during rest user software. steps relatively simple: Assign functions QPAR register.
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Configure clock, master/slave, data size. beginning queue, enable/disable wrap mode (continuous transmit) enable interrupts. command transmit data appropriate queues. Select delay options required enable QSPI. QSPI model seen Figure Example Initialization QSPI
QSPI_INIT #$1B7E QPAR #$8008 SPCR0 #$2069 SPCR1 #$8F00 SPCR2 #$0200 SPCR3 PCS1 active, enable pins, make MISO input master, inactive=0, leading edge, 1.05MHz delay=1.9µs, transfer delay=200µs finished interrupt enable, queue=$F HALTA MODE FAULT interrupt enabled
Setting External Exception
HC11 user most likely IRQx pins emulate functions XIRQ pins HC11. HC16 requires that autovector (AVEC) cycle returned complete interrupt acknowledge request. simplest cheapest this built-in chip select control logic generate AVEC signal complete interrupt acknowledge (IACK) cycle SIM. later section external memory control explains chip select logic more detail. There will need chip select output since will purely generation internal signal SIM, does mean that particular chip select will reserved this purpose cannot also used chip-select function external memory, etc.
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Freescale Semiconductor, Inc. Application Note
this instance, chip select comparator checking space identifier upper four bits address (A(23:20) which will also checks appropriate interrupt level that responding placing this data address A(3:1). other address bits logic Hence, autovector level will result $FFFF3 appearing address bus, autovector level (IRQ7) address will issue $FFFFF. example follows that illustrates implementation chip-select logic generate AVEC signal.
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This example also illustrates initialization software watchdog. This operates exactly same HC11. starting watchdog, cannot disabled until reset occurs. register called reset status register ($FFA06) contains number flags that show last cause reset HC16. these bits flag indicate existence watchdog reset. Table Generating Autovector Initializing Watchdog
LDAB STAB LDAB STAB AUTOV: #$C0 SYPCR #$FFF8 CSBAR3 #$7801 CSOR3 #$FF PFPAR enable watchdog (COP) timeout period seconds initialize Chip Base Autovector IACK cycle: A24-A11=$FFF8, blK_sz initialize Chip Option Autovector: asynchronous, Interrupt Priority Level
port pins pins this redundant: happens reset
when IRQ6 low, this autovector routine starts SEND_STRING return main loop
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Application Note Exception Handling (Interrupts)
Periodic Interrupt Real-Time Interrupt
HC11 real-time interrupt (RTI) allows user generate "ticks" regularly spaced events with four possible periods: 16.4 32.8 with 2-MHz HC11 device. HC16 much improved version this called periodic interval timer (PIT). have seen with other modules, variable system clock frequency HC16 means that modulus counter prescaler replaced four options HC11 give total options timer periods, plus additional divide 512. This results periods ranging from microseconds 15.9 seconds.
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clock source 32.78-kHz oscillator frequency (EXTAL) system clock. have interrupt level from important vector number (multiplied give vector address).
NOTE:
flag hence there clearing mechanism other than execution exception handler after interrupt occurs.
next example shows some example code initialization also includes vector exception handler.
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Table Periodic Interval Timer Setup Exception Handler
demo code. picr pitr $fa22 $fa24
INTERRUPT VECTOR pitint INITIALIZATION VECTOR ROMCODE #$0110 pitr #$0238 picr andp #$FF0F INTERRUPT ROUTINE assume EK=$F pshm #string done $fc0c send_ch $fc0f send_string
interrupt vector
period second vector $38, level interrupt mask
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pitint send_string
done string
ldaa ldab andb staa pulm
scsr wait TDRE=1 scdr
'The writes this using PIT' ,$0a, $0d,
Different Exception Levels
CPU16 seven discrete exception levels, compared with HC11's levels. Level lowest exception mask level level equivalent non-maskable interrupt (NMI) HC11 (masked CCR). Looking once again condition code registers Figure seen that there bits CPU16 which replace bits HC11. HC11, only maskable interrupt (masked bit) available on-chip peripherals, whereas seven levels possible on-chip peripherals HC16. External interrupt pins IRQ1, IRQ2 IRQ7 each generate exception request feature enabled.
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Application Note Exception Handling (Interrupts)
this case, IRQ7 direct equivalent XIRQ HC11, others used HC11 pin. fundamental difference fact that internal external exception requests handled exactly same single section system integration module (SIM). Level exception effectively disabling interrupt source.
Arbitration
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exception scheme taken directly from 68000 later microprocessors where there could very many different interrupt sources. Seven separate levels exception mask great help, complex system there need even greater control exception priorities. this reason, concept arbitration developed implemented HC16 precise. There four arbitration bits available programmer that will allow discrete levels exception priority each exception level. important that every exception source given non-zero arbitration priority that only exception source must have unique arbitration priority given exception level even arbitration logic will unable differentiate between sources same exception level. Remember that even external exception source must also have unique arbitration priorities. IARB lowest practical value arbitration. There little chance running exception levels priorities there total active levels. arbitration level means that internal arbitration switched will possible have CPU16 service interrupt from such source. This because IARB disables internal interrupt acknowledge (IIACK) signal cannot source interrupt defaults spurious interrupt vector.
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Same Exception Level
Several exceptions single exception level commonplace HC11 applications equally possible HC16. Just would expect, exception request given level locks other exceptions that same level lower. Similarly, HC11, exception vector decided after stacking operation registers completed.
NOTE:
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Here CPU16 will stack fewer registers consequently fetches exception vectors very much faster than HC11. reduced exception latency generally great advantage when converting code from HC11.
When several exceptions occur simultaneously, highest level exception arbitration will normally win. Also, subsequent higher level exception interrupt lower level exception routine. example, assuming level exception progress when level exception occurs. level exception masked will cause system stack then start executing level exception routine. exception mask subsequent level exception arbitration level cannot exception until exception mask dropped below level once more. This will happen first level routine restores CCR. this point, pending level exception immediately takes control level exception must wait while longer before resuming task. There short delay from interrupt event occurring fetching vectors. During this time, other interrupts occur same higher interrupt level. during this period that arbitration takes place. examples Figure where three types events occur.
Multiple Exception Events
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Application Note Exception Handling (Interrupts)
SAME INTERRUPT LEVEL MAIN ROUTINE
EXCEPTIONS SAME INTERRUPT LEVEL, EVENT LEAST AFTER EVENT
MAIN ROUTINE
INTERRUPT (IVL IARB INTERRUPT (IVL IARB
EXCEPTION HANDLER
EXCEPTION HANDLER
DELAY BEFORE EXCEPTION PROCESSED
ARBITRATION EFFECT SINCE OCCURS AFTER EVENT VECTORS FETCHED.
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ARBITRATION WORK MAIN ROUTINE
EXCEPTIONS SAME INTERRUPT LEVEL, EVENT AFTER EVENT
MAIN ROUTINE
INTERRUPT (IVL IARB
EXCEPTION HANDLER
EXCEPTION HANDLER
DELAY BEFORE EXCEPTION PROCESSED
INTERRUPT (IVL IARB ARBITRATION TAKES EFFECT SINCE VECTORS HAVE BEEN FETCHED.
HIGHER INTERRUPT LEVEL OCCURS DURING EXCEPTION PROCESS MAIN ROUTINE MAIN ROUTINE
EXCEPTION HANDLER
INTERRUPT (IVL IARB INTERRUPT (IVL IARB
EXCEPTION HANDLER
EXCEPTION HANDLER
EXCEPTION INTERRUPTED EXCEPTION HANDLER RUNS. WHEN COMPLETE, WILL RESUME COMPLETE TASK RETURN MAIN ROUTINE.
Figure Multiple Interrupts
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Freescale Semiconductor, Inc. Application Note
Prioritization Schemes
Prioritizing exceptions normally self evident from system specification, when converting from HC11 code worth careful consideration where required HC16. HC16 much faster than HC11 most HC11 interrupt routines will account possibility being interrupted themselves, leaving routines same level interrupt will normally work perfectly. flexibility exception scheme seem rather daunting, there just points remember: Simultaneous exceptions same interrupt level arbitrated basis IARB0-IARB3 bits each module control registers these must unique. exception same level current exception mask cannot executed until mask level reduces below that pending exception level except level exceptions. higher level exception will interrupt lower exception level routine which must then wait until exception mask returned level before continuing. Level exception highest interrupt level non-maskable exception that interrupted another level exception. arbitration level will cause spurious interrupt interrupt occurs from that module. HC11 interrupt takes same amount time instruction into interrupt routine cycles) CPU16 exception must also clear pipeline addition operations common with command command takes cycles while exception takes cycles reload stages stage pipeline). exception latencies reason moving HC16, then remember that first line exception routine guaranteed execute could PSHM instruction. Making first instruction will reduce time from maximum cycles down just cycles addition cycles entry latency cycles worst case instruction (EDIVS). Included later exception routines that perform same task, MC68HC11E9 other MC68HC16A1. similarity routines most striking feature emphasizes ease code conversion. differences easily seen will invariably follow same approach code conversion exception routine from HC11 HC16.
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Exception Routine Entry Latency
Application Note Exception Handling (Interrupts)
first difference remember save registers that used exception routine, necessarily those that used global variables. see, accumulator registers changed within routine, register used global register contains base address SRAM saved stack. routine, registers pulled back stack with same syntax pushed onto stack. assembler orders registers ensure that unstacking order reversed. register different exception routine must initialized. This requires accumulator make TBXK instruction. terms execution speed, HC16 manages perform entire exception routine 5.76 where HC11 takes 35.5 Also, worst case latency reduces from HC11's 20.5 Example HC11 Timer Output Compare Interrupt Routine
<-A-><-B-><-C-> cycles cycles minimum state cycles) duty (256 cycles) frequency (timer clock same clock) Subroutine below takes cycles (including interrupt latency) until output compare re-armed, plus IDIV FDIV instruction start executing with cycles left before done. Thus period this must cycles since rising edge must occur after re-armed. Routine takes cycles complete (35.5 MHz) with worst case entry latency cycles (20.5 MHz) interrupt latency OC2_INT TEMP_X TOC1+REGS ADDD #PERIOD (max PWM) (max time) before switch other table complete TOC1+REGS write been updated this point which routine must before high. Worst case when maximum delay (max duty cycle). ADDD compare (added OC1) ADDD prevent OC's occurring simultaneously TOC2+REGS write LDAA #%01000000 STAA TFLG1+REGS clear flag Note that only occurs soon after when there plenty time interrupt routine execute (over cycles) flag cleared after updating register. increment index increment output counter
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TEMP_X TABLE_POINTER
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Freescale Semiconductor, Inc. Application Note
Example HC16 Timer Output Compare Exception Handler
|<-a-><-b-><-c-> -|-+ +-|-a timer counts cycles minimum state timer counts) duty (256 timer counts) frequency (timer clock system clock divided minimum pulse width timer clocks. bits (256 timer clocks) subroutine below takes cycles (including interrupt latency) until output compare re-armed, plus edivs instruction start executing with cycles left before done. Thus minimum period this must cycles timer counts) since rising edge must occur after re-armed. Entry conditions ZK:IZ points SRAM location temp_x,Z temporary save register Routine takes clock cycles (5.76µs 16.66MHz with worst case entry latency clock cycles (2.28µs 16.66MHz interrupt latency oc2_int pshm d,x,k save accD,IX stack ldab accB=1 ready TBXK point data space tbxk segment temp_x,z toc1 addd #period 256(max pwm) (max time) before switch other table complete toc1 write been updated this point which routine must before high. worst case when maximum delay (max duty cycle). addd addd bclrw toc2 tflg,oc2f compare oc2(added oc1) prevent oc's occurring simultaneously write clear flag
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note that only occurs soon after when there plenty time exception routine execute flag cleared after updating register pulm increment index temp_x,z table_pointer,z increment output counter d,x,k
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Application Note External Hardware Interfacing
External Hardware Interfacing
Asynchronous Synchronous HC11 address data called synchronous since timing derived from address strobe (AS) clock. 68020 devices have asynchronous where number additional pins that handshakes communication. effect, this allows fast slow external device communicate with MPU, must wait handshake from peripheral device before continuing with portion cycle. HC16 uses techniques from 68020 devices addition chip-select circuitry allow user control entire cycle from HC16. case conversion from HC11 HC16, almost certain that user will make extensive chip-select logic reduce external hardware access external peripheral devices. reference manual describes great detail, very basic look bus, will look using external 6226 (128-Kbyte) SRAM devices will HC16. chip-select logic lets user program specific conditions chip selects function. This includes qualification with address/data strobes, address A(23:11), type address space, etc., chip select base address block size over which will function. overcome asynchronous bus, chip-select logic generates DSACK signals that would normally come from external peripheral circuit. These programmed terms wait states. This refers number cycles that HC16 must wait before complete cycle read write peripheral device. wait state equivalent 16.66-MHz clock. DSACK signal received within time monitor cycles default value), then error (BERR) signal asserted. This indicates possibility non-existent memory this address. second consecutive error indicates that completely lost will force reset.
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NOTE:
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monitor disabled after reset.
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Freescale Semiconductor, Inc. Application Note
CSBOOT line only chip select active after reset. default settings address strobe, upper lower data read/writes, asynchronous mode, wait states. This allows slowest external memory will normally altered immediately after reset speed communication with memory desired rate (normally, fastest memory operate at). chip select with zero wait states equates chip select access time (with 16.78-MHz clock).
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there only single external memory, then chip-select pins required connected memory device. This would assume that user other external devices problems with contention. This would give address access time zero wait states, remember that chip-select logic must configured this memory there will generation DSACK when accessing external memory memory will addressable. chip select logic therefore, essential operation external memory even memory chip-enable permanently connected ground.
Wait States
wait state function asynchronous SIM. Normally, 68000 system would have mixture different memory types with varying address access times. accommodate this, address/data sends address then waits handshaking signals before reading data bus. make this system operate simply possible, chip-select logic allows number cycles remain unchanged while external memory fetches data that will output bus. adding clock cycle fastest normal cycle built-in delay known wait state. 16.66 MHz, this translates wait state.
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Application Note External Hardware Interfacing
Fast Termination (Synchronous Timing)
Fast termination special case address/data timing that most commonly used with internal peripheral modules takes just clock cycles complete, compared with zero wait state memory access three clock cycles. effect, this equivalent HC11 type address/data cycle synchronous with internal clock.
NOTE:
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cycle times instructions shown terms fast termination. external memory must have access time able operate fast termination mode with 16.78 HC16. This compares with 4-MHz HC11F1 (non-multiplexed) memory address access time
Using Chip Selects
chip selects take care address control compare logic required drive external memory devices. single-chip select eight bits wide general chip-select signals range addresses with resolution Kbytes anywhere address range HC16 device. Further options upper/lower data bus, read, and/or write, wait states, type address space, qualification read cycle with address strobe data strobe asynchronous synchronous control. additional control interrupt priority level (IPL) AVEC just alternative function chip-select logic generate AVEC external described previous section exception processing.
8-Bit 16-Bit Read/Write Access 8-Bit Wide Memory Devices
following example, three chip selects connected 32-k bits wide devices (MCM60L256AP10) with access time. connected output enable pins both devices, while connected write enable pins even addressed addressed memory devices, respectively. This arrangement found controlling optional RAMs HC16Z1 EVB.
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Freescale Semiconductor, Inc. Application Note
will memory address range $80000 $8FFFF (64-k range). There 8-bit wide memories, these attach parallel 16-bit wide data bus. Address effectively determines which device written connected device because will chip-select logic perform this task Figure shows actual device connections chip-select logic HC16 bus. This means that base address both memories $80000.
NOTE:
Although memories Kbytes, block size Kbytes with memories attached different halves data bus.
Since connected upper eight bits data bus, even addresses, controls writes lower eight bits becomes addresses. memory devices 100-ns access time, since using chip selects enable device, must take access times from chip-select falling edge rather than address valid time which earlier. Appendix simplified timing diagram. This gives access time required zero wait states This clearly less time that 100-ns device manage, must wait state timing which gives extra 60-ns access time
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Example Initialization Code 16-Bit Addressing External Memories
CSOR0 CSBAR0 CSOR1 CSBAR1 CSOR2 CSBAR2 CSPAR0 LDAB TBEK #$0F select bank direct writes #$0803 CSBAR0 CSBAR1 #$50B0 CSOR0 #$30B0 CSOR1 #$0803 CSBAR2 #$78B0 CSOR2 #$3FFF CSPAR0 base addr $80000: bank base addr $8000: bank Chip Select upper byte, write only Chip Select lower byte, write only Chip Select fire base addr $80000 Chip Selects both bytes, read write Chip Selects 0,1,2, 16-bit ports $FF4C $FF4E $FF50 $FF52 $FF54 $FF56 $FA44
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Application Note External Hardware Interfacing
Hardware 8-Bit 16-Bit Addressing Using Single-Chip Select
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normal practice CSBOOT line select separate memory devices (often EPROMs) since this only chip select active following reset. some cases, however, desired write both 8-bit 16-bit values which selected using CSBOOT. example this HC16Z1 evaluation board where main emulation memory selected CSBOOT. HC16 read 8-bit value correctly with single chip select connected both memories because CPU16 will only read relevant data. Writing byte different matter same setup earlier, 8-bit write would cause write both memories with same data each byte. Thus, write would appear write $5555. cure this, chip select must gated with signals that indicate byte write address written. chip select bits, rather than directly output enable pins both memory devices, gated SIZ0 lines. SIZ0 line logic during byte read write operation address line used determine which memory devices written SIZ1 indicates even address read write required equation that follows because function extra logic prevent writes wrong memory device. This approach makes external logic much simpler. Thus simple logic equation results chip-select lines with slightly delayed timing compared with original chip select. chip select delay maximum with circuit described Figure Thus, 85-ns access time would require extra wait state added chip-select access time (zero wait states 16.6 MHz). Taking chip select CSBOOT, have following equations high memory chip enable pins. logic equations are: CSLOW SIZ0 CSBOOT CSHIGH SIZ0 ./A0 CSBOOT This done either PAL, such 16L8, with 74HC00 devices.
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Freescale Semiconductor, Inc. Application Note
SIZ0
CSlow
CSBOOT
CShigh
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BYTE WORD ADDRESSING USING CSBOOT
Figure 16-Bit Address Read Write Access with CSBOOT VDDE VDDI VDDA device with many different modules board real problem designers. Some modules generate great deal noise supplies because they switching loads very quickly (for example, address data ports), while other modules require noise free supply possible (for instance, PLL). overcome some these problems, HC16 four separate power supplies. VDDI VSSI internal power supply pins. This powers CPU, internal logic internal logic other modules. Power consumption relatively consistent, with sudden changes impedance. VDDE VSSE power supply external logic. This supply have large swings current consumption pins switch off. VDDA VSSA supply analog-to-digital converter (ADC). Since module 10-bit accuracy, important have little noise these power supply pins possible. 10-bit accuracy means resolution just 3-mV peak peak with 3-volt reference voltage differential.
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Application Note External Hardware Interfacing
VDDSYN special power supply just circuit. Just with ADC, internal voltages very susceptible noise internal analog section circuit affected changes voltage little effect noise VDDSYN alter frequency small amount. VSTBY SRAM standby power should treated VDDI supply. also grounded avoid SRAM being disabled lowering VDDI supply below VSTBY voltage.
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0.01 CAPACITOR
CAPACITOR
VDDE
VSSE HC16 DEVICE
PLACE CAPACITORS NEAR HC16 PINS POSSIBLE
Figure Shows Suggested Decoupling Close HC16 Pins Possible These Pairs Power Pins
Minimum Required Connections
rather more complex than address/data section HC11 take while learn, many features have defaults that enable user place device into application with minimum fuss with external connections. Figure shows HC16 same application HC11 Figure
NOTE:
Unused input pins should tied 10-k resistors. Note changes address data interface connections module particular.
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Freescale Semiconductor, Inc. Application Note
Points note about HC16 application include: HC16 data internal pullup resistors internally SIM. There several power supply pairs, which must connected power each pair should suppressed with 0.01 capacitor reduce system noise. Take particular care over noise suppression VDDSYN. Mode selection after reset 74HC244 device.
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memories need doubling make full speed HC16. single 8-bit wide data used reduces performance system significantly. Four chip selects used. EPROM byte word read access, byte word read write access. EPROM uses select device lower 32-k part 64-k block, CSBOOT line selects bank this case bank0). Many pins input output depending upon mode after reset, pullup resistors have been shown these cases. Many could removed specific modes operation.
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XTAL 27C128 KBYTES MC68HC11E9 MODA EXTAL MC68HC11E9 EXPANDED MODE 74HC373 MODB /VSTBY
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MOSI MISO
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XIRQ RESET
MCM60L256 KBYTES
RESET
Application Note External Hardware Interfacing
Figure HC11 with External Memory
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ADDRESS
Application Note
CHIP SELECT
KBYTES 74HC244
BYTE HIGH BYTE 27C128 KBYTES CSBOOT BR/CS0 BG/CS1 BGACK/CS2 FC0/CS3 FC1/CS4 FC2/CS5 A19/CS6 A20/CS7 A21/CS8 A22/CS9 ECLK/A23/CS10 27C128 A(0:18)
MC68HC16Z1SYSTEM
PWMA PWMB
PCLK
OC2/OC1 OC3/OC1 OC4/OC1 IC4/OC5/OC1
DATA DATA
DATA
PCS0/SS PSC1 PSC2 PSC3 MISO MOSI DSACK0 DSACK1 AVEC SIZ0 SIZ1 DD(0:15) RESET RESET
VDDA
0.01 VSSA
QAA0
VOLTAGE REFERENCE SRAM CPU16
HALT BERR MODCK IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7
BYTE
HIGH BYTE
CLKOUT
CLOCK
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MCM60L256 KBYTES 0.01 VSTBY IPIPE0/DS0 IPIPE1/DSI BKPT/DSCLK XTAL EXTAL VDDSYN TSTME/TSC TEST FREEZE/QUOT
MCM60L256 KBYTES
QAA1 QAA2 QAA3 QAA4 QAA5 QAA6 QAA7 QBA0 QBA1 QBA2 QBA3 QBA4 QBA5 QBA6 QBA7
VBattery
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Figure HC16 with External Memory
Application Note Debugging Tools
Debugging Tools
Background Mode Those experienced using PCBUG11 HC11 device will find background mode HC16 very familiar. This mode intended just debug purposes would normally used finished application, although application could leave access mode later problem solving. Background debug mode uses three dedicated pins that only direct connection CPU16. communication with CPU16 similar synchronous serial communication, with clock (DSCLK) transmit receive pins (DSO DSI, respectively). general, user will unaware background mode operation, used most emulation systems basis MC68HC16. There small number commands which built software running make normal emulator commands. Thus, dump block bytes memory will translated into reads memory contents specified addresses which sequential. programmer enter background debug mode with CPU16 instruction BGND. ample explanation background mode found M68HC16 Family Reference Manual, Motorola document order number CPU16RM/AD. Evaluation Board EVB16 software provides sophisticated debug tool with very little external hardware. EVB16Z1 emulator HC16Z1 device sockets Kbytes RAM, HC16Z1 device, course, background mode connector parallel port There little requirement much else background debug mode software provide high degree debug capability, including instructions trace buffer assembly source level debug name just features. logic analyzer clips used perform real-time analysis code running special groups pins these clips. There ample information available from Motorola concerning other related products.
AN461 MOTOROLA
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