AN2153 Freescale Semiconductor, Inc. Serial Bootloader Repro
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Freescale Semiconductor, Inc.
Serial Bootloader Reprogramming MC9S12DP256 FLASH Memory
Gordon Doughman Field Applications Engineer, Software Specialist Dayton, Ohio
Introduction
MC9S12DP256 member M68HC12 Family 16-bit microcontrollers (MCU) containing 262,144 bytes bulk sector erasable, word programmable FLASH memory arranged four 65,536 byte blocks. Including FLASH memory, rather than EPROM ROM, microcontroller significant advantages. manufacturer, placing system firmware FLASH memory provides several benefits. First, firmware development extended late into product development cycle eliminating masked lead times. Second, when manufacturer several products based same microcontroller, help eliminate inventory problems lead times associated with ROM-based microcontrollers. Finally, severe found product's firmware during manufacturing process, in-circuit reprogrammability FLASH memory prevents manufacturer from having scrap work-in-process. ability FLASH memory electrically erased reprogrammed also provides benefits manufacturer's customers. customer's products updated enhanced with features capabilities without having replace components return product factory.
Motorola, Inc., 2001
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Freescale Semiconductor, Inc. Application Note
Unlike M68HC11 Family, MC9S12DP256 does have bootstrap containing firmware allow initial programming FLASH directly through on-chip serial communications interface (SCI) ports. Initial on-chip FLASH programming requires either special test handling equipment program device before placed target system background debug module (BDM) programming tool available from Motorola third party vendor. MC9S12DP256's four on-chip FLASH arrays contain variable size, erase protectable areas shown Figure While majority bootloader could contained protected areas, protected high area $C000-$FFFF memory range must least contain reset interrupt vectors that point jump table. most cases, unless complex sophisticated communication protocol required that will into easiest place entire bootloader into protected high area block zero. Erasing programming on-chip FLASH memory MC9S12DP256 presents some unique challenges. Even though FLASH block zero separate erase protected areas, code cannot either protected area while remainder block erased programmed. While possible code from FLASH block while erasing reprogramming another, adopting such strategy would complicate overall implementation bootloader. Consequently, during erase reprogram process, code must reside other on-chip memory external memory. addition, because reset interrupt vectors reside erase protected area, they cannot changed. This necessitates secondary reset/interrupt vector table placed outside protected FLASH memory area. remainder this application note explores requirements serial bootloader implementation programming algorithm MC9S12DP256's FLASH.
Freescale Semiconductor, Inc.
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Application Note Overview MC9S12DP256's FLASH
$0000
Flash Control Registers Register Base $100
$4000 Protected Area 0.5K,
Block Block Block Block
Freescale Semiconductor, Inc.
$8000 Paged Memory $C000
$FF00 $FF0F, Access Key, Protection, Security
$FFFF
Protected High Area
Figure MC9S12DP256 Memory
Overview MC9S12DP256's FLASH
MC9S12DP256's on-chip FLASH memory composed four 65,536 byte blocks. Each block arranged 32,768 16-bit words read bytes, words, misaligned words. Access time cycle bytes aligned words reads cycles misaligned word reads. Write operations program erase operations performed only aligned word. Each 64-K block organized 1024 rows words. erase sector contains rows bytes. Erase operations performed sector small bytes entire 65,536-byte block. erased word reads $FFFF programmed word reads $0000.
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Freescale Semiconductor, Inc. Application Note
programming voltage required program erase FLASH generated internally on-chip charge pumps. Program erase operations performed command driven interface from microcontroller using internal state machine. completion program erase operation signaled setting CCIF flag optionally generate interrupt. FLASH blocks programmed erased same time; however, possible read from FLASH block while being erased programmed.
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Each 64-K block contains hardware interlocks which protect data from accidental corruption. shown Figure upper block zero accessed through 16-Kbyte PPAGE window fixed address 16-K address ranges. protected area located upper address area fixed page address range from $C000-$FFFF normally used bootloader code. Another area located lower portion fixed page address range from $4000-$7FFF. Additional protected memory areas present three remaining 64-K FLASH blocks; however, they only accessible through 16-K PPAGE window.
FLASH Control Registers
control status registers four FLASH blocks occupy bytes input/output (I/O) register area. accommodate four FLASH blocks while occupying minimum register address space, FLASH control register address range divided into sections. first four registers, shown Figure apply four memory blocks. remaining bytes register space have duplicate sets registers, each FLASH bank. active register bank selected BKSEL bits unbanked FLASH configuration register (FCNFG). Note that only three banked registers contain usable status control bits; remaining nine registers reserved factory testing unused.
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Application Note Overview MC9S12DP256's FLASH
FCLKDIV FSEC Reserved FCNFG Unbanked Banked FDIVLD KEYEN CBEIE
PRDIV8 CCIE
FDIV5 KEYACC
FDIV4
FDIV3
FDIV2
FDIV1 SEC01 BKSEL1
FDIV0 SEC00 BKSEL1 $x100 $x101 $x102 $X103
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FPROT FSTAT FCMD Reserved
FPOPEN CBEIF
CCIF ERASE
FPHDIS PVIOL PROG
FPHS1 ACCERR
FPHS0
FPLDIS BLANK ERVER
FPLS1
FPLS0 MASS
$X104 $X105 $X106 $X107- $x10F
Figure FLASH Status Control Registers
FLASH Protection
protected areas each FLASH block controlled four bytes FLASH memory residing fixed page memory area from $FF0A-$FF0D. During microcontroller reset sequence, each four banked FLASH protection registers (FPROT) loaded from values programmed into these memory locations. shown Figure location $FF0A controls protection block three, $FF0B controls protection block two, $FF0C controls protection block one, $FF0D controls protection block zero. values loaded into each FPROT register determine whether entire block just subsections protected from being accidentally erased programmed. mentioned previously, each 64-K block have protected areas. these areas, known lower protected block, grows from middle 64-K block upward. other, known upper protected block, grows from 64-K block downward. general, upper protected area FLASH block zero used hold bootloader code since contains reset interrupt vectors. lower protected area block zero protected areas other FLASH blocks used critical parameters that would change when program firmware updated.
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Freescale Semiconductor, Inc. Application Note
FPOPEN each FPROT register determines whether entire FLASH block subsections programmed erased. When FPOPEN erased (1), remainder bits register determine state protection size each protected block. programmed state (0), entire FLASH block protected state remaining bits within FPROT register irrelevant.
Address $FF00-$FF07 Description Security back door comparison Reserved Protection byte FLASH block Protection byte FLASH block Protection byte FLASH block Protection byte FLASH block Reserved Security byte
Freescale Semiconductor, Inc.
$FF08-$FF09 $FF0A $FF0B $FF0C $FF0D $FF0E $FF0F
Figure FLASH Protection Security Memory Locations FPHDIS FPLDIS bits determine protection state upper lower areas within each 64-K block respectively. erased state these bits allows erasure programming protected areas renders state FPHS[1:0] FPLS[1:0] bits immaterial. When either these bits programmed, FPHS[1:0] FPLS[1:0] bits determine size upper lower protected areas. tables Figure summarize combinations FPHS[1:0] FPLS[1:0] bits size protected area selected each.
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Application Note Overview MC9S12DP256's FLASH
FPHS[1:0]
Protected Size
FPLS[1:0]
Protected Size bytes
Figure FLASH Protection Select Bits
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FLASH protection registers loaded during reset sequence from address $FF0D FLASH block $FF0C FLASH block $FF0B FLASH block $FF0A FLASH block This indicated reset register diagram MC9S12DP256 data book. This register determines whether whole block subsections block protected against accidental program erase. Each FLASH block have protected areas, starting from relative address $8000 (called lower) toward higher addresses other growing downward from $FFFF (called higher). While later mainly targeted hold bootloader code since covers vector space (FLASH other area used keep critical parameters. Trying alter protected areas will result protect violation error, PVIOL will FLASH status register FSTAT.
NOTE:
mass bulk erase full 64-Kbyte block only possible when FPLDIS FPHDIS bits erased state.
FLASH Security
security microcontroller's program data memories long been concern companies main reason. Because considerable time money that invested development proprietary algorithms firmware, extremely desirable keep firmware associated data from prying eyes. This especially difficult problem earlier M68HC12 Family members background debug module (BDM) interface provided easy, uninhibited access FLASH EEPROM contents using 2-wire connection. Later revisions original Family parts provided method that
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Freescale Semiconductor, Inc. Application Note
allowed customer's firmware disable interface (BDM lockout) once part been placed circuit programmed. While this prevents FLASH EEPROM from being easily accessed in-circuit, does prevent Family part from being removed from circuit placed expanded mode FLASH EEPROM read. security features MC9S12DP256 have been greatly enhanced. While security feature percent guaranteed prevent access MCU's internal resources, MC9S12DP256's security mechanism makes extremely difficult access FLASH EEPROM contents. Once security mechanism been enabled, access FLASH EEPROM either through expanded inhibited. Gaining access either these resources accomplished only erasing contents FLASH EEPROM through built-in back door mechanism. While having back door mechanism seem weakness security mechanism, target application must specifically support this feature operate. Erasing FLASH EEPROM accomplished using methods. first method requires resetting target special single-chip mode using interface. When secured device reset special single-chip mode, special security becomes active. program this small performs blank check FLASH EEPROM memories. both memory spaces erased, firmware temporarily disables device security, allowing full functionally. However, FLASH EEPROM blank, security remains active only hardware commands remain functional. this mode, commands restricted reading writing register space. Because other commands on-chip resources disabled, contents FLASH EEPROM remain protected. This functionality adequate manipulate FLASH EEPROM control registers erase their contents.
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NOTE:
interface erase FLASH EEPROM memories present initial mask (0K36N) MC9S12DP256. Great care must exercised ensure that microcontroller programmed secure state unless back door mechanism supported target firmware.
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Application Note Overview MC9S12DP256's FLASH
second method requires microcontroller connected external memory devices reset expanded mode where program executed from external memory erase FLASH EEPROM. This method preferred before parts placed target system. shown Figure security mechanism controlled least significant bits security byte. Because only unsecured combination when SEC1 value SEC0 value microcontroller will remain secured even after FLASH EEPROM erased, since erased state security byte $FF. previously explained, even though device secured after being erased, part reset special single-chip mode, allowing manipulation microcontroller interface. However, after erasing FLASH EEPROM, microcontroller placed unsecured state programming security byte with value $FE. Note that because FLASH must programmed aligned word time because security byte resides address ($FF0F), word $FF0E must programmed with value $FFFE.
SEC[1:0] Security State Secured Secured Unsecured Secured
Freescale Semiconductor, Inc.
Figure Security Bits Utilizing FLASH Security Back Door normal single-chip normal expanded operating modes, security mechanism temporarily disabled only through back door access feature. Because back door mechanism requires support target firmware, impossible back door mechanism used defeat device security unless capability designed into target application. disable security, firmware must have access 64-bit value stored security back door comparison located FLASH memory from $FF00-$FF07.
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Freescale Semiconductor, Inc. Application Note
operating single-chip mode, would typically provided firmware through on-chip serial ports. addition, back door security bypass must enabled leaving most significant Security byte $FF0F erased. disable back door security bypass feature, this should programmed zero. Once application receives 64-bit key, must KEYACC FCNFG register. After setting KEYACC bit, firmware must write received 64-bit security back door comparison memory locations ($FF00-$FF07) four 16-bit words, sequential order. Finally, KEYACC must cleared. four 16-bit words written comparison memory area matched corresponding values stored FLASH, will unsecured forcing SEC[1:0] bits FSEC register unsecured state. Note that this operation only temporarily disables device security. next time reset, SEC[1:0] bits will loaded from security byte $FF0F
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FLASH Program Erase Overview
FLASH program erase timings handled hardware state machine, freeing perform other tasks during these operations. timebase state machine derived from oscillator clock programmable down counter. Program erase operations accomplished writing values FCMD register. Four commands recognized current implementation summarized Figure
Command Other Operation Memory program Sector erase Mass erase Erase verify Illegal Description Program aligned word, bytes Erase 512-byte sector Erase 64-Kbyte block Verify erasure 64-Kbyte block Generate access error
Figure FLASH Program Erase Commands
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Application Note Overview MC9S12DP256's FLASH
Freescale Semiconductor, Inc.
command register associated address data registers implemented 2-stage first first (FIFO) command buffer. This configuration allows command issued while hardware state machine completes previously issued command. main reason this design decrease programming time. Without 2-stage FIFO command buffer, programing voltage would have removed from FLASH array each program command avoid exceeding high voltage active time, tHV, specification. Applying removing programming voltage after each program command would double time required program aligned word. program commands continuously available state machine, will keep high voltage applied array program command operates same 64-byte row. command second stage FIFO buffer changed, address within same 64-byte command buffer empty, high voltage will removed reapplied with command required. development multitasking environment where perform other tasks while performing program erase operations, FLASH module control registers provide ability generate interrupts when command completes command buffer empty. When command buffers empty interrupt enable (CBEIE) set, interrupt generated whenever command buffers empty interrupt flag (CBEIF) set. When command complete interrupt enable (CCIE) set, interrupt generated when command complete interrupt flag (CCIF) set. Note that CCIF flag completion each command while CBEIF when both stages FIFO empty.
NOTE:
Because interrupt vectors located FLASH block zero, memory locations block zero cannot erased programmed when utilizing FLASH interrupts target application.
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Freescale Semiconductor, Inc. Application Note
FLASH Erasure previously discussed, each 64-K block organized 1024 rows words. erase sector contains rows bytes. Erase operations performed sector small bytes entire 65,536 byte block. erased word reads $FFFF programmed word reads $0000. Program erase operations very similar, differing only command written FCMD register data written FLASH memory array. FLASH state machine erase verify command operation depicted flowchart Figure
Freescale Semiconductor, Inc.
WRITE BKSEL[1:0] BITS
CLEAR CBEIF FLAG
WRITE PPAGE REGISTER
ACCERR PVIOL FLAG
FLASH ARRAY PROTECTED COMMAND
CBEIF FLAG
DELAY CYCLES
WRITE ALIGNED DATA WORD
CCIF FLAG
COMMAND COMPLETED
WRITE COMMAND FCMD REGISTER
Figure Erase Verify Flowchart Before beginning either erase program operation, necessary write value FCLKDIV register. value written FCLKDIV register programs down counter used divide oscillator clock, producing 150-kHz 200-kHz clock source used drive FLASH memory's state machine. most significant FCLKDIV register, when set, indicates that register been
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Application Note Overview MC9S12DP256's FLASH
initialized. FDIVLD clear, indicates that register been written since part last reset. Attempting erase program FLASH without initializing FCLKDIV register will result access error command will executed. combination PRDIV8 FDIV[5:0] bits used divide oscillator clock 150-kHz 200-kHz range required FLASH's state machine. PRDIV8 used control 3-bit prescaler. When set, oscillator clock will divided eight before being 6-bit programmable down counter. Note that oscillator clock greater than 12.8 MHz, PRDIV8 must obtain proper state machine clock source using FDIV[5:0] bits. formulas determining proper value FDIV[5:0] bits shown Figure
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(OSCCLK 12.8 MHz) PRDIV8 else PRDIV8 (PRDIV OSCCLK else OSCCLK FCLKDIV[5:0] INT((CLK 1000) 200) FCLK (FCLKDIV[5:0]
Figure FCLKDIV Formulas formulas, OSCCLK represents reference frequency present EXTAL pin, frequency output. function always rounds toward zero FCLK represents frequency clock signal that drives FLASH's state machine.
NOTE:
Erasing programming FLASH with oscillator clock less than should avoided. Setting FCLKDIV such that state machine clock less than destroy FLASH high voltage over stress. Setting FCLKDIV such that state machine clock greater than result improperly programmed memory locations.
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Freescale Semiconductor, Inc. Application Note
After initializing FCLKDIV register with proper value, PPAGE register BKSEL[1:0] bits must initialized. PPAGE register must written with value that places correct 16-K memory block PPAGE window that contains memory area erased. mass (bulk) erase operation performed 64-K blocks, PPAGE register written with four PPAGE values associated with 64-K block. Note that when performing mass sector erase address range fixed pages, $4000-$7FFF $C000-$FFFF, value PPAGE register unimportant. BKSEL[1:0] bits, located FCNFG register, used select banked status control registers associated with 64-K FLASH block which erase operation performed. shown Figure value FLASH block number decreases with increasing PPAGE values. Closely examining Figure reveals that correct value BKSEL[1:0] bits one's complement PPAGE[3:2] register bits. Even though flowchart shows block select bits being written before PPAGE register, these registers written reverse order. This makes code implementation straight forward since value block select bits easily derived from value written PPAGE register. After initializing PPAGE register block select bits, command buffer empty interrupt flag (CBEIF) should checked ensure that address, data command buffers empty. CBEIF set, buffers empty program erase command sequence started. next three steps flowchart must strictly adhered intermediate writes FLASH control status registers reads FLASH block which operation being performed will cause access error (ACCERR) flag operation will immediately terminated. mass erase operation, address aligned data word valid address 64-K block. sector erase, only upper seven address bits significant, lower eight bits ignored. erase operations, data written FLASH block ignored.
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Application Note Overview MC9S12DP256's FLASH
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After writing program erase command FCMD register, CBEIF must written with value clear CBEIF initiate command. After clearing CBEIF bit, ACCERR PVIOL bits should checked ensure that command sequence valid. either these bits set, indicates that erroneous command sequence issued command sequence will immediately terminated. Note that either both ACCERR PVIOL bits set, they must cleared writing each flag's associated position before another command sequence initiated. Five cycles after CBEIF cleared, CCIF flag will cleared state machine indicating that command successfully begun. previous command been issued, CBEIF will become set, indicating that address, data, command buffers available begin command sequence. Once erase command completed, erasure sector block should verified ensure that locations contain $FF. When erasing 512-byte sector, each byte word must checked erased condition using software. Fortunately, however, state machine verify command built into hardware perform erase verify contents 64-K blocks. command sequence used perform erase verify identical that performing erase command except that erase verify command ($05) written FCMD register block select bits PPAGE register need rewritten. locations 64-K block erased, successful erase verify will cause BLANK FSTAT register set. Note that BLANK must cleared writing associated position before next erase verify command issued.
FLASH Programming
mentioned previous section, erase program operations follow nearly identical flow. There are, however, some minor changes flow that improve efficiency programming process. take advantage decreased programming time provided 2-stage FIFO command buffer, must kept full with programming commands. flowchart Figure shows, rather than waiting each programming command complete, programming command issued soon CBIEF flag set. This allows programming voltage remain applied array long next
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Freescale Semiconductor, Inc. Application Note
aligned word address remains within same 64-byte row. Therefore, minimize programming times, blocks data programmed into FLASH array should begin 64-byte boundary multiple bytes. Verification programmed data should performed only after block data been programmed programming commands have completed. Performing read operation FLASH array while programming command executing will cause ACCERR flag current pending commands terminated.
Freescale Semiconductor, Inc.
WRITE BKSEL[1:0] BITS
CLEAR CBEIF FLAG
WRITE PPAGE REGISTER
ACCERR PVIOL FLAG
FLASH ARRAY PROTECTED COMMAND
CBEIF FLAG
DELAY CYCLES
WRITE ALIGNED DATA WORD
DONE WITH DATA BLOCK
BLOCK PROGRAM COMPLETED
WRITE COMMAND FCMD REGISTER
Figure Programming Flowchart
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Application Note General FLASH Serial Bootloader Requirements
General FLASH Serial Bootloader Requirements
program such FLASH serial bootloader important requirements. First, must have minimal impact final product's software performance. Second, should little cost hardware design. Because MC9S12DP256 includes variety on-chip communications modules, five modules, J1850 module, ports, three modules, additional external hardware should required. Designs incorporating J1850 network connection could easily incorporate existing connection into bootloader download FLASH data. applications utilizing network connection basic design, ports used. many systems, part hardware design since often used diagnostic port. RS232 level translator included part system design, small adapter board constructed containing level translator RS232 connector. This board then used service personnel update system firmware. Using such adapter board prevents cost level translator connector from being added each system. addition port, single input required notify serial bootloader startup code execute bootloader code jump system application program. mentioned previously, because MC9S12DP256's interrupt reset vectors reside protected bootblock, they cannot changed without erasing bootblock itself. Even though possible erase reprogram bootblock, inadvisable anything goes wrong during process reprogramming bootblock, would impossible recover from situation without programming hardware. this reason, bootloader should include support secondary interrupt reset vector table located just below protected bootblock area. Each entry secondary interrupt table should consist 2-byte address mirroring primary interrupt reset vector table. secondary interrupt reset vector table utilized having each vector point single instruction that uses CPU12's indexed-indirect program counter relative addressing mode. This form instruction uses four bytes
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Freescale Semiconductor, Inc. Application Note
memory requires just clock cycles execute. systems operating maximum speed 25.0 MHz, cycles adds only interrupt latency. most applications, this small amount additional time will affect overall performance system.
Bootloader S-Record Format
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S-record object file format designed allow binary object code and/or data represented printable ASCII hexadecimal format allowing easy transportation between computer systems development tools. M68HC12 Family members supporting less than Kbytes address space, records, which contain 16-bit address, sufficient specify location device's memory space where code and/or data loaded. load address contained record generally corresponds directly address on-chip off-chip memory device. M68HC12 devices that support address space greater than Kbytes, records sufficient. Because M68HC12 Family 16-bit microcontroller with 16-bit program counter, cannot directly address total more than Kbytes memory. enable M68HC12 Family address more than Kbytes program memory, paging mechanism designed into architecture. Program memory space expansion provides window 16-Kbyte pages that located from $8000-$BFFF. 8-bit paging register, called PPAGE register, provides access maximum 256, 16-Kbyte pages megabytes program memory. While there never devices that contain this much on-chip memory, MC68HC812A4 capable addressing this much external memory. addition, MC9S12DP256 contains Kbytes on-chip FLASH residing address space. While many high-level debuggers capable directly loading linked, absolute binary object files into target system's memory, bootloader does have that ability. bootloader only capable loading object files that represented S-record format. Because records only contain 16-bit address, they inadequate specify load address memory space greater than Kbytes. records, which contain 24-bit load address, were originally defined loading object files into memory space M68000 Family. would seem
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Application Note General FLASH Serial Bootloader Requirements
that records would provide necessary load address information required M68HC12 object files. However, those familiar with M68000 Family know, M68000 linear (non-paged) address space. Thus, development tools, such non-volatile memory device programmers, interpret 24-bit address simple linear address when placing program data into memory devices. Because M68HC12 memory space expansion based 16-Kbyte pages, there direct one-to-one mapping 24-bit linear address contained record 16-Kbyte program memory expansion space. Instead defining S-record type utilizing existing S-record type non-standard manner, bootloader's program FLASH command views MC9S12DP256's memory space simple linear array memory that begins address $C0000. This same format which S-records would need presented stand alone non-volatile memory device programmer. MC9S12DP256 implements bits PPAGE register which gives program memory address space that accessed through PPAGE window addresses $8000-$BFFF. lower 768-K portion address space, accessed with PPAGE values $00-$2F, reserved external memory when part operated expanded mode. upper address space, accessed with PPAGE values $30-$3F, occupied on-chip FLASH memory. mapping between linear address contained S-record 16-Kbyte page viewable through PPAGE shown Figure generation S-records that meet these requirements responsibility linker and/or S-record generation utility provided compiler/assembler vendor. Cosmic Software's linker S-record generation utility capable producing properly formatted S-records that used bootloader. Other vendor's tools posses this capability. those compilers assemblers that produce "banked" S-records, S-record conversion utility, SRecCvt.exe, available that used convert "banked" S-records linear S-record format required serial bootloader.
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NOTE:
bootloader limited receiving S-records containing maximum bytes code/data field. S-record containing more than bytes code/data field received, error message will displayed.
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Freescale Semiconductor, Inc. Application Note
PPAGE Value $00-$2F
S-Record Address Range $00000-$BFFFF $C0000-$C3FFF $C4000-$C7FFF $C8000-$CBFFF $CC000-$CFFFF $D0000-$D3FFF $D4000-$D7FFF $D8000-$DBFFF $DC000-$DFFFF $E0000-$E3FFF $E4000-$E7FFF $E8000-$EBFFF $EC000-$EFFFF $F0000-$F3FFF $F4000-$F7FFF $F8000-$FBFFF $FC000-$FFFFF
Memory Type Off-chip memory On-chip FLASH On-chip FLASH On-chip FLASH On-chip FLASH On-chip FLASH On-chip FLASH On-chip FLASH On-chip FLASH On-chip FLASH On-chip FLASH On-chip FLASH On-chip FLASH On-chip FLASH On-chip FLASH On-chip FLASH On-chip FLASH
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Figure MC9S12DP256 PPAGE S-Record Address Mapping conversion linear S-record load address PPAGE number PPAGE window address performed formulas shown Figure first formula, PageNum value written PPAGE register, PPAGEWinSize size PPAGE window which $4000. second formula, PPAGEWinAddr address within PPAGE window where S-record code/data loaded. PPAGEWinStart beginning address PPAGE window which $8000.
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Application Note General FLASH Serial Bootloader Requirements
pageNum SRecLoadAddr PPAGEWinSize; PPAGEWinAddr (SRecLoadAddr PPAGEWinSize) PPAGEWinStart;
Figure PPAGE Number Window Address Formulas Using S-Record Bootloader S-record bootloader presented this application note utilizes on-chip communications with host computer does require special programming software host. bootloader presented this application note used erase reprogram upper on-chip FLASH memory. bootloader program utilizes on-chip communications does require special programming software host computer. only host software required simple terminal program that capable communicating 9600 115,200 baud supports XOn/XOff handshaking. Invoking bootloader causes prompt shown Figure displayed host terminal's screen. lowercase ASCII characters through comprise three valid bootloader commands. These three lowercase characters were selected, rather than ASCII characters through prevent accidental command execution. problem occurs while programming FLASH, error message displayed, bootloader will redisplay prompt wait command entry from operator. Because host computer will continue sending S-record file, each character S-record file would interpreted operator command entry. Since S-records contain ASCII numeric characters, highly likely that them would understood valid command.
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MC9S12DP256Bootloader Erase Flash Program Flash Baud Rate
Figure Serial Bootloader Prompt
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Freescale Semiconductor, Inc. Application Note
Erase FLASH Command Selecting erase function typing lowercase terminal will cause bulk erase four 64-K FLASH arrays except boot block upper 64-K array where S-record bootloader resides. After erase operation completed, verify operation performed ensure that locations were properly erased. erase operation successful, bootloader's prompt redisplayed. locations were found contain value other than $FF, error message displayed screen bootloader's prompt redisplayed. MC9S12DP256 device will erase after attempts, device damaged.
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Program FLASH Command
increase efficiency programming process, S-record bootloader uses interrupt driven, buffered serial conjunction with XOn/XOff software handshaking control S-record data flow from host computer. This allows bootloader continue receiving S-record data from host computer while data from previously received S-record programmed into FLASH. terminal program must support XOn/XOff handshaking properly reprogram MC9S12DP256's FLASH memory. Typing lowercase terminal causes bootloader enter programming mode, waiting S-records sent from host computer. bootloader will continue receive process S-records until receives file record. object file being sent bootloader does contain record, bootloader will return prompt will continue wait file record. Pressing system's reset switch will cause bootloader return prompt. FLASH memory location will program properly, error message displayed terminal screen bootloader's prompt redisplayed. MC9S12DP256 device will program after attempts, device damaged S-record with load address outside range available on-chip FLASH have been received. S-record data must have load addresses range $C0000-$FFFFF. This address range represents upper Kbytes 1-MB address space MC9S12DP256.
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Application Note Bootloader Software
Baud Rate Command
While default communications rate bootloader 9600 baud, this speed much slow majority MC9S12DP256's FLASH programmed; however, provides best compatibility initial communications with most terminal programs. baud rate command allows bootloader communication rate four standard baud rates. Using baud rate 57,600 allows entire FLASH programmed just under minutes. Typing lowercase terminal causes prompt shown Figure displayed host terminal's screen. Entering number through keyboard will select associated baud rate issue secondary prompt indicating that terminal baud rate should changed. After changing terminal baud rate, pressing enter return will return main bootloader prompt. selected baud rate will remain until target system reset.
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9600 38400 57600 115200 Change Terminal Press Return
Figure Change Baud Rate Prompt
Bootloader Software
software implementing serial FLASH bootloader, shown Code Listing, consists seven basic parts: startup code, bootloader control loop, programming erase code, serial communications routines, S-record loader secondary interrupt vector jump table. code written position independent manner that generated object code will execute properly from address.
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Freescale Semiconductor, Inc. Application Note
Startup Code bootloader startup code implements several setup initialization tasks. first action performed startup code checks state port logic present, instruction will continue execution address stored reset vector secondary vector table. logic present port execution continues label Boot where watchdog timer disabled. After watchdog timer disabled, bootloader copies itself into upper on-chip RAM. Execution bootloader code from necessary portion FLASH block zero occupied bootloader erased programmed. Notice that only code between labels BootStart BootLoadEnd copied into RAM. This does include secondary vector jump table primary interrupt vector addresses since neither required bootloader. After copy operation complete, relocated overlay upper FLASH memory between $D000 $FFFF. Writes INITRM register into effect until clock after write cycle occurs. This means that cannot accessed address until after this clock delay. Normally, store instruction would simply followed with instruction ensure that unintended operations occurred. However, this case because being moved into same address space where executing, free cycle must follow write cycle.
Freescale Semiconductor, Inc.
NOTE:
understand store instruction must extended addressing must aligned even byte boundary, necessary examine cycle-by-cycle execution detail store instruction. STAB instruction using extended addressing requires three clock cycles when executed from internal memory. These three clock cycles consist cycle, cycle cycle (PwO). cycle program word access cycle where program information fetched aligned 16-bit word. cycle 8-bit data write. Finally, cycle optional cycle that used adjust instruction alignment instruction queue. cycle free cycle program word access cycle (P). When first byte instruction with number bytes misaligned address), cycle becomes
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Application Note Bootloader Software
Freescale Semiconductor, Inc.
cycle maintain queue order. first byte aligned even address), cycle cycle. Consequently, first byte STAB instruction using extended addressing aligned even byte boundary, cycle will cycle. This will then provide cycle delay required while overlaying FLASH. Because default address INITRM register direct page addressing range, most assemblers will direct rather than extended addressing. greater than character appearing first character operand field STAB instruction used force extended addressing. Note that some assemblers recognize this modifier character. main reason relocating RAM, rather than executing bootloader RAM's default address, allow SCI0 interrupt vector changed. Because on-chip higher priority memory decoding logic than on-chip FLASH, overlaying FLASH with on-chip causes accessed rather than FLASH. fact that bootloader's communications routines utilize buffered, interrupt driven mode, SCI0 interrupt vector must initialized point bootloader's interrupt service routine. After relocating on-chip RAM, startup code initializes engages clock. values REFDV SYNR registers calculated assembler based values oscillator frequency (OscClk), final frequency (fEclock), desired reference frequency (RefClock). this case, final frequency specified 24.0 MHz. Because this integer multiple oscillator frequency, oscillator frequency used reference clock PLL. This results value zero being written REFDV register. obtain clock MHz, reference frequency must multiplied three. value written SYNR register multiplies reference clock SYNR+1 generate clock. Therefore, value written SYNR register obtain 24-MHz clock. Note that four instructions following STAB instruction work around 0K36N mask set. This errata manifested itself LOCK being cleared until several cycles after write SYNR register occurred. Also note that 24-MHz clock chosen support baud rate 115,200.
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Freescale Semiconductor, Inc. Application Note
final actions performed startup code initialize FCLKDIV register call SCIInit subroutine. value written FCLKDIV register calculated assembler based MC9S12DP256's oscillator frequency, frequency. SCIInit subroutine initializes SCI0 hardware associated data structures needed support buffered, interrupt driven communications. accepts single parameter accumulator that used initial baud rate.
Freescale Semiconductor, Inc.
Bootloader Control Loop
After startup code completed task, sign-on message displayed bootloader enters main control loop. start loop, index register loaded with address bootloader prompt subroutine PromptResp called. PromptResp subroutine used display null terminated ($00) character string then waits single character response from operator. Upon receipt character, PromptResp subroutine returns range check performed received character ensure valid command. received character valid command, entry ignored prompt redisplayed. received character three valid commands, ASCII value used index into table offsets. However, before being used offset, upper four bits ASCII value must removed. Next, must subtracted from remaining value because first entry table offset zero. result subtraction must then multiplied because each entry table consists bytes. Next LEAX instruction used conjunction with program counter relative (PCR) indexed addressing load address command table into index register position independent manner. Because accumulator contains offset proper entry command table, instruction uses accumulator offset indexed addressing retrieve entry from table. Examining command table label CmdTable, seen that table does contain absolute address command execute. Rather each table entry contains offset from beginning table start command. This offset, when added
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Application Note Bootloader Software
base address table contained index register, produces absolute address first instruction requested command. Using offsets command table conjunction with calculating beginning table position independent manner, allows computed GOTO performed position independent manner. Finally, instruction uses accumulator offset indexed addressing calculate address command calls command subroutine.
Freescale Semiconductor, Inc.
Upon return from command, value global variable ErrorFlag examined. contains value zero, command completed without errors. this case, code branches back command loop where bootloader prompt redisplayed. however, error occurred during command execution, value ErrorFlag used index into table offsets null terminated error strings. Calculation absolute address error string performed much same manner calculation absolute address command. After displaying error message, code branches back command loop where bootloader prompt redisplayed.
Program Command Code
firmware required implement FLASH programming command consists subroutines. first subroutine, ProgFlash, called through command table. This subroutine coordinates activities required ProgFBlock subroutine which performs actual programming FLASH memory. ProgFlash subroutine begins calling GetSRecord subroutine which used receive single S-record from host computer. Having received valid S-record, subroutine performs several checks ensure that S-record meets programming requirements MC9S12DP256. Because MC9S12DP256's FLASH only programmed align word time, both code/data field length load address must even numbers. either value odd, error code stored ErrorFlag global variable FLASH programming operation terminated.
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Freescale Semiconductor, Inc. Application Note
Next, received S-record type checked. Reception S-record terminates program FLASH command returning bootloader's control loop where prompt redisplayed. records, designated header records, contain program data simply ignored. Because linear S-record addresses MC9S12DP256 begin $C0000 shown Figure only S-records used program on-chip FLASH. Because GetSRecord subroutine capable receiving S-records, program FLASH command terminated error code returned ErrorFlag global variable record received. After checking received S-record type, range check performed S-record load address ensure within range on-chip FLASH minus size protected area containing bootloader. When performing range check, load address first checked against SRecLow, lowest valid S-record address on-chip FLASH. However, when checking against upper limit, SRecHi, number code/data bytes contained S-record must added load address before comparison performed. This ensures that even though initial load address less than upper limit, none S-record code/data falls outside upper limit. Finally, ProgFlash subroutine uses S-record load address calculate PPAGE number PPAGE window address using formulas Figure After initializing PPAGE register, PPAGE value used calculate value block select bits. Closely examining PPAGE values block numbers shown Figure determined that block number PPAGE values corresponds one's complement bits three block's corresponding PPAGE value. After writing proper value block select bits FCNFG register, ProgFBlock subroutine called program received S-record data into FLASH. errors occurred during programming operation, code branches label FSendPace where ASCII asterisk character sent host computer indicate that S-record data successfully programmed into FLASH.
Freescale Semiconductor, Inc.
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Application Note Bootloader Software
ProgFBlock subroutine performs task programming received S-record data into on-chip FLASH. While subroutine generally follows flowchart Figure some operations have been rearranged improve efficiency implementation. first steps flowchart, writing PPAGE register block select bits, performed ProgFlash subroutine. Note that order these operations important. Because value block select bits derived from PPAGE value, ProgFlash subroutine writes PPAGE register value first.
Freescale Semiconductor, Inc.
third operation flowchart checks state CBEIF ensure that command buffer empty ready accept command. This check made beginning ProgFBlock subroutine because known when subroutine completes execution. This condition inferred fact that CCIF flag before programmed data from previously received S-record verified. ProgFBlock subroutine begins retrieving S-record code/data field length, dividing value placing result stack. code/data field length divided because FLASH programmed word time. Next, index registers initialized point FLASH S-record data respectively. Note that index register loaded with value PPAGEAddr global variable. This value, calculated using second formula Figure will always point within PPAGE window. After initializing pointers, programming loop entered label ProgLoop. Note that within programming loop there instructions that directly correspond five cycle delay before checking state CBEIF flag after issuing program command. Instead, five cycle delay inherent three instructions (LDAB, BITB, BNE) used check state ACCERR PVIOL status bits. This loop follows remainder flowchart Figure issuing programming command each time CBEIF flag until count local variable NumWords zero. Before verifying that FLASH locations programmed properly, firmware must wait until CCIF flag set, indicating that issued programming commands have completed. Failure observe this
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Freescale Semiconductor, Inc. Application Note
constraint before performing read operation FLASH will result setting ACCERR pending programming commands will terminated. verification process begins reinitializing DataBytes local variable index register pointers. programmed words match S-record data, "not equal" condition equal returned.
Freescale Semiconductor, Inc.
Erase Command Code
code comprising FLASH erase command nearly simple programming code; consists five subroutines. reason additional complexity surrounds method that must used erase FLASH block containing protected areas. When 64-K block portion contents protected from being erased programmed, FLASH's mass erase command cannot used. Instead, unprotected areas must erased 512-byte sector time. Because time required erase sector versus mass erase operation, erasure 64-K block with protected areas requires much longer. this case where bootloader resides protected area block zero, sector erase operations must performed. counting time required verify each sector erasure, sector erase operations require seconds sectors). FLASH erase command begins with subroutine EraseFlash, called through command table. This subroutine coordinates activities other four subroutines. begins performing mass erase verify three 64-K FLASH blocks. After three 64-K FLASH blocks have been successfully erased, EraseBlk0 subroutine called perform sector sector erase unprotected portion FLASH block zero. EraseBlk0 subroutine begins allocating initializing local variable PPAGECnt. initialized value three number 16-K PPAGE windows that will completely erased sector time. PPAGE register initialized with value passed accumulator from EraseFlash subroutine. This value, $3C, places lower FLASH block zero into PPAGE window. block select bits initialized zero. After loading index register with address
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Application Note Bootloader Software
start PPAGE window accumulator with number sectors erase, EraseSectors subroutine called. addition erasing requested number sectors, VerfSector subroutine called verify erasure. Note that VerfSector subroutine verifies erasure word time because erase verify command built into FLASH state machine will only operate 64-K block. After EraseBlk0 performs erasure lower FLASH block zero, lower sectors ($8000-$EFFF) upper block zero erased.
Freescale Semiconductor, Inc.
Baud Rate Command Code
code comprising baud rate command relatively simple. subroutine begins displaying baud rate change prompt then waiting operator enter baud rate selection. range check performed entered character; invalid character entered, prompt redisplayed. selection valid, upper four bits masked off, subtracted from lower four bits, result divided two. result used index into BaudTable retrieve proper SCI0BD register value selected baud rate. Before switching newly selected baud rate, message displayed prompting operator change host terminal's baud rate. However, before SCI0BD register written with value, firmware must wait until last character message shifted from SCI0 transmit shift register. Once last character message sent, SCI0BD register written with value getchar subroutine called wait indication from operator that host terminal baud rate been changed. Finally, carriage return/line feed sent terminal before returning bootloader control loop.
S-Record Loader Code
GetSRecord subroutine used receive single S-record from host computer. GetSRecord begins allocating space stack local variables initializing index register. SRecBytes variable used hold converted value S-record length field. This value includes number bytes contained load address field, length code/data field, length
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Freescale Semiconductor, Inc. Application Note
checksum field. variable CheckSum used contain calculated checksum value S-record received. index register initialized point beginning 24-bit global variable, LoadAddr, where received S-record's address stored. Note also that most significant byte LoadAddr cleared case record received. After initializations, search begun character pairs which indicate start valid S-record. Once valid start record found, number bytes load address plus stored global variable DataBytes. This value subsequently subtracted from received S-record length byte produce result representing code/data field length. Before receiving S-record length byte, second character start record pair stored global RecType. After receiving S-record length byte, value saved local variable SRecBytes. This value also used initialize CheckSum which used calculate checksum value S-record received. loop beginning label RcvData receives remainder S-record including load address, code/data field, checksum. Note that because each received byte stored successive memory locations, global variables LoadAddr SRecData must remain order they declared. each data byte checksum received, added into calculated checksum value. Because received checksum actually one's complement what calculated checksum should adding values should produce result $FF. incrementing CheckSum variable receive loop should produce result zero checksum S-record fields were received properly. This results "equal" condition (CCR being returned S-record properly received "not equal" condition (CCR being returned problem occurred receiving S-record. Operation GetSRecord subroutine supported three additional subroutines GetHexByte, IsHex, CvtHex. GetHexByte subroutine retrieves ASCII bytes from serial port converts them into single 8-bit data byte that returned accumulator. IsHex subroutine used check received byte
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Freescale Semiconductor, Inc.
Application Note Bootloader Software
ensure that ASCII hexadecimal character. character accumulator non-hexadecimal character, subroutine returns "not equal" condition (CCR Otherwise, "equal" condition (CCR returned. CvtHex subroutine converts ASCII hexadecimal character accumulator binary value. result remains accumulator.
Freescale Semiconductor, Inc.
Serial Communications Code
serial communications routines utilize SCI0 communicate with host computer. routines utilize interrupt driven mode, allowing reception data from host computer while bootloader programming on-chip FLASH memory. prevent possibility receive buffer overflowing, receive routines support XOn/XOff handshaking with host computer. Because bootloader does send large amounts data host computer, XOn/XOff handshaking supported transmit routines. utilize interrupt driven mode effectively, circular buffer queue must associated with both transmitter receiver. queue acts elastic buffer providing software interface between received character stream MC9S12DP256. addition storage required transmit receive queues, several other pieces data required queue management. information necessary manage queue consists determine next available storage location each queue, next available location piece data queue, determine queue full empty. Rather than utilize 16-bit pointers manage queues, communications routines employ four 1-byte variables. RxIn, RxOut, TxIn, TxOut used conjunction with 8-bit accumulator offset indexed addressing access data transmit receive queues. addition, 1-byte variables, RxBAvail TxBAvail, used keep track number bytes available each queue. When value each these variables equal size queue, buffer empty. When value zero, queue full. Using byte index does allow support queue sizes greater than bytes. However, this should pose severe restrictions most applications.
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Freescale Semiconductor, Inc. Application Note
proper queue size application will depend expected length messages transmitted received. selected transmit queue size small, routines essentially will behave same polled example. Once queue fills, CPU12 will have wait until character transmitted before next character placed queue. receive queue small, there will risk that received characters will lost queue becomes full CPU12 does remove some data before next piece data arrives. Conversely, picking queue sizes larger than necessary does have detrimental effect program performance loss data. However, will consume valuable on-chip memory unnecessarily. uncertain exact queue size particular application, best make larger than necessary. shown, transmit receive queues have same size, their sizes required even power two. XOffCount XOnCount constants used manage full empty, respectively, receive queue allowed before XOff control characters sent host computer. value XOffCount should chosen based number bytes that expected sent from host after request been made TxIRQ routine send XOff host. This value, which represents number remaining bytes receive queue when XOff should sent, will depend UART characteristics host computer. this case, value XOffCount would allow additional characters sent after request send XOff been posted. This would allow host computer UART with 8-byte FIFO plus possible 2-character delay sending XOFF character transmit shift register transmit data register were both full. value XOnCount should selected such that queue will never become empty long host data send. Setting correct value this constant requires analysis rate which data removed from queue application delay before host computer begins sending data after receiving XOn. Because host's characteristics vary widely, value receive buffer minus eight arbitrarily chosen. Note that value XOnCount represents number characters available receive queue.
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Freescale Semiconductor, Inc.
Application Note Bootloader Software
Freescale Semiconductor, Inc.
SCIInit subroutine used initialize hardware related queue data structures. baud rate register (SCI0BD) value desired baud rate passed subroutine accumulator. queue index values RxIn, RxOut, TxIn, TxOut, values RxBAvail TxBAvail specifically initialized subroutine because initial values point their declaration. This technique works this case because constant values were copied from FLASH into RAM. situation where variables were declared with (define storage) directive each variable would have initialized proper value. When transmitter receiver enabled, notice that only receive interrupts enabled. Unlike receiver interrupts, which enabled times, transmit interrupt enabled only when transmit queue contains characters sent. Enabling transmit interrupts initialization would immediately cause transmitter interrupt even though transmit queue empty. This because TDRE whenever transmitter idle state. final action performed SCIInit subroutine initializes SCI0 interrupt vector point interrupt routine, SCIISR. Because each only single interrupt vector shared transmitter receiver, short dispatch routine determines source interrupt calls either RxIRQ TxIRQ. Note that arbitrary choice have dispatch routine check receiver interrupts before transmitter interrupts. avoid loss received data, interrupt dispatch routine should always check receiver control status flags before checking those associated with transmitter. Failure follow this convention will most likely result receiver overruns when data received during message transmissions longer than couple bytes. receive interrupt service routine, RxIRQ, responsibility removing received byte from receive data register placing receive data queue space available. addition, space available queue falls below value XOffCount, variables, SendXOff XOffSent, non-zero value transmitter interrupts enabled. These actions cause XOff character sent host computer next time transmit
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Freescale Semiconductor, Inc. Application Note
interrupt generated. XOffSent used receive interrupt service routine ensure that only single XOff character sent host after space available queue falls below value XOffCount. XOffSent also used getchar subroutine determine should sent after each character removed from queue. Finally, notice that queue becomes full, received byte simply discarded. transmit interrupt service routine, TxIRQ, responsibility removing byte from transmit data queue sending host computer. Before sending character from transmit queue, SendXOff checked. contains non-zero value, XOff character immediately sent host. Sending XOff character before sending data that transmit queue ensures data flow from host stopped before receive queue overflows. Notice that queue becomes empty after character transmitted, transmitter interrupts disabled. last major routines rounding serial communication code getchar putchar subroutines. getchar subroutine's main function retrieve single character from receive queue return calling routine accumulator. Notice that receive queue empty, getchar subroutine will wait until character received from host. Because this action desirable some applications, utility subroutine, SCIGetBuf, called determine data receive queue. This small subroutine returns, accumulator, count number data bytes receive queue. addition managing receive queue variables each time character removed from queue, getchar subroutine checks state XOffSent number characters left receive queue determine character should sent host computer. XOff character previously sent number characters left receive queue less than XOnCount, character sent host calling putchar routine.
Freescale Semiconductor, Inc.
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Application Note Secondary Interrupt Vector Jump Table
putchar subroutine's main function place single character, passed accumulator, into transmit queue. Once character queue queue variables have been updated, transmit interrupt enable (TIE) set. transmitter interrupts were previously enabled transmit data register empty (TDRE) set, setting will cause interrupt occur immediately.
Secondary Interrupt Vector Jump Table
Freescale Semiconductor, Inc.
Because reset interrupt vectors reside protected bootblock, secondary vector table located just below protected bootblock area. Each entry secondary interrupt table should consist 2-byte address mirroring primary interrupt reset vector table. secondary interrupt reset vector table utilized having each vector point single instruction that uses CPU12's indexed-indirect program counter relative addressing mode. This form instruction uses four bytes memory requires just clock cycles execute. table Figure associates each vector source with secondary interrupt table address.
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Freescale Semiconductor, Inc. Application Note
Interrupt Source Reserved $FF80 Reserved $FF82 Reserved $FF84 Reserved $FF86 Reserved $FF88 Reserved $FF8A emergency shutdown Port interrupt MSCAN transmit MSCAN receive MSCAN errors MSCAN wakeup MSCAN transmit MSCAN receive MSCAN errors MSCAN wakeup MSCAN transmit MSCAN receive MSCAN errors MSCAN wakeup MSCAN transmit MSCAN receive MSCAN errors MSCAN wakeup MSCAN transmit MSCAN receive MSCAN errors MSCAN wakeup FLASH EEPROM SPI2 SPI1
Secondary Vector Address $EF80 $EF82 $EF84 $EF86 $EF88 $EF8A $EF8C $EF8E $EF90 $EF92 $EF94 $EF96 $EF98 $EF9A $EF9C $EF9E $EFA0 $EFA2 $EFA4 $EFA6 $EFA8 $EFAA $EFAC $EFAE $EFB0 $EFB2 $EFB4 $EFB6 $EFB8 $EFBA $EFBC $EFBE
Interrupt Source SCME lock Pulse accumulator overflow Modulus down counter underflow Port interrupt Port interrupt ATD1 ATD0 SCII SCI0 SPI0 Pulse accumulator input edge Pulse accumulator overflow Timer overflow Timer channel Timer channel Timer channel Timer channel Timer channel Timer channel Timer channel Timer channel Real-time interrupt XIRQ Unimplemented instruction trap failure reset Clock monitor fail reset Reset
Secondary Vector Address $EFC0 $EFC2 $EFC4 $EFC6 $EFC8 $EFCA $EFCC $EFCE $EFD0 $EFD2 $EFD4 $EFD6 $EFD8 $EFDA $EFDC $EFDE $EFE0 $EFE2 $EFE4 $EFE6 $EFE8 $EFEA $EFEC $EFEE $EFF0 $EFF2 $EFF4 $EFF6 $EFF8 $EFFA $EFFC $EFFE
Freescale Semiconductor, Inc.
Figure Secondary Vector Table Addresses Bootblock
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Freescale Semiconductor, Inc.
Code Listing
AN2153
RegBase: offset: PCSave: macro endm $0000 switch: macro '.text',':0' PCSave endif endm oscillator clock frequency. final E-clock frequency (PLL). reference clock used PLL. value REFDV register. value SYNR register. OscClk: fEclock: RefClock: REFDVVal: SYNRVal: FCLKDIVVal: FCLKDIVVal: (OscClk/200000) 8000000 24000000 8000000 (OscClk/RefClock)-1 (fEclock/RefClock)-1 OscClk>12800000 (OscClk/200000/8)+FDIV8 value FCLKDIV register. value FCLKDIV register. else endif 16384 $c0000 $ff000 $8000 4096 $1000 $ff80 $3000 fEclock/16/115200 fEclock/16/57600 fEclock/16/38400 fEclock/16/9600 baud baud baud baud register register register register value value value value 115,200 baud. 57,600 baud. 38,400 baud. 9,600 baud. Baud115200: Baud57600: Baud38400: Baud9600: FlashStart: BootBlkSize: RAMStart: StackTop: RAMBoot: start address flash window. Erase protected bootblock size. default base address. stack location after moved. starting address where bootloader will copied. size Flash Sector. size PPAGE window ($8000 $BFFF). SectorSize: PPAGESize: SRecLow: SRecHi: lowest S-Record load address accepted bootloader. highest S-Record load address accepted bootloader.
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00000000
007A1200 016E3600 007A1200 00000000 00000002 00000000
00000028
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0000000D 0000001A 00000027 0000009C
00008000 00001000 00001000 0000FF80 00003000
00000200 00004000
000C0000
Application Note Code Listing
000FF000
Freescale Semiconductor, Inc.
Application Note
S0RecType: S1RecType: S2RecType: S8RecType: S9RecType: FEraseError: SRecRngErr: FlashPrgErr: SRecDataErr: Flash failed erase. S-Record range. Flash programming error. Received S-Record contained number data bytes. S-Record Address odd. S-Record long.
00000030 00000031 00000032 00000038 00000039
00000001 00000002 00000003 00000004
00000005 00000006
0000F000
0000F000 0000F005
0000F009
0000F00C 0000F00F 0000F012 0000F015 0000F018 0000F01B 0000F01F
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0000F022
00000000
0000F024
0000F027 0000F029 0000F02B 0000F02D 0000F02F 0000F030 0000F031
SRecAddrErr: SRecLenErr: $f000 1F02514004 BootStart: brclr PTIM,#$40,Boot execute bootloader? 05FBFFF5 [Reset-BootBlkSize,pcr] jump program pointed secondary reset vector. 79003C Boot: COPCTL keep watchdog disabled. CFFF80 BootCopy: #StackTop initialize stack pointer CEF000 #BootStart point start Flash bootloader Flash. CD3000 #RAMBoot point start on-chip RAM. CCF59A #BootLoadEnd calculate size bootloader code. 83F000 subd #BootStart 180A3070 MoveMore: movb 1,x+,1,y+ move byte bootloader into RAM. 0434F9 dbne d,MoveMore byte count, move till done. C6C1 ldab #$c0+RAMHAL write INITRM register overlay Flash bootblock with RAM. *&$0001<>0 currently byte boundary? endif 7B0010 stab >INITRM this instruction MUST extended addressing aligned even byte boundary. C600 ldab #REFDVVal REFDV register. 5B35 stab REFDV C602 ldab #SYNRVal SYNR register. 5B34 stab SYNR nops required initial silicon.
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Freescale Semiconductor, Inc.
brclr bset CRGFLG,#LOCK,* CLKSEL,#PLLSEL #FCLKDIVVal FCLKDIV #Baud9600 SCIInit,pcr 9600 baud. initialize SCI. value Flash clock divider register. wait here till locked. switch clock PLL. ldab stab
AN2153
CmdLoop: SignOn,pcr OutStr,pcr ErrorFlag,pcr BLPrompt,pcr PromptResp #$61 CmdLoop #$63 CmdLoop #$0f leax leax cmpb cmpb andb decb lslb leax ldab decb lslb leax leax CmdTable,pcr ErrorFlag,pcr CmdLoop ErrorTable,pcr OutStr,pcr CmdLoop bootloader signon message send terminal. clear global error flag. bootloader prompt display prompt character response. range check. less than 'a'? yes. just re-display prompt. greater than 'c'? yes. just re-display prompt. mask upper nybble. reduce indexing into command offset table. mult each table entry byte address. point command table. offset from beginning table cmd. execute command. error executing command? display prompt, wait entered command. subtract from error number indexing. mult because each address table bytes. yes. point error table. offset from start table string. calc address error string from table. send error message terminal. display prompt.
0000F032 0000F033 4F3708FC 0000F037 4C3980
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0000F03A C628 0000F03C 7B0100
0000F03F CC009C 0000F042 15FA046F 0000F046 10EF
0000F048 0000F04C 0000F050 0000F054 0000F058 0000F05A 0000F05C 0000F05E 0000F060 0000F062 0000F064 0000F065 0000F066 0000F06A 0000F06C 0000F06E 0000F072 0000F074 0000F075 0000F076 0000F07A 0000F07C 0000F07E 0000F082
1AFA0055 15FA0422 69FA0546 1AFA0064 072A C161 25F2 C163 22EE C40F 1AFA0031 ECE5 15E6 E6FA0528 27DC 1AFA00CC ECE5 1AE6 15FA03F0 20CC
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0000F084 0000F088 0000F08C 0000F090 0000F091 0000F095 0000F099 0000F09A
15FA03EA 15FA04B8 15FA04E9 1AFA0060 15FA03D9
PromptResp: OutStr,pcr send prompt terminal. getchar,pcr user's choice. putchar,pcr echo pshb save leax CrLfStr,pcr next line. OutStr,pcr pulb restore entered character.
Application Note Code Listing
Freescale Semiconductor, Inc.
Application Note
CmdTable: dc.w dc.w dc.w EraseFlash-CmdTable ProgFlash-CmdTable SetBaud-CmdTable table entry 'Erase Flash' command. table entry 'Program Flash' command. table entry 'Set Baud Rate' command.
0000F09B 0288 0000F09D 01A7 0000F09F 0169
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0000F0A1 0D0A4D433953 SignOn: dc.b $0d,$0a,"MC9S12DP256 Bootloader",$0d,$0a,0 0000F0BC 0D0A61292045 BLPrompt: dc.b $0d,$0a,"a) Erase Flash",$0d,$0a 0000F0CE 62292050726F dc.b Program Flash",$0d,$0a 0000F0E0 632920536574 dc.b Baud Rate",$0d,$0a 0000F0F2 3F2000 dc.b 0000F0F5 0D0A00 CrLfStr: dc.b $0d,$0a,0 0000F0F8 0D0A31292039 BaudPrompt: dc.b $0d,$0a,"1) 9600",$0d,$0a 0000F103 322920333834 dc.b 38400",$0d,$0a 0000F10D 332920353736 dc.b 57600",$0d,$0a 0000F117 342920313135 dc.b 115200",$0d,$0a 0000F122 3F2000 dc.b 0000F125 4368616E6765 BaudChgPrompt: dc.b "Change Terminal Press Return",0 0000F146 000C ErrorTable: dc.w FNotErasedStr-ErrorTable 0000F148 0021 dc.w SRecRngStr-ErrorTable 0000F14A 003B dc.w FlashPrgErrStr-ErrorTable 0000F14C 0057 dc.w SRecDataErrStr-ErrorTable 0000F14E 007C dc.w SRecAddrErrStr-ErrorTable 0000F150 0098 dc.w SRecLenErrStr-ErrorTable 0000F152 0D0A466C6173 FNotErasedStr: dc.b $0d,$0a,"Flash Erased",$0d,$0a,0 0000F167 0D0A532D5265 SRecRngStr: dc.b $0d,$0a,"S-Record Range",$0d,$0a,0 0000F181 0D0A466C6173 FlashPrgErrStr: dc.b $0d,$0a,"Flash Programming Error",$0d,$0a,0 0000F19D 0D0A532D5265 SRecDataErrStr: dc.b $0d,$0a,"S-Record code/data length odd",$0d,$0a,0 0000F1C2 0D0A532D5265 SRecAddrErrStr: dc.b $0d,$0a,"S-Record Address odd",$0d,$0a,0 0000F1DE 0D0A532D5265 SRecLenErrStr: dc.b $0d,$0a,"S-Record Code/Data Field Long",$0d,$0a,0 0000F204 SetBaud: 0000F204 1AFAFEF0 leax BaudPrompt,pcr baud rate change prompt 0000F208 15FAFE78 PromptResp,pcr display prompt character response. 0000F20C C131 cmpb #$31 range check. less than '1'? 0000F20E 25F4 SetBaud yes. just re-display prompt. 0000F210 C134 cmpb #$34 greater than '4'? 0000F212 22F0 SetBaud yes. just re-display prompt. 0000F214 C40F andb #$0f mask upper nybble. 0000F216 decb subtract table indexing. 0000F217 lslb multiply because each table entry bytes. 0000F218 1AFA001E leax BaudTable,pcr point start table. 0000F21C ECE5 SCI0BD value from table. 0000F21E pshd save value.
AN2153
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Freescale Semiconductor, Inc.
leax brclr BaudChgPrompt,pcr OutStr,pcr SCI0SR1,#TC,* return. Baud9600 Baud38400 Baud57600 Baud115200 SCI0BD SCI0BD SCI0BD SCI0BD value value value value 9600 baud. 38400 baud. 57600 baud. 115200 baud. prompt user change terminal baud rate. send terminal. wait until last character sent until change baud rate. restore SCI0BD value from stack. change baud rate. wait user change baud rate. next line.
AN2153
puld leax SCI0BD getchar,pcr CrLfStr,pcr OutStr,pcr BaudTable: dc.w dc.w dc.w dc.w
MOTOROLA
0000F21F 1AF903 0000F222 15FA024C 0000F226 4FCC40FC
0000F22A 0000F22B 0000F22D 0000F231 0000F235 0000F239
5CC8 15FA0313 1AFAFEC0 15FA0239
0000F23A 0000F23C 0000F23E 0000F240
009C 0027 001A 000D
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0000F242 0000F242 0000F244 0000F247 0000F249 0000F24B 0000F24F 0000F253 0000F255 0000F25B 0000F25D 0000F25F 0000F265 0000F267
0000F269 0000F26D 0000F26F 0000F271
0000F273
0000F275 0000F277 0000F279 0000F27B 0000F27D 0000F27F
Application Note Code Listing
0000F281 0000F285 0000F287
ProgFlash: C630 ldab #PVIOL+ACCERR either PVIOL ACCERR from 7B0105 stab FSTAT previous error, reset them program Flash. 2006 FSkipFirst don't send progress character first time. C62A FSendPace: ldab #'*' ascii asterisk progress character. 15FA032A putchar,pcr user know we've processed S-Record. 15FA0174 FSkipFirst: GetSRecord,pcr S-Record. 267D ProgDone non-zero condition means there error 0FFA03410104 brclr DataBytes,pcr,#$01,DataLOK received S-Record length even? 8604 ldaa #SRecDataErr report error. 2073 ProgDone stop programming. 0FFA033C0104 DataLOK: brclr LoadAddr+2,pcr,#$01,SRecOK received S-Record address even? 8605 ldaa #SRecAddrErr report error. 2069 ProgDone stop programming. E6FA032E SRecOK: ldab RecType,pcr check record type. C131 cmpb #S1RecType record received? 2604 ChckNext check records. 8602 ldaa #SRecRngErr yes. only records load addresses $C0000 $FEFFF allowed. 205D ProgDone save error return. C139 ChckNext: cmpb #S9RecType record? 275D ProgRtn yes. we're done. C138 cmpb #S8RecType record? 2759 ProgRtn yes. we're done. C130 cmpb #S0RecType record? 27C8 FSendPace yes. just ignore E6FA031A ldab LoadAddr,pcr record. high byte 24-bit address. C10C cmpb #SRecLow>>16 less than $c0000? 2404 ChkHiLimit check upper limit.
Freescale Semiconductor, Inc.
BadSRecRng: ChkHiLimit: ldab clra addd ldab adcb cmpb LoadAddr+1,pcr LoadAddr,pcr #$00 #SRecHi>>16 AddrOK #SRecHi&$ffff BadSRecRng LoadAddr,pcr LoadAddr+1,pcr #PPAGESize #FlashStart PPAGE upper 8-bits 24-bit load address. zero extend into 32-bit divide lower 16-bits 24-bit load address. divide load address PPAGE window size. ldab ediv addd DataBytes,pcr number bytes S-Record. zero extend lower 16-bits 24-bit address. save rthe result upper 8-bits 24-bit address. possible carry from lower 16-bits. greater than $0fxxxx? S-Record within range. yes. check lower bits. range? yes. S-Record range.
Application Note
ldaa #SRecRngErr ProgDone yes. S-Record range. save error code return. AddrOK: PPAGE window start address remainder (this gives PPAGE window load address). lower byte quotent PPAGE value. calculate value block select bits based bits PPAGE register value. #$03 FCNFG PPAGEWAddr,pcr ProgFBlock,pcr FSendPace #FlashPrgErr ErrorFlag,pcr mask lower bits. select block erase. save PPAGE window address. program data into Flash. zero condition means went stab lsrb lsrb comb andb stab lbeq ldaa staa
0000F289 8602 0000F28B 2045
0000F28D 0000F291 0000F292 0000F296 0000F298 0000F29C 0000F29E 0000F2A0 0000F2A2 0000F2A5
E6FA030B E3FA030A B745 E6FA0303 C900 C10F 2505 8EF000 22E2
0000F2A7 0000F2AB 0000F2AD 0000F2B1 0000F2B4 0000F2B5
E6FA02F4 B796 ECFA02EF CE4000 C38000
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0000F2B8 0000F2BA 0000F2BC 0000F2BD 0000F2BE 0000F2BF 0000F2C1 0000F2C4 0000F2C8 0000F2CC 0000F2D0 0000F2D2 0000F2D6
B7C6 5B30 C403 7B0103 6DFA02D5 15FA000B 1827FF79 8603 6AFA02C4
0000F2D7 0000F2D7 00000000
00000000 00000001
00000001 00000001 0000F2D7
AN2153
MOTOROLA
0000F2D7
ProgDone: error code where access ProgRtn: fall through, automatically return non-zero condition. offset PCSave: NumWords: LocalSize: switch .text '.text','.text' PCSave endif E6FA02C1 ProgFBlock: ldab DataBytes,pcr block size.
Freescale Semiconductor, Inc.
lsrb
AN2153
ProgLoop: pshb leay PPAGEWAddr,pcr SRecData,pcr 2,y+ 2,x+ #PROG FCMD #CBEIF FSTAT FSTAT #PVIOL+ACCERR Return FSTAT,#CBEIF,* NumWords,sp ProgLoop FSTAT,#CCIF,* DataBytes,pcr ldab stab ldab stab ldab bitb brclr brclr ldab lsrb block size. divide byte count since verify word time. divide byte count since program word time. allocate local. PPAGE window Flash address. point received S-Record data. word from buffer. latch address data into Flash program/erase buffers. program command. write command register. start command writing CBEIF. check there problem executing command. either PVIOL ACCERR set, return. wait here till command buffer empty. more words program? yes. continue until done. wait until commands complete. VerfLoop: stab leay pulb NumWords,sp PPAGEWAddr,pcr SRecData,pcr 2,y+ 2,x+ Return NumWords,sp VerfLoop PPAGE window Flash address. point received S-Record data. word from buffer. same word Flash? return error condition). yes. done comparing words? compare some more. deallocate local. return. Return:
MOTOROLA
0000F2DB
0000F2DC 0000F2DD 0000F2E1 0000F2E5 0000F2E7
EEFA02BC 19FA02BD EC71 6C31
0000F2E9 0000F2EB 0000F2EE 0000F2F0 0000F2F3
C620 7B0106 C680 7B0105 F60105
0000F2F6 0000F2F8 0000F2FA 0000F2FF 0000F301 0000F303
C530 2627 1F010580FB 6380 26E2 1F010540FB
0000F308 E6FA0290 0000F30C
0000F30D 0000F30F 0000F313 0000F317 0000F319 0000F31B 0000F31D 0000F31F
6B80 EEFA028A 19FA028B EC71 AC31 2604 6380 26F6
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0000F321 0000F322
0000F323 0000F323 00000000
00000000
00000001
Application Note Code Listing
00000001 00000001 0000F323
offset PCSave: BlockCnt: ds.b number blocks erase. LocalSize: switch .text '.text','.text' PCSave
Freescale Semiconductor, Inc.
endif EraseFlash: #$03
Application Note
EraseLoop: ldab pshb ldab stab #$30 PPAGE Z=0, error occurred. perform erase verify. wait until command completed. flag erased error BLANK set. mask lower bits. select block erase. latch address erase command perform bulk erase. write PPAGE register allow writes proper Flash block. calculate value block select bits based bits PPAGE register. VerfCmdOK: Erased: lsrb lsrb comb andb stab ldab ldab brclr brset ldaa ldab stab ldab addb #$03 FCNFG #FlashStart #ERASE+MASS EraseCmd SaveError #ERVER+MASS EraseCmd FSTAT,#CCIF,* FSTAT,#BLANK,Erased #FEraseError SaveError #BLANK FSTAT PPAGE #$04 BlockCnt,sp EraseLoop EraseBlk0 clear BLANK status bit. ErrorFlag,pcr return. block sector (512 bytes) time because bootblock protected. number PPAGE windows that will completely erased. staa pulb current PPAGE value. select next Flash block. done with blocks? block must erased seperately because contains bootblock. error code where access SaveError: FEEDone: ;EraseBlk0 erases Flash offset PCSave: PPAGECnt: ds.b LocalSize: switch endif .text '.text','.text' PCSave
0000F323 0000F325 0000F326 0000F328
C603 C630 5B30
0000F32A 0000F32B 0000F32C 0000F32D 0000F32F 0000F332 0000F335 0000F337 0000F339 0000F33B 0000F33D 0000F33F 0000F344 0000F349 0000F34B 0000F34D 0000F34F 0000F352 0000F354 0000F356 0000F358 0000F35A
C403 7B0103 CE8000 C641 0760 2621 C605 075A 1F010540FB 1E01050404 8601 200F C604 7B0105 D630 CB04 6380 26CE 0706
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0000F35C 6AFA023A 0000F360 0000F361
0000F362 0000F362 00000000
00000000
00000001
MOTOROLA
00000001 00000001 0000F362
AN2153
Freescale Semiconductor, Inc.
EraseBlk0: movb stab #3,1,-sp PPAGE
AN2153
EraseBlk0Loop: ldab ldab BadBlk0: pulb PPAGE windows will completely erased. PPAGE first page block (passed accumulator). FCNFG block select bits #FlashStart point start PPAGE window. #PPAGESize/SectorSize number sectors PPAGE window. EraseSectors erase PPAGE window sector time. BadBlk0 non-zero value returned indiciates sector didn't erase. PPAGE next PPAGE. PPAGECnt,sp done with full PPAGE blocks? EraseBlk0Loop erase more blocks. #FlashStart yes. point start PPAGE window. number sectors PPAGE minus bootblock. EraseSectors erase sectors outside bootblock. remove page count from stack. ;Erases (accumulator) sectors beginning address (index register) EraseSectors: sector count EraseSectLoop: ldab #ERASE perform sector erase. EraseCmd DoEraseVerf problem with erase command, verify. Rtn: problem, return with error code DoEraseVerf: VerfSector problem, return with error code leax SectorSize,x point next sector. dbne y,EraseSectLoop continue erase remaining sectors. done. return. ;Erases block sector Flash EraseCmd: latch address erase command. stab FCMD ldab #CBEIF stab FSTAT initiate erase command. brclr FSTAT,#PVIOL+ACCERR,EraseCmdOK continue privliage violation Access error flags clear. ldaa #FEraseError EraseCmdOK: brclr FSTAT,#CCIF,* wait until command completed. clra ;Verify that sector properly erased ;Must verify word time because built verify command only works block (64K)
MOTOROLA
0000F362 1808AF03 0000F366 5B30
0000F368 0000F36B 0000F36E 0000F370 0000F372
790103 CE8000 C620 0712 260E
0000F374 0000F377 0000F379 0000F37B 0000F37E
720030 6380 26F0 CE8000 C618
0000F380 0702 0000F382 0000F383
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0000F384 0000F386 0000F388 0000F38A 0000F38C 0000F38D 0000F38F 0000F391 0000F395 0000F398
B796 C640 070F 2701 0723 26FB 1AE20200 0436EE
0000F399 0000F39B 0000F39E 0000F3A0 0000F3A3
6C00 7B0106 C680 7B0105 1F01053003
0000F3A8 0000F3AA 0000F3AB 0000F3B0 0000F3B1
8601 1F010540FB
Application Note Code Listing
Freescale Semiconductor, Inc.
VerfSector:
Application Note
VerfSectLoop: save base address sector. save sector count. we'll check bytes time. byte from sector. WordOK: SectRtn: restore sector count. restore base address sector. return. pshx pshy ibeq ldaa dbne clra puly pulx #SectorSize/2 2,x+ d,WordOK #FEraseError SectRtn y,VerfSectLoop yes. sector word count.
0000F3B2 0000F3B3 0000F3B4 0000F3B7 0000F3B9 0000F3BC 0000F3BE 0000F3C0 0000F3C3 0000F3C4 0000F3C5 0000F3C6
CD0100 EC31 048404 8601 2004 0436F4
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0000F3C7 offset 0000F3C7 PCSave: 00000000 00000000 SRecBytes: ds.b number bytes address, data checksum fields. 00000001 CheckSum: ds.b used calculated checksum. 00000002 LocalSize: 00000002 switch .text 00000001 '.text','.text' 0000F3C7 PCSave endif 0000F3C7 GetSRecord: 0000F3C7 1B9E leas -LocalSize,sp allocate stack space variables. 0000F3C9 1AFA01D2 leax LoadAddr,pcr point code/data buffer. 0000F3CD 6900 clear upper byte address case receive 16-bit address). 0000F3CF 15FA0171 LookForSOR: getchar,pcr character from receiver. 0000F3D3 C153 cmpb #'S' start-of-record character? 0000F3D5 26F8 LookForSOR back another character. 0000F3D7 15FA0169 getchar,pcr yes. found start-of-record character (ASCII 'S') 0000F3DB C130 cmpb #S0RecType found (header) record? 0000F3DD 2602 CheckForS9 check record. 0000F3DF 200A Addr16 yes. receive record. (16-bit load address) 0000F3E1 C139 CheckForS9: cmpb #S9RecType found (end) record? (16-bit load address) 0000F3E3 2602 ChkForS1 check record. 0000F3E5 2004 Addr16 receive record. 0000F3E7 C131 ChkForS1: cmpb #S1RecType found record? (16-bit load address) 0000F3E9 2609 ChkForS2 false start-of-record character received. check another. 0000F3EB Addr16: adjust storage pointer compensate
AN2153
MOTOROLA
Freescale Semiconductor, Inc.
ldaa staa receive record. record? (24-bit load address) receive record. ChkForS2: cmpb #S2RecType ChkForS8 Addr24 DataBytes,pcr SaveRecType byte load address. address bytes plus checksum.
AN2153
ChkForS8: Addr24: SaveRecType: RcvSRec: stab stab subb DataBytes,pcr CheckSum,sp GetHexByte,pcr BadSRec SRecBytes,sp yes. save record type. cmpb ldaa staa stab #S8RecType LookForSOR DataBytes,pcr RecType,pcr record? (24-bit transfer address) look next Start Record. address bytes plus checksum. RcvData: S-Record length byte. return there error. save total number S-Record bytes receive. initialize checksum calculation with data byte count subtract load address checksum field length from data field count. save code/data field size. code/data field yes. received. code/data field limited bytes. return with error code S-Record data byte. return there error. save byte data buffer. byte into checksum. save result. received S-Record bytes? some more. checksum result will zero. BadSRec: stab cmpb ldaa stab addb stab leas DataBytes,pcr RcvData #SRecLenErr BadSRec GetHexByte,pcr BadSRec 1,x+ CheckSum,sp CheckSum,sp SRecBytes,sp RcvData CheckSum,sp LocalSize,sp
MOTOROLA
0000F3EC 8603 0000F3EE 6AFA01AA 0000F3F2 2010
0000F3F4 C132 0000F3F6 2602 0000F3F8 2004
0000F3FA 0000F3FC 0000F3FE 0000F400 0000F404
C138 26D1 8604 6AFA0198 6BFA0193
0000F408 15FA003E 0000F40C 2626 0000F40E 6B80
0000F410 6B81
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0000F412 E0FA0186
0000F416 0000F41A 0000F41C 0000F41E 0000F420 0000F422 0000F426 0000F428 0000F42A 0000F42C 0000F42E 0000F430 0000F432 0000F434 0000F436
6BFA0182 C140 2304 8606 2012 15FA0024 260C 6B30 EB81 6B81 6380 26F0 6281 1B82
0000F437 0000F437 C130 0000F439 250E
Application Note Code Listing
0000F43B 0000F43D 0000F43F 0000F441
C139 2308 C141 2506
IsHex: cmpb #'0' less than ascii zero? NotHex yes. character hex. return non-zero indication. cmpb #'9' less than equal ascii nine? IsHex1 yes. character hex. return zero indication. cmpb #'A' less than ascii 'A'? NotHex yes. character hex. return non-zero indication.
Freescale Semiconductor, Inc.
cmpb #'F' NotHex less than equal ascii 'F'? yes. character hex. return non-zero indication. return zero indication.
Application Note
0000F443 C146 0000F445 2202
0000F447 1404 0000F449
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IsHex1: orcc #$04 NotHex: 0000F44A GetHexByte: 0000F44A 15FA00F6 getchar,pcr upper nybble from SCI. 0000F44E 07E7 IsHex valid character? 0000F450 2701 yes. convert binary. 0000F452 return with non-zero indication. 0000F453 0714 OK1: CvtHex convert ascii-hex character binary. 0000F455 8610 ldaa shift upper 4-bits. 0000F457 0000F458 pshb save stack. 0000F459 15FA00E7 getchar,pcr lower nybble from SCI. 0000F45D 07D8 IsHex valid character? 0000F45F 2702 yes. convert binary. 0000F461 pulb remove saved upper byte from stack. 0000F462 return with non-zero indication. 0000F463 0704 OK2: CvtHex convert ascii-hex character binary. 0000F465 EBB0 addb 1,sp+ upper nybble. 0000F467 clra simple bit. 0000F468 return. 0000F469 C030 CvtHex: subb #'0' subtract ascii from character. 0000F46B C109 cmpb #$09 decimal digit? 0000F46D 2302 CvtHexRtn yes. 0000F46F C007 subb #$07 ascii letter ('A' 'F'). 0000F471 CvtHexRtn: 0000F472 OutStr: send null terminated string display. 0000F472 E630 ldab 1,x+ character, advance pointer, null? 0000F474 2706 OutStrDone yes. return. 0000F476 15FA00FF putchar,pcr send SCI. 0000F47A 20F6 OutStr next character. 0000F47C OutStrDone: 00000020 RxBufSize: receive queue size. 00000010 TxBufSize: transmit queue size.
AN2153
MOTOROLA
Freescale Semiconductor, Inc.
XOnCount: XOffCount: RxBufSize-8
00000018
AN2153
ASCII ASCII receive queue. transmit queue. next available location queue. next character removed from queue. next available location queue next character sent from queue. number bytes left queue. number bytes left queue. XOff been sent. request send XOff host number bytes avail. queue before sent. number bytes remaining queue when XOff sent. dc.b dc.b dc.b dc.b dc.b dc.b dc.b dc.b RxBufSize,0 TxBufSize,0 RxBufSize TxBufSize
MOTOROLA
0000000A
00000011 00000013
XOn: XOff: 0000F47D 000000000000 RxBuff: 0000F49D 000000000000 TxBuff: 0000F4AD RxIn: 0000F4AE RxOut: 0000F4AF TxIn: 0000F4B0 TxOut: 0000F4B1 RxBAvail: 0000F4B2 TxBAvail: 0000F4B3 XOffSent: 0000F4B4 SendXOff:
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0000F4B5 0000F4B7 0000F4B9 0000F4BB 0000F4BF 0000F4C2
5CC8 C62C 5BCB 1AFA0004 7EFFD6
0000F4C3 0000F4C7 0000F4CB 0000F4CF 0000F4D3
4FCB2004 4ECC2009 4FCB8004 4ECC8035
0000F4D4 0000F4D7 0000F4D9 0000F4DC
E7F9DC 2610 A6F9D5 810A
Application Note Code Listing
0000F4DE 0000F4E0 0000F4E3 0000F4E6
2209 72F4B4 4CCB80 62F9CA
SCIInit: SCI0BD initialize baud rate register. ldab #TE+RE+RIE mask interrupt. stab SCI0CR2 enable interrupts. leax SCIISR,pcr setup SCI0 interrupt vector point SCI0 bootloader's interrupt service routine. done. SCIISR: brclr SCI0CR2,#RIE,ChkRxInts interrupts enabled? brset SCI0SR1,#RDRF,RxIRQ yes. RDRF flag set, service interrupt. ChkRxInts: brclr SCI0CR2,#TIE,NoSCIInt interrupts enabled? brset SCI0SR1,#TDRE,TxIRQ Yes. TDRE set, service interrupt NoSCIInt: return action. RxIRQ: XOffSent,pcr XOff previously sent host? AlreadySent yes. place received char queue. ldaa RxBAvail,pcr number bytes available queue. cmpa #XOffCount more than enough space receive FIFO full data from host? AlreadySent yes. place received byte queue. SendXOff flag that XOff will sent ISR. bset SCI0CR2,#TIE enable transmitter interrupts. XOffSent,pcr 'XOff Sent' flag
Freescale Semiconductor, Inc.
AlreadySent: RxBAvail,pcr Buffull RxBAvail,pcr RxBuff,pcr RxIn,pcr SCI0DRL #RxBufSize NoRxWrap RxIn,pcr
Application Note
NoRxWrap: Buffull: ldab SCI0DRL leax ldaa ldab stab inca cmpa clra staa queue full. character throw away. return. room left queue? just throw character away. yes. there'll less now. point physical start queue. index next available queue location. received character. place queue. next available queue location. wrap around start queue? just update index. yes. start begining queue. update next available queue location index. return from interrupt.
0000F4E9 0000F4EC 0000F4EE 0000F4F1 0000F4F4 0000F4F7 0000F4F9 0000F4FB 0000F4FC 0000F4FE 0000F500 0000F501 0000F504
E7F9C5 2717 63F9C0 1AF989 A6F9B6 D6CF 6BE4 8120 2501 6AF9A9
0000F505 D6CF 0000F507
0000F508 0000F50B 0000F50D 0000F510 0000F512 0000F514 0000F517 0000F519
F7F4B4 2712 69F9A4 C613 5BCF E6F99B C110 2622
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0000F51B 4DCB80 0000F51E
0000F51F 0000F522 0000F525 0000F527 0000F529 0000F52A 0000F52C 0000F52E 0000F52F 0000F532 0000F535 0000F538 0000F53A 0000F53D
1AF97B A6F98B E6E4 5BCF 8110 2501 6AF97E 62F97D A1F977 2603 4DCB80
AN2153
MOTOROLA
0000F53E C620 0000F540 E0F96E
TxIRQ: SendXOff request send XOff. NoSendXOff send character from queue. SendXOff,pcr yes. clear request flag. ldab #XOff XOff character. stab SCI0DRL send ldab TxBAvail,pcr other characters queue? cmpb #TxBufSize TxRTI yes. just return next interrupt send character. bclr SCI0CR2,#TIE disable interrupts. return. NoSendXOff: leax TxBuff,pcr point physical start queue. ldaa TxOut,pcr index next character send. ldab data. stab SCI0DRL send inca advance next character send. cmpa #TxBufSize reached queue? NoTxWrap clra yes. wrap start. NoTxWrap: staa TxOut,pcr update queue index. TxBAvail,pcr more byte available queue. cmpa TxIn,pcr TxIn TxOut? TxRTI more characters send. bclr SCI0CR2,#TIE yes. queue empty turn TDRE interrupts. TxRTI: return. SCIGetBuf: ldab #RxBufSize there characters queue? subb RxBAvail,pcr
Freescale Semiconductor, Inc.
AN2153
MOTOROLA
0000F543
0000F544 0000F545 0000F546 0000F548 0000F54B 0000F54D 0000F550
C620 E0F966 27F9 1AF92D A6F95B
0000F553 0000F555 0000F556 0000F558 0000F55A 0000F55B 0000F55E
E6E4 8120 2501 6AF950 62F950
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0000F561 0000F564 0000F566 0000F569 0000F56B 0000F56D 0000F56E 0000F570 0000F572 0000F575 0000F576 0000F577 0000F578
E7F94F 2710 A6F948 8118 2409 C611 0707 69F93E
0000F579 0000F57A 0000F57B 0000F57E 0000F580 0000F583 0000F586 0000F588 0000F589 0000F58B 0000F58D 0000F58E 0000F591 0000F594
E7F934 27FB 1AF91A A6F929 6BE4 8110 2501 6AF91E 63F91E 4CCB80
return number available. getchar: pshx save registers we'll use. psha RxChk: ldab #RxBufSize characters available? subb RxBAvail,pcr RxChk just wait until some are. leax RxBuff,pcr point physical start queue. ldaa RxOut,pcr index next available character queue. ldab character. inca point next location queue. cmpa #RxBufSize reached queue? NogcWrap clra yes. wrap start. NogcWrap: staa RxOut,pcr update queue index. RxBAvail,pcr removed character from queue, there's more available. XOffSent,pcr XOff character previously sent ISR? gcReturn just return. ldaa RxBAvail,pcr yes. number bytes available queue. cmpa #XOnCount enough space available receive more? gcReturn just return. pshb yes. save character retrieved from queue. ldab #XOn send character host. putchar XOffSent,pcr clear XOff flag. pulb restore character retrieved from queue. gcReturn: pula restore what saved. pulx return. putchar: pshx save registers we'll use. psha TxChk: TxBAvail,pcr room left queue? TxChk just wait here till leax TxBuff,pcr point physical start queue. ldaa TxIn,pcr index next available spot. stab character inca point next available spot. cmpa #TxBufSize past queue? NopcWrap clra yes. wrap around start. NopcWrap: staa TxIn,pcr update queue index TxBAvail,pcr less byte available queue. bset SCI0CR2,#TIE enable transmitter interrupts.
Application Note Code Listing
Freescale Semiconductor, Inc.
pula pulx return restore what saved.
Application Note
BootLoadEnd: ;Global Variable declarations ErrorFlag: ds.b RecType: ds.b DataBytes: PPAGEWAddr: LoadAddr: SRecData: ds.b ds.b ds.b ds.b error code stored various routines. received record type. number data bytes S-Record. PPAGE window address ($8000 $BFFF) load address S-Record. S-Record data storage. (handle 64-byte S-Records received checksum)
0000F597 0000F598 0000F599
0000F59A
0000F59A 0000F59B
0000F59C 0000F59D 0000F59F 0000F5A2
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0000F5E3 0000F5E7 0000F5EB 0000F5EF 0000F5F3 0000F5F7 0000F5FB 0000F5FF 0000F603 0000F607 0000F60B 0000F60F 0000F613 0000F617 0000F61B 0000F61F 0000F623 0000F627 0000F62B
05FBF9A5 05FBF9A3 05FBF9A1 05FBF99F 05FBF99D 05FBF99B 05FBF999 05FBF997 05FBF995 05FBF993 05FBF991 05FBF98F 05FBF98D 05FBF98B 05FBF989 05FBF987 05FBF985 05FBF983 05FBF981
This jump table that used access secondary interrupt vector table. Each actual interrupt vectors, begining $ff8c, points entry this table. Each instruction uses indexed indirect program counter relative (pcr) addressing access secondary interrupt vector table that located just below bootblock. JPWMEShutdown: [PWMEShutdown-BootBlkSize,pcr] JPortPInt: [PortPInt-BootBlkSize,pcr] JMSCAN4Tx: [MSCAN4Tx-BootBlkSize,pcr] JMSCAN4Rx: [MSCAN4Rx-BootBlkSize,pcr] JMSCAN4Errs: [MSCAN4Errs-BootBlkSize,pcr] JMSCAN4WakeUp: [MSCAN4WakeUp-BootBlkSize,pcr] JMSCAN3Tx: [MSCAN3Tx-BootBlkSize,pcr] JMSCAN3Rx: [MSCAN3Rx-BootBlkSize,pcr] JMSCAN3Errs: [MSCAN3Errs-BootBlkSize,pcr] JMSCAN3WakeUp: [MSCAN3WakeUp-BootBlkSize,pcr] JMSCAN2Tx: [MSCAN2Tx-BootBlkSize,pcr] JMSCAN2Rx: [MSCAN2Rx-BootBlkSize,pcr] JMSCAN2Errs: [MSCAN2Errs-BootBlkSize,pcr] JMSCAN2WakeUp: [MSCAN2WakeUp-BootBlkSize,pcr] JMSCAN1Tx: [MSCAN1Tx-BootBlkSize,pcr] JMSCAN1Rx: [MSCAN1Rx-BootBlkSize,pcr] JMSCAN1Errs: [MSCAN1Errs-BootBlkSize,pcr] JMSCAN1WakeUp: [MSCAN1WakeUp-BootBlkSize,pcr] JMSCAN0Tx: [MSCAN0Tx-BootBlkSize,pcr]
AN2153
MOTOROLA
Freescale Semiconductor, Inc.
AN2153
JMSCAN0Rx: JMSCAN0Errs: JMSCAN0WakeUp: JFlash: JEEPROM: JSPI2: JSPI1: JIICBus: JDLC: JSCME: JCRGLock: JPACCBOv: JModDnCtr: JPortHInt: JPortJInt: JATD1: JATD0: JSCI1: JSCI0: JSPI0: JPACCAEdge: JPACCAOv: JTimerOv: JTimerCh7: JTimerCh6: JTimerCh5: JTimerCh4: JTimerCh3: JTimerCh2: JTimerCh1: JTimerCh0: JRTI: JIRQ: JXIRQ JSWI: JIllop: JCOPFail: JClockFail: dc.b dc.b PWMEShutdown: dc.w $ff8c JPWMEShutdown value security byte unsecured state. $ff0f location security byte. setup bootblock Flash block $ff0d [MSCAN0Rx-BootBlkSize,pcr] [MSCAN0Errs-BootBlkSize,pcr] [MSCAN0WakeUp-BootBlkSize,pcr] [Flash-BootBlkSize,pcr] [EEPROM-BootBlkSize,pcr] [SPI2-BootBlkSize,pcr] [SPI1-BootBlkSize,pcr] [IICBus-BootBlkSize,pcr] [DLC-BootBlkSize,pcr] [SCMEVect-BootBlkSize,pcr] [CRGLock-BootBlkSize,pcr] [PACCBOv-BootBlkSize,pcr] [ModDnCtr-BootBlkSize,pcr] [PortHInt-BootBlkSize,pcr] [PortJInt-BootBlkSize,pcr] [ATD1-BootBlkSize,pcr] [ATD0-BootBlkSize,pcr] [SCI1-BootBlkSize,pcr] [SCI0-BootBlkSize,pcr] [SPI0-BootBlkSize,pcr] [PACCAEdge-BootBlkSize,pcr] [PACCAOv-BootBlkSize,pcr] [TimerOv-BootBlkSize,pcr] [TimerCh7-BootBlkSize,pcr] [TimerCh6-BootBlkSize,pcr] [TimerCh5-BootBlkSize,pcr] [TimerCh4-BootBlkSize,pcr] [TimerCh3-BootBlkSize,pcr] [TimerCh2-BootBlkSize,pcr] [TimerCh1-BootBlkSize,pcr] [TimerCh0-BootBlkSize,pcr] [RTI-BootBlkSize,pcr] [IRQ-BootBlkSize,pcr] [XIRQ-BootBlkSize,pcr] [SWI-BootBlkSize,pcr] [Illop-BootBlkSize,pcr] [COPFail-BootBlkSize,pcr] [ClockFail-BootBlkSize,pcr]
MOTOROLA
More Information This Product, www.freescale.com
0000F62F 0000F633 0000F637 0000F63B 0000F63F 0000F643 0000F647 0000F64B 0000F64F 0000F653 0000F657 0000F65B 0000F65F 0000F663 0000F667 0000F66B 0000F66F 0000F673 0000F677 0000F67B 0000F67F 0000F683 0000F687 0000F68B 0000F68F 0000F693 0000F697 0000F69B 0000F69F 0000F6A3 0000F6A7 0000F6AB 0000F6AF 0000F6B3 0000F6B7 0000F6BB 0000F6BF 0000F6C3
05FBF97F 05FBF97D 05FBF97B 05FBF979 05FBF977 05FBF975 05FBF973 05FBF971 05FBF96F 05FBF96D 05FBF96B 05FBF969 05FBF967 05FBF965 05FBF963 05FBF961 05FBF95F 05FBF95D 05FBF95B 05FBF959 05FBF957 05FBF955 05FBF953 05FBF951 05FBF94F 05FBF94D 05FBF94B 05FBF949 05FBF947 05FBF945 05FBF943 05FBF941 05FBF93F 05FBF93D 05FBF93B 05FBF939 05FBF937 05FBF935
0000FF0D
0000FF0D
0000FF0F
0000FF0F
0000FF8C
Application Note Code Listing
0000FF8C F5E3
Freescale Semiconductor, Inc.
Application Note
PortPInt: MSCAN4Tx: MSCAN4Rx: MSCAN4Errs: MSCAN4WakeUp: MSCAN3Tx: MSCAN3Rx: MSCAN3Errs: MSCAN3WakeUp: MSCAN2Tx: MSCAN2Rx: MSCAN2Errs: MSCAN2WakeUp: MSCAN1Tx: MSCAN1Rx: MSCAN1Errs: MSCAN1WakeUp: MSCAN0Tx: MSCAN0Rx: MSCAN0Errs: MSCAN0WakeUp: Flash: EEPROM: SPI2: SPI1: IICBus: DLC: SCMEVect: CRGLock: PACCBOv: ModDnCtr: PortHInt: PortJInt: ATD1: ATD0: SCI1: SCI0: SPI0: PACCAEdge: PACCAOv: TimerOv: TimerCh7: TimerCh6: TimerCh5: TimerCh4: TimerCh3: TimerCh2: TimerCh1: TimerCh0: RTI: dc.w dc.w dc.w dc.w dc.w dc.w dc.w dc.w dc.w dc.w dc.w dc.w dc.w dc.w dc.w dc.w dc.w dc.w dc.w dc.w dc.w dc.w dc.w dc.w dc.w dc.w dc.w dc.w dc.w dc.w dc.w dc.w dc.w dc.w dc.w dc.w dc.w dc.w dc.w dc.w dc.w dc.w dc.w dc.w dc.w dc.w dc.w dc.w dc.w dc.w JPortPInt JMSCAN4Tx JMSCAN4Rx JMSCAN4Errs JMSCAN4WakeUp JMSCAN3Tx JMSCAN3Rx JMSCAN3Errs JMSCAN3WakeUp JMSCAN2Tx JMSCAN2Rx JMSCAN2Errs JMSCAN2WakeUp JMSCAN1Tx JMSCAN1Rx JMSCAN1Errs JMSCAN1WakeUp JMSCAN0Tx JMSCAN0Rx JMSCAN0Errs JMSCAN0WakeUp JFlash JEEPROM JSPI2 JSPI1 JIICBus JDLC JSCME JCRGLock JPACCBOv JModDnCtr JPortHInt JPortJInt JATD1 JATD0 JSCI1 JSCI0 JSPI0 JPACCAEdge JPACCAOv JTimerOv JTimerCh7 JTimerCh6 JTimerCh5 JTimerCh4 JTimerCh3 JTimerCh2 JTimerCh1 JTimerCh0 JRTI
More Information This Product, www.freescale.com
0000FF8E 0000FF90 0000FF92 0000FF94 0000FF96 0000FF98 0000FF9A 0000FF9C 0000FF9E 0000FFA0 0000FFA2 0000FFA4 0000FFA6 0000FFA8 0000FFAA 0000FFAC 0000FFAE 0000FFB0 0000FFB2 0000FFB4 0000FFB6 0000FFB8 0000FFBA 0000FFBC 0000FFBE 0000FFC0 0000FFC2 0000FFC4 0000FFC6 0000FFC8 0000FFCA 0000FFCC 0000FFCE 0000FFD0 0000FFD2 0000FFD4 0000FFD6 0000FFD8 0000FFDA 0000FFDC 0000FFDE 0000FFE0 0000FFE2 0000FFE4 0000FFE6 0000FFE8 0000FFEA 0000FFEC 0000FFEE 0000FFF0
F5E7 F5EB F5EF F5F3 F5F7 F5FB F5FF F603 F607 F60B F60F F613 F617 F61B F61F F623 F627 F62B F62F F633 F637 F63B F63F F643 F647 F64B F64F F653 F657 F65B F65F F663 F667 F66B F66F F673 F677 F67B F67F F683 F687 F68B F68F F693 F697 F69B F69F F6A3 F6A7 F6AB
AN2153
MOTOROLA
Freescale Semiconductor, Inc.
IRQ: XIRQ: SWI: Illop: COPFail: ClockFail: Reset: None $0000FFFF $FFFFFFFF $000006F4 $0000004E 1780 dc.w dc.w dc.w dc.w dc.w dc.w dc.w JIRQ JXIRQ JSWI JIllop JCOPFail JClockFail BootStart
AN2153
MOTOROLA
0000FFF2 0000FFF4 0000FFF6 0000FFF8 0000FFFA 0000FFFC 0000FFFE
F6AF F6B3 F6B7 F6BB F6BF F6C3 F000
Errors: Labels: Last Program Address: Last Storage Address: Program Bytes: Storage Bytes:
More Information This Product, www.freescale.com Application Note Code Listing
Freescale Semiconductor, Inc. Application Note
Freescale Semiconductor, Inc.
AN2153 More Information This Product, www.freescale.com MOTOROLA
Application Note Code Listing
Freescale Semiconductor, Inc.
AN2153 MOTOROLA More Information This Product, www.freescale.com
Freescale Semiconductor, Inc. Application Note
Freescale Semiconductor, Inc.
Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters which provided Motorola data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. Motorola registered trademarks Motorola, Inc. Motorola, Inc. Equal Opportunity/Affirmative Action Employer.
reach USA/EUROPE/Locations Listed: Motorola Literature Distribution; P.O. 5405, Denver, Colorado 80217. 1-303-675-2140 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu, Minato-ku, Tokyo 106-8573 Japan. 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, King Street, Industrial Estate, N.T., Hong Kong. 852-26668334 Technical Information Center: 1-800-521-6274 HOME PAGE:
Motorola, Inc., 2001
AN2153/D More Information This Product, www.freescale.com
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