AN1837 Freescale Semiconductor, Inc. Non-Volatile Memory Tec
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Non-Volatile Memory Technology Overview
Stephen Ledford Non-Volatile Memory Technology Center Austin, Texas
Introduction
Today's microcontroller applications more sophisticated with application code requirements increasing size. Code development represents significant investment time resources initial development debug application. Since code application embedded on-chip memory, this represents some challenges, especially with debug cycle which code bugs identified, fixes generated, ultimate implementation back into memory microcontroller. With conventional mask (read-only memory), this debug cycle could represent many weeks from point identification code issue validation code with product. light debug cycle time issue with on-chip mask ROM, emulation development option microcontroller required enable reduction time required debug learning cycle. While (random-access memory) could provide quick simple means enabling quick code updates, complete replacement mask since contents lost soon power removed. this primary differentiation with volatility nonvolatility other classes memories discussed here that
Motorola, Inc., 2000
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Freescale Semiconductor, Inc. Application Note
term non-volatile memory (NVM) become important world microcontrollers. past product generations, memory replaced with EPROM enable programming application code, erasure with (ultraviolet) light, reprogramming code debug cycle. More recent products have utilized FLASH EEPROM (electrically erasable programmable read-only memory) rather than EPROM memory continue improve debug cycle even more well resolve some disadvantages presented EPROM memory.
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addition EPROM FLASH EEPROM memory code development purposes, many products incorporate smaller byte erasable EEPROM memory permanent scratch memory, data storage, storing unique product characteristics, well many other purposes. This category non-volatile memory offers some unique characteristics that usually found FLASH EEPROM memories such byte erasability higher endurance characteristics. There very high level diversity non-volatile memory application needs evident from products offered Motorola. these reasons, well many others, unique technologies have been developed major (microcontroller unit) families, M68HC12, M68HC08, M68HC3xx, MPC. This application note describes three major FLASH EEPROM technologies currently found these MCUs. explanation characteristics these memories provided features that enable certain characteristics such high density low-power operation. Non-volatile memory also presents broad array terms describe EPROM byte erasable EEPROM memories, introduction these terms with definitions included. Finally, EEPROM represents similar unique category explanation basic operation critical enabling characteristics provided this class memories.
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Application Note Common Terms Definitions
Common Terms Definitions
landscape extremely broad requires that terms introduced describe behavior characteristics memory well what differentiates memory type from another.
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Read-only memory name implies, memory only read. memory elements hard coded during wafer manufacturing process cannot changed altered. This type memory commonly used program code storage microcontroller permanent look tables parameters.
EPROM
Electrically programmable read-only memory This memory type unique when compared that memory programmed electrically versus hard coding memory elements during wafer manufacturing process. similar that after programming event occurred, memory only read. alter memory, array must first erased exposing surface ultraviolet light which then permits programming contents memory array. Since surface must able exposed light perform erase operation, quartz windowed ceramic package must used which expensive. result, EPROM products sometimes packaged conventional plastic package which allows programming without window expose surface. unit cannot erased subsequently reprogrammed. this configuration, product referred onetime programmable offers lower cost sacrificing ability reprogram same device.
EEPROM
Electrically erasable programmable read-only memory name implies, this category memory electrically erased versus EPROM operation erasure requiring surface exposed light. Therefore, there special packaging requirements take advantage memory features. term EEPROM quite commonly used itself refer byte- erasable
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Freescale Semiconductor, Inc. Application Note
EEPROM. reasons utilization this term this become apparent with next definition.
FLASH EEPROM
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This family uses acronym EEPROM since shares electrical characteristics being able electrically erased programmed. However, phrase "FLASH" been added describe erase operation distinguish from byte-erasable EEPROM memories. phrase FLASH refers manner which erase operation performed. instance, either entire memory array large block memory erased during operation, which improves throughput reprogramming memory array. There many other differences reasons differentiating FLASH EEPROM from byte-erasable EEPROM, these will highlighted detailed description each class memory. FLASH EEPROM commonly referred simply FLASH memory phrase that encompasses characteristics EEPROM while contrasting with byte-erasable EEPROM.
Endurance
particular, this critical characteristic EEPROM class memories. Since EEPROM electrically erased reprogrammed, well suited applications that require values permanently stored updated ongoing basis application. result, memory cycled between programmed erased data states many times. more detailed description program erase operations provided later these operations require high voltage applied bitcell change data states. This high voltage degrades electrical operation bitcell small amount each time cumulatively reach point after which bitcell longer operates properly.
Data Retention
Since manufactured that hard codes contents array, subject data retention commonly applied ROM. However, electrically programmable memory changes data states placing removing charge electrically isolated piece material. detailed description these operations provided later. defect isolating oxides surrounding material used store charge
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Application Note Common Terms Definitions
results leakage path stored charge. bitcell data state changed result charge loss charge gain floating gate. Therefore, data retention parameter that defines ability retain data across defined operating specification. Data retention applies classes EPROM EEPROM.
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Channel electron commonly used programming mechanism EPROM some types FLASH EEPROM. When large bias placed drain terminal CMOS (complementary metal-oxide semiconductor) transistor, minority carriers flow through channel transistor become heated result high electric field drain side channel which results their energy being shifted higher. When some minority carriers gain enough energy, they able surmount silicon dioxide energy barrier turn injected over barrier onto floating gate device. important fact remember about that one-way programming mechanism only. other words, capable performing programming operation reverse case, erase, possible. more complete description provided discussion various memory technologies. This mechanism sometimes also referred carrier injection.
Fowler-Nordheim Tunneling
This alternate form injection floating gate devices. technical description this mechanism field assisted electron tunneling. This different from that mechanism created result high electric field between gate device source drain. field large enough, lowers height energy barrier, silicon dioxide layer, electrons. Then tunnels through silicon dioxide onto floating gate. referred Fowler-Nordheim tunneling after scientists Fowler Nordheim identified case electrons tunneling through vacuum barrier. Lenzingler Snow later described case oxide tunneling. Again, more thorough explanation provided this application note part discussion various memory technologies.
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Freescale Semiconductor, Inc. Application Note Non-Volatile Memory Operation
This section deals with operation non-volatile memory (NVM). description used first foundation operation comparison electrically alterable memory classes follow. viewed simplest non-volatile memory class because memory "programmed" during wafer manufacturing process taking advantage masking layers used during formation transistors. most commonly used methods performing this "programming" utilization nitride layer, sometimes referred active layer. following transistor cross sections help describe this process. These diagrams represent entire wafer manufacturing process ones that important formation bitcell.
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PHOTO RESIST NITRIDE
PHOTO RESIST
SILICON SUBSTRATE
Figure Nitride Photo Patterning Early wafer fabrication process layer nitride deposited across surface wafer. photo resist then applied nitride subsequently exposed photo-lithography process step. result cross section shown Figure where opening photo resist ultimately will result bitcell that "programmed" area where photo resist remains, resulting bitcell that "programmed."
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Application Note Non-Volatile Memory Operation
PHOTO RESIST NITRIDE
PHOTO RESIST
NITRIDE SILICON SUBSTRATE
Figure Nitride Etch next steps that take place etch exposed nitride, leaving silicon substrate exposed subsequent process steps. photo resist acts etch block preventing nitride underneath resist from being etched away.
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NITRIDE FIELD OXIDE
NITRIDE
SILICON SUBSTRATE
Figure Photo Resist Removal Field Oxidation Next, photo resist removed, leaving nitride exposed. nitride sometimes referred hard mask, meaning sacrificial layer used define certain areas wafer. this case, high temperature oxidation cycle will form silicon dioxide regions wafer covered nitride layer shown Figure resulting oxide very thick normally used throughout design isolating layer between transistors signal layers running across die.
POLY-SI POLY-SI FIELD OXIDE SILICON SUBSTRATE
Figure Nitride Removal, Gate Oxidation, Gate Poly Formation cross section Figure result several process steps. nitride been removed thin layer silicon dioxide been grown regions that were under nitride layer. This oxide growth used insulating layer under polysilicon form gate
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CMOS transistor. Polysilicon then deposited across wafer, photo resist applied shown earlier with nitride layer, photo resist patterned, extra unwanted polysilicon etched away, leaving only polysilicon used form gate transistor. array design polysilicon gates bitcell locations represented this diagram. However, case unprogrammed bitcell, polysilicon left field oxide which results significantly different transistor characteristics. importance this difference described sections that follow.
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POLY-SI FIELD OXIDE SOURCE
GATE POLY-SI DRAIN
SILICON SUBSTRATE
Figure Source Drain Formation final steps transistor formation implantation source drain regions. Additional wafer processing required define metal interconnect routing transistors together. This additional processing represented here because same classes transistors. From circuit design perspective, previous build steps these transistors described Figure
THICK FIELD TRANSISTOR THRESHOLD VOLTAGE WORDLINE
NORMAL TRANSISTOR THRESHOLD VOLTAGE
BITLINE
BITLINE
Figure Bitcell Schematic Diagram transistor left same transistor build-up diagram left referred thick field transistor. Likewise, transistor right same build-up diagram normal n-channel transistor. critical difference transistors threshold voltage transistors. threshold voltage
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Application Note Non-Volatile Memory Operation
different thickness oxide under polysilicon gate. typical transistor with standard gate oxide will have threshold voltage range volts. Since field oxide very thick relative conventional gate oxide, threshold voltage this transistor very high, greater than volts. high threshold voltage important because read byte data from array, wordline corresponding selected address raised VDD. bitlines also corresponding this byte also raised voltage close VDD, sources transistors grounded. These bias conditions normal transistor with threshold voltage volts conduct current which then sensed, latched, driven array. Since thick field transistor threshold voltage above volts, when placed wordline bitline transistor cannot turned will conduct current. This state thick field transistor corresponds opposite data state bitcell that conducts current. important understand basic concepts introduced bitcell ability bitcell either conduct current inhibit conduction current reused operation other electrically changeable memory types. also important understand that bitcell formation function standard wafer fabrication process which much simpler than process required build EPROM EEPROM memory bitcells. Further discussion these memory types bear this point out. Finally, there alternate methods building bitcell. description here most common method bitcell formation. "programming" step uses nitride layer which occurs early wafer fabrication process. This method drawback relatively long cycle time from receipt code delivery samples containing code. result, there alternate methods achieving same result enabling disabling transistor from conducting current. these alternate techniques have goal pushing "programming" step late wafer fabrication process possible reduce cycle time turn code customer. circuit operation same.
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Freescale Semiconductor, Inc. Application Note
EPROM EPROM first widely deployed non-volatile memory technologies, been replaced gradually FLASH EEPROM over past years. EPROM used extensively applications that required permanent storage application code, opposed whose contents would lost removal power, want utilize mask programmable reasons previously discussed. Remember from description manufacturing process concept introduced transistor threshold voltage, this relates data state transistor. same also true nonvolatile memories means achieving these states physically much different. diagram Figure useful understanding operation EPROM bitcell well describing concepts reused other categories, EEPROM FLASH EEPROM.
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CONTROL GATE FLOATING GATE POLY-SI SOURCE POLY-SI DRAIN WORDLINE
TUNNEL OXIDE
SILICON SUBSTRATE
BITLINE
Figure EPROM Bitcell Cross Section Schematic seen from diagram, bitcell constructed much differently from typical CMOS transistor used design. particular, notice extra gate bitcell referred floating gate. referred floating because isolated sides does come electrical contact with terminal. dielectric layer below floating gate commonly referred tunnel oxide. nature this term described further later. layer transistor similar function performed gate CMOS transistor, described bitcell, also performs some additional functions programming operation. Programming bitcell done mechanism referred channel electron (CHE). large voltage, approximately volts, placed drain, volts, ground, source, slightly positive voltage
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Application Note Non-Volatile Memory Operation
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placed gate device. high voltage difference between source drain device what heats minority carriers channel. previously described Common Terms Definitions, some these carriers have enough energy surmount barrier presented tunnel oxide become trapped floating gate. Even though programming operation accomplished injection, oxide under floating gate still commonly referred tunnel oxide, although this somewhat misnomer. programming operation requires high programming current bitcell CHE. Because this, most EPROM products have high voltage supply pin, referred VPP, that provides high voltage used programming operation.
CONTROL GATE
SOURCE VOLTS
DRAIN VOLTS
Figure Channel Electron Programming Mechanism Programming does itself refer particular data state bitcell, because possible logical inversion output from core memory array output data bus, programmed state correspond either logic Therefore, sometimes easier when discussing mechanics programming erase operations refer effect either enabling channel conduct conduct current. With this frame reference, programming operation EPROM bitcell injects electrons onto floating gate transistor which raises threshold voltage channel. typical read operation memory array will place onto wordline just read mode. transistor approaches level VDD, channel will longer conduct sufficient current which will result bitcell being read programmed. item identified definition time program bitcell. Although there some variations around these targets,
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Freescale Semiconductor, Inc. Application Note
programming typically specified take between location.
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Figure Effects Programming Bitcell case EPROM technology, erase operation performed exposing bitcell light. light effect removing electrons stored floating gate returning state what referred charge neutral, which will move lower enable formation channel when wordline selected read operation. These concepts reused description other memory technologies form basis most technology found commercial today. From description program erase operations, importance floating gate seen with respect acting storage node even power removed from device. bitcell remain programmed state, materials surrounding floating gate must good insulators prevent loss charge from floating gate. ability floating gate remain charge state commonly referred data retention. This where major challenge arises technology development. general, thicker materials surrounding floating gate, more robust data retention will However, materials must thin enough allow programming mechanisms such take place within reasonable program time. challenge finding right balance manufacturing these dielectric materials that provides acceptable programming times with robust data retention characteristics.
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Application Note Non-Volatile Memory Operation
EEPROM
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primary disadvantages EPROM requirement exposing bitcells light reprogram contents. This prove difficult, unit already attached application board, requires expensive ceramic package with quartz window. package cost reduced placing conventional plastic package sacrifice ability erase reprogram. Therefore, solution this problem required that provided ability electrically erase memory array. This first satisfied with introduction EEPROM technology. addition providing ability erase array electrically, EEPROM also adds ability erase reprogram individual bytes within memory without altering other contents. This added functionality results larger bitcell when compared EPROM. provide byte addressability modes, program, erase, read, second transistor must added bitcell referred select transistor. cross section schematic representation EEPROM bitcell shown Figure
CONTROL GATE POLY-SI SOURCE POLY-SI FLOATING GATE SELECT TRANSISTOR POLY-SI DRAIN WORDLINE TUNNEL OXIDE SILICON SUBSTRATE BITLINE SELECTLINE
Figure EEPROM Bitcell Cross Section Schematic Remember from description that one-way mechanism. other words, move electrons onto floating gate, cannot remove them from floating gate. EEPROM fills this role providing erase mechanism Fowler-Nordheim tunneling. Since tunneling created result high electric field between terminals provides robust solution problem erase. high voltage, range volts, placed control gate storage transistor while placing volts source drain transistor. very high voltage difference between source/drain control gate what activates Fowler-Nordheim tunneling,
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Freescale Semiconductor, Inc. Application Note
removes charge from floating gate, seen from Figure
CONTROL GATE CONTROL GATE
SOURCE SILICON SUBSTRATE ERASE OPERATION
DRAIN
SOURCE SILICON SUBSTRATE PROGRAM OPERATION
DRAIN
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Figure Fowler-Nordheim Tunneling EEPROM Bitcell This diagram also shows programming operation being performed with Fowler-Nordheim tunneling well. described previously, EPROM bitcells programmed which requires external high voltage supply provide current required enable mechanism. provide full program erase within circuit without need external supplies, lower-power programming method required. Fowler-Nordheim tunneling requires little current from high voltage supply used during program erase operations. primarily this reason that Fowler-Nordheim tunneling been adopted programming mechanism addition using erase mechanism. Simple charge pumping schemes used generate these high voltages chip providing self-contained solution without need supplying external high voltage supplies. item identified definition Fowler-Nordheim tunneling time program erase bitcell. Although some variations around these targets, both program erase operations typically specified take between location. seen Figure programming operation performed placing high voltage drain storage transistor which sets field with opposite polarity, with erase operation, tunnels electrons onto floating gate. Since high voltage programming placed only drain, electric field along drain edge device this region that tunneling takes place. importance select transistor comes into effect when needing selectively program only byte. memory array, multiple bitcells share common bitline, high 2048. there
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Application Note Non-Volatile Memory Operation
block this high voltage from drain unselected bitcell, then other bitcells also would programmed. select transistor performs task blocking high voltage from reaching unselected bitcells seen Figure
SELECTLINE
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WORDLINE
SELECTLINE WORDLINE
BITLINE
BITLINE
Figure Selected Unselected Bitcells during Programming selectline byte programmed must raised same voltage, higher, pass voltage placed drain. volts placed unselected byte's selectline, then voltage along bitline cannot passed storage device preventing from being programmed. Since there also many bitcells wordline bitcells sharing selectline will able pass high voltage, another level decode required well. seen from Figure bitline right volts placed hence will programmed since high voltage will drain storage device. bias condition volts bitline will bits along same that will left unchanged during programming operation. astute reader would note that during erase volts applied wordline this would mean that bits along wordline would erased. byte erase achieved with this architecture? answer that wordline broken into byte wide word wide pieces, depending width, decoded each location.
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Freescale Semiconductor, Inc. Application Note
example, there were bits wordline array ability erase eight bits individually, that would mean there would break wordline every eight bits total separate locations. point each break, simple pass transistor commonly used selectively pass high voltage onto control gates based location erased. From this description seen that extra overhead EEPROM array required implement extra features. second transistor, select device, must added each bitcell achieve byte programmability, wordline must decoded byte basis well achieve byte erasability. Both these features area memory array implementation result same number EEPROM bits consuming more area silicon than implemented with EPROM. added overhead both bitcell with select transistor array with erase decoding byte, most EEPROM arrays small general several kilobytes size.
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FLASH EEPROM
previous section covered EEPROM added features capability that category memory offers application. However, these added features come price larger memory arrays when compared EPROM. this reason, another category non-volatile memory been developed. FLASH memory developed provide in-circuit, electrical erase offered EEPROM also optimizing architecture reduce area memory array. primary method used achieve this modification features memory particular removal byte-erase feature sometimes also byte program feature. FLASH EEPROM, sometimes referred just name FLASH, offered standalone memory many companies well many others offering FLASH embedded applications. result, many different implementations found industry. generic overview FLASH memory more focused examination FLASH memory technologies found Motorola products presented here.
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Application Note Non-Volatile Memory Operation
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mentioned, primary difference between EEPROM FLASH EEPROM removal ability erase byte level. FLASH erases much larger chunks memory commonly referred sectors. Depending array size technology chosen, sector size vary significantly therefore there standard erase sector size across industry even within product family. main point remember that array erased large pieces opposed byte erase found full featured EEPROM. Almost commercially available FLASH memories utilized Fowler-Nordheim tunneling erase operation. second major difference relates programming programming size here again there clear standard across industry. Some FLASH memories will away with byte programming together will program large sections referred pages. Other FLASH memories still retain ability program byte wide increments. choice programming width mostly determined throughput erasing memory completely reprogramming array. There also some diversity among FLASH memory products with respect programming method. example, some FLASH products others Fowler-Nordheim tunneling. been previously described EPROM EEPROM overviews, each method pros cons, these limitations that drive programming size array. Remember from discussion EPROM that requires relatively high current, especially when compared Fowler-Nordheim tunneling. However, Fowler-Nordheim tunneling requires more time program memory location than does CHE. Therefore, compensate longer time required programming location using Fowler-Nordheim tunneling, programming size larger than that used with CHE. cannot scale with respect program size because high current required activate mechanism. Although there certainly power supplies that supply many amps current part, there issue with power distribution within chip itself. general, this limits programming size when using bits. look each FLASH memory technologies found Motorola MCUs will addressed.
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Freescale Semiconductor, Inc. Application Note
1.5T FLASH EEPROM This memory technology found 68HC12, 68HC16, 68HC3xx Families microcontrollers. Development technology dates back 1990 first FLASH memory offered embedded Motorola products. name 1.5T FLASH comes from arrangement bitcell this case indicates that half transistors comprise bitcell. fact that name implies that there possibility half transistor seem odd, impossible, actuality indicates construction bitcell category referred split gate. other words, there gate within bitcell that structurally shared with another gate resulting half transistor. cross section down view bitcell Figure helps explain this concept.
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CONTROL GATE POLY-SI SOURCE POLY-SI
FLOATING GATE
WORDLINE DRAIN
SILICON SUBSTRATE BITLINE
Figure 1.5T FLASH Bitcell Cross Section Schematic
CONTROL GATE FLOATING GATE DRAIN
SOURCE
Figure 1.5T FLASH Bitcell Down View half transistor case 1.5T FLASH comes from shared gate formed control gate overlapping channel source side. This extended overlap essentially forms select transistor source side storage node. This bitcell architecture unique when compared conventional EPROM EEPROM bitcells. particular, EEPROM erase operation occurs same channel
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transistor program operation. 1.5T bitcell different that programming occurs channel function CHE. However, erase operation occurs within source region with part floating gate that extends into source. This this bitcell architecture sometimes referred technical name source coupled split gate (SCSG) FLASH EEPROM. During erase operation, source actually what driven high voltage, approximately volts, with control gate VSS, volts, drain left floating. control gate voltage capacitively coupled floating gate, subsequent potential difference between source floating gate what activates erase operation. mentioned, program operation conducted with CHE. source driven VSS, volts, control gate held approximately volts, drain voltage approximately volts. lateral potential difference between source drain what activates CHE, high voltage control gate what forms channel. microcontrollers that utilize 1.5T FLASH memory have external high voltage program erase FLASH memory. externally applied voltage typically range volts, quite often question arises about higher external voltage required than what used internally bitcell. simple explanation that paths from external internal nodes perfect lossless. Because switches CMOS, particular high voltage switches necessary this technology, experience voltage drops function their threshold voltage, resistance channel, other characteristics transistor, external voltage applied usually higher than internally driven voltages. This that internal nodes regulated independent externally applied voltage. other words, externally applied voltage targeted volts external circuit applies 12.5 volts, there will increase internal nodes approximately volts.
WARNING:
Depending maximum ratings transistors used path from external internal node, over voltage small volts result serious damage transistors, bitcells, support circuitry that could permanently damage degrade operation.
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Freescale Semiconductor, Inc. Application Note
formation select transistor source side device opposed drain side EEPROM results some different characteristics being introduced into bitcell operation. Keep mind that placement select transistor drain side EEPROM bitcell done primarily block high voltages from reaching storage transistor, thus providing selective program erase. Since select transistor been moved from drain side source side, result that bitcell subjected data disturbs well. Disturb comes primarily from programming another location along same bitline array this technology. high voltage applied bitline during programming operation, since select transistor opposite side device, cells along bitline will high voltage stress. This effect managed through careful precise programming sequence, well proper balance voltages along control gate drain selected case rate disturb with drain-only bias unselected cells.
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FLASH EEPROM
FLASH development started 1994 several targeted features that drove FLASH memory technology development. particular, M68HC08 Family microcontrollers targeted minimum volts well very power operation. noted discussion 1.5T FLASH, this technology capable supporting products that operate range volts. Although circuit design methods used overcome some limitations with respect ability operate with below volts, virtually them result higher power consumption. Obviously, with primary objective operating lower reduce power consumption, pushing 1.5T technology would achieve desired features lower lower power operation. result development effort bitcell that looks first glance very similar conventional EEPROM bitcell, seen cross section schematic views bitcell. (See Figure 15.) However, upon closer inspection, noticeable that primary difference between FLASH bitcell regular EEPROM bitcell placement select transistor relative storage transistor. Remember from EEPROM description that select transistor positioned between storage transistor bitline. bitcell
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reverses these positions with storage transistor directly positioned bitline select transistor source side. Consequently, this technology sometimes referred more complete technical name source select, 2TS, versus EEPROM bitcell which drain select, 2TD.
CONTROL GATE SELECT TRANSISTOR SOURCE POLY-SI POLY-SI POLY-SI DRAIN SELECTLINE TUNNEL OXIDE SILICON SUBSTRATE BITLINE TUNNEL OXIDE FLOATING GATE WORDLINE
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Figure FLASH Cross Section Schematic Although this simple rearrangement transistors bitcell would seem small modification, forms critical feature that enables bitcell operate both lower with lower power. During description 1.5T technology, there some discussion about circuit design methods required switch high voltage within circuit. typical logic transistor only withstand normal operating voltages which vary technology generation, some high volts, this been consistently dropping with latest 0.25-µ generation operating with typical volts. gate oxide logic transistor what commonly dictates this upper operating limit. Therefore, pass high voltages like those typically found non-volatile memory designs, another transistor type with thicker gate oxide typically required withstand these high voltages. common trade-offs made when thickening gate oxide that dimensions transistor must larger together these parameters generally result transistor being slower with respect switching speed. case program erase operations, slower switching speed limiting factor, since operations take many microseconds perform. However, transistor switching speed critical read performance, this where high-voltage transistors within design create challenges voltage lowpower operation.
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Freescale Semiconductor, Inc. Application Note
considering EEPROM bitcell, high voltage must applied bitline programming select gate well control gate during erase. High voltage transistors must used paths these nodes withstand voltages required perform these operations. During normal read operation, bitline selectline must driven each access cycle speed. However, high voltage transistors will slower switch thicker gate oxide larger dimensions transistor which results memory performing fast other logic design. Typically, this difference noticeable voltage range volts EEPROM 1.5T FLASH. lowered below volts, high voltage transistors cannot support performance requirements limit ability memory read rated speed. common design technique used work around this problem voltage boosting circuits along selectline bitline. concept boosting circuit take input voltage that low, example volts, through some charge pumps raise voltage level. While this will, effect, lower operating voltage range memory array, adds considerable power consumption read operation because charge pumps that must always active. This option effective applications where lowering voltage range more important than lowering overall power consumption memory array. FLASH attacks this issue eliminating high voltages along typical read path, bitline, selectline, allowing standard logic transistors these nodes. achieve this, first modification that must done move select transistor from drain side storage transistor source side. Programming performed through Fowler-Nordheim tunneling applying volts control gate, floating source turning select transistor, driving volts onto bitline. With this split bias scheme, only node within bitcell that sees high voltage control gate. Remember that Fowler-Nordheim tunneling activated potential difference between nodes electric field created result. fact that control gate driven below negative voltage what sets large potential difference activates FowlerNordheim tunneling.
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Application Note Non-Volatile Memory Operation
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Erase accomplished similar fashion. source driven through select transistor turning transistor control gate driven approximately volts, drain placed VSS. These biases electric field required activate Fowler-Nordheim tunneling erase bitcell. Again, high voltage applied only control gate transistor while selectline bitline stay within normal logic operating levels. Since critical switching nodes array read mode, bitline selectline, always stay within normal voltage range product, regular logic transistors used. result that memory array operate within same range rest logic chip. Finally, since nodes have driven only with regular logic levels achieve desired performance read mode, charge pumps need during read mode low-power operation also achieved. bitcell design does come without disadvantages. During discussion 1.5T FLASH, subject bitcell data disturbs introduced. Also keep mind that placement select transistor drain side EEPROM bitcell done primarily block high voltages from reaching storage transistor thus providing selective program erase. Since select transistor been moved from drain side source side FLASH bitcell, result that subjected data disturbs well. Disturb comes primarily from programming another location within same array. programming operation places volts control gates bitcells along row. bitcell selected placing volts along bitline while unselected bitcell volts along bitline. potential difference selected bitcell will |17V|, unselected bitcell still relatively high difference |12V|. This translates unselected bits being exposed weak programming event. good balance must achieved between time program regular bitcell time disturb unselected bitcell. Other preventative measures must taken manage disturbs. There natural level variation program time across array with some bitcells programming faster than others. method minimizing exposure that unselected bitcells have adaptive programming algorithm. result, some specification items must added such programming step size maximum number
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Freescale Semiconductor, Inc. Application Note
program pulses. Without adaptive programming algorithm, programming time spec would have derived based upon worst case program time across entire array. This type spec would into operating margin disturb would likely render product manufacturable best very difficult manufacture. adaptive programming algorithm benefit user. Since programming operation takes more time than required each location, overall program time entire array much faster than worst case value used locations.
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FLASH
transistor FLASH, FLASH, what most commonly used industry standalone FLASH memory. popular among standalone memories since bitcell area tends dominate very large memory arrays select transistor takes silicon real estate. Many details related bitcell operation array vary among manufacturers thus possible cover these this discussion. However, description FLASH technology becoming available several Motorola microcontroller products provided. From structural point view, bitcell appears very similar EPROM bitcell discussed earlier. cross section schematic view bitcell identical high level, this where similarities stop. (See Figure 16.)
CONTROL GATE POLY-SI SOURCE POLY-SI DRAIN WORDLINE TUNNEL OXIDE SILICON SUBSTRATE BITLINE FLOATING GATE
Figure FLASH Bitcell Cross Section Schematic case Motorola implementation FLASH embedded products, programming erase operations performed Fowler-Nordheim tunneling. Other vendor's implementations utilize programming operation, Fowler-Nordheim tunneling almost
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Application Note Non-Volatile Memory Operation
universally used perform erase operation. case products with 1.5T FLASH technology, products utilizing FLASH have external high voltage supply programming operation. FLASH design also uses external high voltage supply program operations used generate control gate drain voltages required sustain Fowler-Nordheim tunneling operation.
WARNING:
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Great care must taken properly control this external high voltage supply just with 1.5T technology internal damage result small drift this supply voltage. Some technical challenges that must addressed managed arise from elimination select transistor from bitcell. Recall from discussions EEPROM 1.5T FLASH technologies that inclusion select transistor provided varying degrees protection bitcell during program operation advantages read performance case FLASH. Some additional functions select transistor performs array operation those technologies have been discussed here, they become critically important operation FLASH. read particular bitcell EEPROM, 1.5T FLASH, wordline must raised level. voltage applied turns select transistor which then allows actual storage transistor access bitline. FLASH bitcell does have separate select transistor read operation performed similar fashion. This itself does present problem this replicates read mode operation EPROM bitcell comes result introduction erase operation single transistor bitcell. bitcell erased long, condition referred over-erase result. basic explanation this effect that during erase operation bitcell moved. moved far, bitcell will operate depletion mode, meaning that regardless voltage applied gate transistor will always conduct current effect that when wordline unselected, lowered VSS, bitcell will still conduct current pull down bitline resulting bits along bitline reading erased. This problem EPROM bitcells since exposure light returns floating gate charge neutral
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Freescale Semiconductor, Inc. Application Note
state, which design depletion mode. This problem EEPROM, 1.5T FLASH, FLASH since select transistor will prevent conduction even storage transistor operating depletion mode. Another problem arises bitcell over-erased. only will bitcell cause other bitcells along bitline read erased, also will prevent other bitcells along bitline from being programmed. Again, since bitcell operating depletion mode, meaning always regardless gate voltage, high voltage applied bitline, which case programming, over-erased bitcell will pull bitline down. Since onboard circuits that generate bitline voltage have limited current supply capability designed normal operation, pull down presented over-erased bitcell will drop bitline voltage suppress program operation point failure. From this explanation, seen that bitcell must carefully manage erase operation, erase algorithm must carefully tailored address these issues. Data disturb conditions also exist with FLASH bitcell both wordline bitline conditions. Again, program erase operations must carefully designed controlled avoid unintentional changes data other sections array.
Freescale Semiconductor, Inc.
General Topics Related
this point, information this application note described operation non-volatile memory devices provided detailed explanation operation technologies found Motorola products today. However, some items have been covered that general operation. final topics covered program erase endurance data retention. This discussion provides overview operation bitcell impact these parameters. Very high voltages utilized perform program erase operations been seen repeatedly each technologies
AN1837 More Information This Product, www.freescale.com MOTOROLA
Application Note General Topics Related
that have been covered here. High voltage transistors utilized generation switching these high voltages, these transistors specifically developed this purpose withstand these conditions extended periods. bitcell also developed withstand these stresses operating limits that inherent operation. principal program erase mechanisms that have been discussed, Fowler-Nordheim tunneling, present significant stress onto bitcell.
Freescale Semiconductor, Inc.
challenge arises because program erase operations constrained with respect long operation allowed take. Since relatively fast program erase desired, tunnel oxide beneath floating gate needs relatively thin. However, thinner oxide becomes, electric field increases strength across oxide hence higher stress. terms actual operation, this translates each program erase event degrading oxide very small amount. single operation will result failure bitcell, cumulative effect bitcell program erase operations ultimately will reach point failure. failing event very subtle will always catastrophic hard failure which bitcell ceases able program erase. example, degradation bitcell operation result program erase times needing longer change data state bitcell. Another case might that bitcell disturb characteristics degrade point where longer-than-normal program event could result data being inadvertently altered within array. These kinds cases understanding their behavior important during development cycle given technology. behavior array must understood across entire operating life product specified. Therefore, quite common array perform much better during early stages life cycle when compared maximum minimum limits specification. reason this account change behavior performance result program erase events over course normal operation still enable bitcell operate life. specific example this program time. common observe that array will program faster than stated values specification
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Freescale Semiconductor, Inc. Application Note
during early life product. However, unit cycled, program performance might slowly degrade time reaches upper limit cycling array program time might very close specified value. Because this, customer should strictly observe implement specified values become aggressive based early life product observations. This kind practice will result performance issues application later life product have serious consequences. Data retention performance another critical characteristic array performance. There obvious expectation that data programmed into array will remain there whether array programmed time upper limit cycles allowed. specifications operation array play major role data retention product through life cycle. Subjecting part higher-than-specified voltages, such VPP, performing program erase operations outside specification, result overstressing bitcells that could effect data retention product. This another parameter that demonstrate very good performance early phases life used outside defined specification result serious degradation ultimately failure.
Freescale Semiconductor, Inc.
Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters which provided Motorola data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. Motorola registered trademarks Motorola, Inc. Motorola, Inc. Equal Opportunity/Affirmative Action Employer.
reach USA/EUROPE/Locations Listed: Motorola Literature Distribution, P.O. 5405, Denver, Colorado 80217, 1-303-675-2140 1-800-441-2447. Customer Focus Center, 1-800-521-6274 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu, Minato-ku, Tokyo, 106-8573 Japan. 81-3-3440-8573 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, King Street, Industrial Estate, N.T., Hong Kong. 852-26668334 MfaxTM, Motorola Back System: RMFAX0@email.sps.mot.com; http://sps.motorola.com/mfax/; TOUCHTONE, 1-602-244-6609; Canada ONLY, 1-800-774-1848 HOME PAGE: http://motorola.com/sps/ Mfax trademark Motorola, Inc.
Motorola, Inc., 2000
AN1837/D More Information This Product, www.freescale.com
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