AN1798 Timing Requirements Stuart Robb East Kilbride, Scotla

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

AN1798 Timing Requirements Stuart Robb East Kilbride, Scotla

Datasheet Thumbnail

Top Searches for this datasheet

Order this document AN1798/D
AN1798
Timing Requirements
Stuart Robb East Kilbride, Scotland.
Freescale Semiconductor, Inc.
Introduction
Controller Area Network (CAN) serial, asynchronous, multi-master communication protocol connecting electronic control modules automotive industrial applications. feature protocol that rate, sample point number samples programmable. This gives system engineer opportunity optimise performance network given application. This paper examines relationship constraints between timing parameters, reference oscillator tolerance, various signal propagation delays system.
Timing Overview Structure
Nominal Rate network uniform throughout network given
where tNBT Nominal Time. defined [1], divided into four separate non-overlapping time segments called SYNC_SEG, PROP_SEG, PHASE_SEG1 PHASE_SEG2. These illustrated Figure
Motorola, Inc., 1999
More Information This Product, www.freescale.com
AN1798 Rev.
Application Note
SYNC_SEG
PROP_SEG
PHASE_SEG1
PHASE_SEG2
Sample Point
Figure Segments sample point indicated Figure position actual sample point single sample selected. three samples selected, sample point indicated Figure marks position final sample. period Nominal Time (NBT) segment durations:
Freescale Semiconductor, Inc.
SYNC_SEG PROP_SEG PHASE_SEG1 PHASE_SEG2
Each these segments integer multiple unit time called Time Quantum, duration Time Quantum equal period system clock, which derived from microcontroller (MCU) system clock oscillator programmable prescaler, called Baud Rate Prescaler.
scillator ystem Clock Baud Rate Prescaler (Programmable)
System Clock
Period
PROP_SEG SYNC_SEG
PHASE_SEG
PHASE_SEG
Sample Point(s)
Figure Relationship between System Clock Period
AN1798
More Information This Product, www.freescale.com
MOTOROLA
Timing Overview Structure
duration synchronisation segment, SYNC_SEG, programmable fixed Time Quantum. duration other segments programmable, either individually with values, tSEG1 tSEG2 where:
SEG1 PROP_SEG PHASE_SEG1 SEG2 PHASE_SEG2
Freescale Semiconductor, Inc.
duration propagation segment PROP_SEG between Time Quanta. duration segment PHASE_SEG1 between Time Quanta sample selected between Time Quanta three samples selected. three samples chosen, most frequently sampled value taken value. duration segment PHASE_SEG2 must equal PHASE_SEG1, unless PHASE_SEG1 less than Information Processing Time (IPT), which case PHASE_SEG2 must equal Information Processing Time. This summarised Table
Segment SYNC_SEG PROP_SEG PHASE_SEG1 PHASE_SEG2
Duration tSYNC_SEG tPROP_SEG tPHASE_SEG1 tPHASE_SEG2 MAX(IPT, tPHASE_SEG1)
Table Note: function MAX( returns larger arguments. Information Processing Time equal Time Quanta, except following circumstances [2]: TOUCAN Module: Baud Rate Prescaler (MCU system clock equals system clock.) MCAN Module: samples selected.
From Table would appear that minimum number Time Quanta However, many controllers require minimum Time Quanta bit, stipulated [1]. maximum number Time Quanta
AN1798 MOTOROLA
More Information This Product, www.freescale.com
Application Note Synchronisation Segment
each node, nominal start each beginning SYNC_SEG segment. nodes that transmitting, value transmitted from beginning SYNC_SEG segment. receiving nodes, start received expected occur during SYNC_SEG segment. propagation delay transmitted signal through physical interface along itself, SYNC_SEG segment receiving nodes will delayed with respect SYNC_SEG segment transmitting node(s). This illustrated Figure actual delay will vary depending distance between transmitting receiving nodes being considered.
Freescale Semiconductor, Inc.
Propagation Segment
existence propagation delay segment, PROP_SEG, fact that protocol allows non-destructive arbitration between nodes contending access bus, requirement in-frame acknowledgement. case non-destructive arbitration, more than node transmitting during arbitration field. Each transmitting node samples data from order determine whether arbitration, also receive arbitration field case loses arbitration. When each node samples each bit, value sampled must logical superposition values transmitted each nodes arbitrating access. case acknowledge field, transmitting node transmits recessive expects receive dominant bit, i.e. dominant value must sampled sample point(s). propagation delay segment, PROP_SEG, exists delay earliest possible sample node until transmitted values from transmitting nodes have reached nodes.
Node
SYNC_SEG
PROP_SEG tProp(B,A)
PHASE_SEG1 PHASE_SEG2
tProp(A,B)
Node
SYNC_SEG
PROP_SEG
PHASE_SEG1 PHASE_SEG2
Figure Propagation delay between nodes
AN1798
More Information This Product, www.freescale.com
MOTOROLA
Timing Overview Synchronisation
Figure shows propagation delay between nodes, shows that value transmitted Node received Node after time tProp(A,B), value transmitted Node received Node after time tProp(B,A), before Node propagation segment, thus ensuring that Node will correctly sample value. Node will also correctly sample value, even although Node sample point lies beyond Node time, because propagation delay between Node Node Time tProp(A,B) consists propagation delay through Node driver plus propagation delay along from Node Node plus propagation delay through Node receiver:
Freescale Semiconductor, Inc.
Prop(A,B) Tx(A) Bus(A,B) Rx(B) Synchronisation
nodes network must synchronised while receiving transmission, i.e. beginning each received must occur during each nodes SYNC_SEG segment. This achieved means synchronisation. Synchronisation required phase errors between nodes which arise nodes having slightly different oscillator frequencies, changes propagation delay when different node starts transmitting. types synchronisation defined, hard synchronisation re-synchronisation. Hard synchronisation performed only beginning message frame, when every node aligns SYNC_SEG current time recessive dominant edge transmitted Start-Of-Frame bit. Re-synchronisation subsequently performed during remainder message frame, whenever change value from recessive dominant occurs outside expected SYNC_SEG segment. nodes which transmitting, value transmitted start transmitting nodes SYNC_SEG segment, value transmitted until PHASE_SEG2 segment. nodes which active receive data (including transmitting nodes) changes value expected occur during SYNC_SEG segment. recessive dominant value transition detected outside receiving nodes SYNC_SEG segment, then that node will re-synchronise edge. recessive dominant value transition detected after SYNC_SEG segment, before sample point, then this interpreted late edge. node will attempt re-synchronise stream increasing duration PHASE_SEG1 segment current number Time Quanta which edge late, re-synchronisation jump width limit. effect this
AN1798 MOTOROLA
More Information This Product, www.freescale.com
Application Note
that next sample point delayed until programmed number Time Quanta after actual edge required delay does exceed re-synchronisation jump width limit). Conversely, recessive dominant value transition detected after sample point before SYNC_SEG segment next bit, then this interpreted early bit. node will attempt re-synchronise stream decreasing duration PHASE_SEG2 segment current number Time Quanta which edge early, re-synchronisation jump width limit. Effectively, SYNC_SEG segment next begins immediately edge early more than re-synchronisation jump width limit). number Time Quanta which period extended shortened re-synchronisation limited programmable value called re-synchronisation jump width (RJW SJW). re-synchronisation jump width must programmed valid value. re-synchronisation jump width cannot exceed Time Quanta also must exceed number Time Quanta PHASE_SEG1 segment. minimum value re-synchronisation jump width Time Quantum. order minimise maximum time between recessive dominant edges, hence maximise number opportunities resynchronisation, protocol uses stuffing. After every occurrence five consecutive bits equal value, extra stuff opposite value inserted into stream. stuffing implemented Data Frames Remote Frames, from Start-Of-Frame Cyclic Redundancy Check field.
Freescale Semiconductor, Inc.
Oscillator Tolerance
Typically, system clock each node will derived from different oscillator. actual system clock frequency each node, hence actual time, will subject tolerance. Ageing variations ambient temperature will also affect initial tolerance. system clock tolerance defined relative tolerance:
where actual frequency nominal frequency.
AN1798
More Information This Product, www.freescale.com
MOTOROLA
Timing Requirements Propagation Delay
Timing Requirements
ensure effective communication, minimum requirement network that nodes, each opposite ends network with largest propagation delay between them, each having system clock frequency opposite limits specified frequency tolerance, must able correctly receive decode every message transmitted network. This requires that nodes sample correct value each bit.
Freescale Semiconductor, Inc.
Propagation Delay
minimum time propagation delay segment ensure correct sampling values given
PROP_SEG Prop(A,B) Prop(B,A)
where nodes opposite ends network, i.e. propagation delay maximum between nodes From equation (5), this gives:
PROP_SEG
where tBus propagation delay signal along longest length between nodes, propagation delay transmitter part physical interface propagation delay receiver part physical interface. propagation delay transmitters receivers network uniform, maximum delay values should used equation (8). minimum number Time Quantum that must allocated PROP_SEG segment therefore:
PROP_SEG PROP_SEG ROUND_UP
where function ROUND_UP( returns argument rounded next integer value.
AN1798 MOTOROLA
More Information This Product, www.freescale.com
Application Note Oscillator Tolerance Requirements
absence errors example, electrical disturbances, stuffing guarantees maximum periods between re-synchronisation edges dominant bits followed recessive bits will then followed dominant bit). This represents worst case condition accumulation phase error during normal communication. accumulated phase error must compensated re-synchronisation following recessive dominant edge therefore accumulated phase error must less than programmed Re-synchronisation Jump Width (tRJW). accumulated phase error tolerance system clock, this requirement expressed [1]: (10)
Freescale Semiconductor, Inc.
Real systems must operate presence electrical noise which induce errors bus. event error being detected, Error Flag transmitted bus. case local error, only node that detects error will transmit Error Flag. other nodes receive Error Flag then transmit their Error Flags echo. error global, nodes will detect within same time will therefore transmit Error Flags simultaneously. node therefore differentiate between local error global error detecting whether there echo after Error Flag. This requires that node correctly sample first after transmitting Error Flag. Error Flag from Error Active node consists dominant bits, there could dominant bits before Error Flag, example, error stuff error. node must therefore correctly sample 13th after last re-synchronisation. This expressed [1]: PHASE_SEG2 PHASE_SEG1 PHASE_SEG2 (11) where function MIN( returns smaller arguments. Thus there clock tolerance requirements which must satisfied. should noted that high rates (small Nominal Time), clock tolerance specified over relatively short time: tNBT case equation (10), tNBT tPHASE_SEG2 case Equation (11). This important systems which derive clock from Phase Locked Loop circuit which relative accuracy decreases over short time periods output jitter.
AN1798
More Information This Product, www.freescale.com
MOTOROLA
Selection Timing Values Step-by-Step Calculation Timing Parameters
Selection Timing Values
selection timing values involves consideration various fundamental system parameters. requirement PROP_SEG value imposes trade-off between maximum achievable rate maximum propagation delay, length characteristics driver circuit. maximum achievable rate also influenced tolerance clock source. highest rate only achieved with short length, fast driver circuit high frequency high tolerance clock source. many systems, length will least variable system parameter which will impose fundamental limit rate. However actual rate chosen involve trade-off with other system constraints, such cost.
Freescale Semiconductor, Inc.
Step-by-Step Calculation Timing Parameters
following steps provide method determining optimum timing parameters which satisfy requirements proper sampling. Step Determine minimum permissible time PROP_SEG segment. Obtain maximum propagation delay physical interface both transmitter receiver from manufacturers data sheet. Calculate propagation delay multiplying maximum length signal propagation delay cable. these values calculate tPROP_SEG using equation (8). Choose System Clock Frequency system clock derived from system clock oscillator, possible system clock frequencies will limited whole fractions system clock oscillator prescaler. system clock chosen that desired Nominal Time (NBT) integer number time quanta (CAN system clock periods) from Calculate PROP_SEG duration. From equation (9), number time quanta required PROP_SEG segment calculated. result greater than back Step choose lower system clock frequency.
Step
Step
AN1798 MOTOROLA
More Information This Product, www.freescale.com
Application Note
Step Determine PHASE_SEG1, PHASE_SEG2 From number time quanta obtained Step subtract PROP_SEG value calculated Step subtract SYNC_SEG. remaining number less than then back Step select higher system clock frequency. remaining number number greater than then PROP_SEG value recalculate. remaining number equal then PHASE_SEG1 PHASE_SEG2 only sample chosen. Otherwise divide remaining number assign result PHASE_SEG1 PHASE_SEG2. Determine chosen smaller PHASE_SEG1 Calculate required oscillator tolerance from equations (10) (11). case PHASE_SEG1 recommended repeat steps with larger value prescaler, i.e. smaller period, this result reduced oscillator tolerance requirement. Conversely, PHASE_SEG1 recommended repeat steps with smaller value prescaler, long PROP_SEG this result reduced oscillator tolerance requirement. prescaler already equal reduced oscillator tolerance still required, only option consider using higher frequency prescaler clock source.
Freescale Semiconductor, Inc.
Step Step
Example
Calculate segments following system constraints: rate second length propagation delay 10-9 sm-1 Physical Interface (PCA82C250) transmitter plus receiver propagation delay 150ns oscillator frequency 8MHz Step Physical delay 10-9 100ns
PROP_SEG 100ns 150ns 500ns
AN1798
More Information This Product, www.freescale.com
MOTOROLA
Selection Timing Values Example
Step
prescaler value gives system clock 8MHz Time Quantum 125ns. This will give 1000 time quanta bit. -PROP_SEG ROUND_UP 500ns ROUND_UP 125ns From time quanta bit, subtract PROP_SEG SYNC_SEG. This leaves which absolute minimum, PHASE_SEG1 PHASE_SEG2 smaller PHASE_SEG1, this case From equation (10): 0.00625 From equation (11):
Step
Step
Freescale Semiconductor, Inc.
Step Step
PHASE_SEG1 ,PHASE_SEG2 0.00490 PHASE_SEG2 required oscillator tolerance smaller these values, i.e. 0.0049 (0.49%) over period 12.75µs (12.75 periods). this case prescaler reduction oscillator tolerance made without using higher oscillator frequency. Also PHASE_SEG1 only sample possible. summary: Prescaler Nominal Time PROP_SEG PHASE_SEG1 PHASE_SEG2 Oscillator tolerance 0.49%
AN1798 MOTOROLA
More Information This Product, www.freescale.com
Application Note Example
Calculate segments following system constraints: rate 125k second length propagation delay 10-9 sm-1 Physical Interface (PCA82C250) transmitter plus receiver propagation delay 150ns oscillator frequency 8MHz Step Physical delay 10-9 250ns
Freescale Semiconductor, Inc.
PROP_SEG 250ns 150ns 800ns
Step prescaler value gives system clock 2MHz Time Quantum 500ns. This will give 8000 time quanta bit. PROP_SEG ROUND_UP 800ns ROUND_UP 500ns From time quanta bit, subtract PROP_SEG SYNC_SEG. This leaves Therefore PHASE_SEG1 PHASE_SEG2 remaining added PROP_SEG, i.e. PROP_SEG lesser PHASE_SEG1, this case From equation (10): 0.0125 From equation (11): PHASE_SEG1 ,PHASE_SEG2 0.01485 PHASE_SEG2 required oscillator tolerance smaller these values, i.e. 0.0125 (1.25%). PHASE_SEG1 repeat Steps with larger prescaler value:
Step
Step
Step Step
AN1798
More Information This Product, www.freescale.com
MOTOROLA
Selection Timing Values Example
Step
prescaler value gives system clock 1MHz Time Quantum 1000ns. This will give 8000 1000 time quanta bit. 800ns PROP_SEG ROUND_UP ROUND_UP 1000ns From time quanta bit, subtract PROP_SEG SYNC_SEG. This leaves Therefore PHASE_SEG1 PHASE_SEG2 smaller PHASE_SEG1, this case From equation (10): 0.01875 From equation (11):
Step
Step
Freescale Semiconductor, Inc.
Step Step
PHASE_SEG1 ,PHASE_SEG2 0.01485 PHASE_SEG2 required oscillator tolerance smaller these values, i.e. 0.01485 (1.485%) over 101µs (12.625 times). This significant increase oscillator tolerance requirement, chosen values are: Prescaler Nominal Time PROP_SEG PHASE_SEG1 PHASE_SEG2 Oscillator tolerance 1.485%
AN1798 MOTOROLA
More Information This Product, www.freescale.com
References
References
Bosch Specification Version 1990 Motorola BCANPSV2.0/D
Freescale Semiconductor, Inc.
AN1798 MOTOROLA
More Information This Product, www.freescale.com
Freescale Semiconductor, Inc.
AN1798 MOTOROLA
More Information This Product, www.freescale.com
Freescale Semiconductor, Inc.
Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters which provided Motorola data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. Motorola registered trademarks Motorola, Inc. Motorola, Inc. Equal Opportunity/Affirmative Action Employer.
reach USA/EUROPE/Locations Listed: Motorola Literature Distribution, P.O. 5405, Denver, Colorado 80217, 1-800-441-2447 1-303-675-2140. Customer Focus Center, 1-800-521-6274 JAPAN: Motorola Japan Ltd.: SPD, Strategic Planning Office, 141, 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan. 03-5487-8488 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd., Ping Industrial Park, Ting Road, N.T., Hong Kong. 852-26629298 HOME PAGE: http://motorola.com/sps/
Motorola, Inc., 1999
More Information This Product, www.freescale.com
AN1798/D

AN1798 Timing Requirements Stuart Robb East Kilbride, Scotla

Top Searches for this datasheet

Other recent searches