AN1776 Freescale Semiconductor, Inc. Stereo Audio Transmissi
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AN1776
Freescale Semiconductor, Inc.
Stereo Audio Transmission Over Using Motorola MC68376 With TouCAN Module
Allan Dobbin Transportation Systems Group East Kilbride, Scotland 1.0, 10th July 1998
Introduction
main purpose this application note provide reader with working knowledge Motorola TouCAN module. non-typical application stereo-audio transmission used example. Motorola MC68376 microcontroller with TouCAN used QADC QSPI modules demonstrated also. source code TouCAN module audio transfer provided this example, MC68376 samples stereo audio data using QADC. resultant sampled data transmitted onto TouCAN module received second 68376 also connected bus. receiving uses small internal buffer temporary storage before outputting audio data QSPI external reproduction analogue signal. MCUs queuing mechanism QADC QSPI minimize overhead.
Motorola, Inc., 1998
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Contents
Contents
Introduction Contents Summary Physical Layer Message Transfer Monitoring Arbitration Errors Fault Confinement Timing Motorola Modules
Freescale Semiconductor, Inc.
MC68376 Overview CPU32. QADC 7.5K SRAM ROM. CTM. TouCAN. 4.9.1 Message Buffers 4.9.2 TouCAN Timing 4.9.3 Configuration 4.9.4 Interrupts 4.9.5 Message Filters 4.9.6 Error Counters 4.9.7 TouCAN Initialization Audio Transfer Audio Input 5.1.1 Digital Audio Sampling. 5.1.2 QADC TouCAN Transfer Audio Output 5.2.1 Digital Analogue Converter 5.2.2 QSPI Operation 5.2.3 QSPI Data Output Timing 5.2.4 QSPI Data Updating Mechanism
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5.2.5 5.2.6 5.2.7 Receiving Data from Synchronizing Audio Output Input Altering QSPI Output Rate Buffer Size
Hardware Design Audio Input Hardware Audio Output Hardware. 6.2.1 Digital Signals 6.2.2 Analogue Signals Hardware
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Software File Summary Generic TouCAN Routines file `toucan.c' 7.2.1 toucan_init_global 7.2.2 toucan_MB_off. 7.2.3 toucan_bus_on 7.2.4 set_ip Audio Input file `ain.c' 7.3.1 ain_toucan_ init 7.3.2 ain_QADC_ init 7.3.3 ain_Q2_ISR 7.3.4 ain_MB4_ISR. 7.3.5 Audio-in main routine Audio Output file `aout.c' 7.4.1 aout_toucan_init. 7.4.2 aout_SPI_init 7.4.3 testSPIspeed 7.4.4 aout_MB6_ 7.4.5 Audio-out main routine. Source Listings 7.5.1 ain.c 7.5.2 aout.c 7.5.3 toucan.c 7.5.4 audio.h 7.5.5 regs.h 7.5.6 toucan1.h References
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Summary Physical Layer
Summary
Controller Area Network (CAN) originally developed BOSCH Gmbh serial communications protocol pass information between controllers automotive network thus reduce growing complexity wiring harness modern design. protocol include prioritization messages, flexible configuration, multicast reception, multiple masters, error detection, fault confinement automatic retransmission.
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Over recent years there been steady growth number applications using interface. already widely used Automotive industry Europe increasingly USA. automotive electronics, engine control units, anti-lock braking sensors connected using high-speed with bit-rates Mbit/s whereas electric windows vehicle lighting connected speed with data transmission rates between kbit/s. Other applications include industrial nautical equipment, medical apparatus, elevator controls even entire manufacturing plants interface intelligent control systems communicating real time using networks. original specification provided identifier (ID) bits. updated specification provides either bits larger identifier range using bits. 11-bit format referred standard format governed standard 1.2/2.0A, whilst 29-bit referred extended format. standard 2.0B caters both 29-bit ID's. majority current applications standard 11-bit identifier greater throughput i.e. smaller field less overhead than 29-bit field. reference full specification.
Physical Layer
physical layer covers transfer data between different nodes network electrical properties. actual physical interface described within specification usually consists two-wire differential with each signal designated CANL CANH. `off' state called recessive `on' state dominant. physical interface designed that more than node drive instant without damage. both dominant recessive bits transmitted onto together, resulting state will dominant. Using wired-AND implementation example, logic would dominant logic would recessive state would input
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Freescale Semiconductor, Inc. Application Note
actual voltage levels that appear defined Bosch specification several different transmission mediums used. Although twisted pair common, others used including optical single wire implementations. Most controller implementing protocol include physical layer drivers, have CMOS transmit receive pins instead. common interface Philips 82C250 transceiver which implements physical layer defined 11898 (CAN standard high speed communications). This used hardware described later this application.
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82C250 outputs nominal voltage levels 3.5V CANH 1.5V CANL dominant state i.e. differential. pins drive during recessive state tied together using termination resistors produce zero differential. transceiver interprets input differential greater than dominant. TouCAN module receive input, CANRx0 transmit outputs, CANTx0 CANTx1. transmit outputs configured full CMOS with positive negative polarity open drain. receive input configured dominant. 68376 device, only CANTx0 CANRx0 bonded pins. TouCAN module described detail next section. maximum speed bus, according standard, Mbit/s. Since arbitration scheme requires that data propagates most remote node back, maximum cable length this transmission rate limited speed propagation) meters. cable length increased lower transmission rates i.e. meters kbit/s. This transmission speed limitation propagation delay described Section Timing.
Message Transfer
Four different frame types possible CAN. remote frame transmitted from node acting receiver request data. This remote frame contains data, does contain type data requesting. error frame transmitted node which detects error. This error frame consists mainly dominant bits which override current message break stuffing rule (described Section 3.3). This forces transmitter abort transmission current message ensures that nodes aware error. overload frame used when node requires delay between reception successive data frames.
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Summary Message Transfer
data frame regular message frame that carries data from transmitter receivers. Under normal operating conditions, data frame predominant, only, frame described more detail. data frame consists several fields shown below.
NOTE:
Data remote frames issued controller after instruction whereas error overload frames usually issued automatically controller independently CPU.
Interframe space
Data Frame
Interframe space
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Start Frame bit)
Control Field bits) Arbitration Field (Extended bits) (Standard bits)
Field bits) Data Field (0-8 bytes)
Frame bits)
Field bits)
Figure Data Frame start frame single dominant start indicates start message from more nodes. arbitration field this contains message plus bit. 11-bit used standard format bits extended format shown Figure extended format additionally contains bits. usually used assign message type i.e. temperature, engine speed, audio left, etc. destination address, however this specified system designer. also used assign priority messages priority discussed more detail section arbitration. (Remote Transmission Request) specifies whether frame data frame remote frame. (Identifier Extension indicates 11-bit 29-bit identifier) (Substitute Remote Request) transmitted recessive extended format frame. control field this field contains 4-bit data length code (DLC) plus reserved bits. specifies many bytes data contained within data frame bytes allowed. Codes permitted. data field data consists between bytes vary length i.e. temperature consist data bytes, whereas audio
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Freescale Semiconductor, Inc. Application Note
consist eight. zero byte message does have uses could used wake-up command, synchronization command request data case remote frame where would recessive). field this consists 15-bit cyclic redundancy sequence which allows nodes perform frame security check detecting errors, plus single recessive used delimiter. sequence derived from preceding fields. field this consists bits slot delimiter. transmitting node sends recessive bits other active node network which receives frame correctly will force first dominant. This acts acknowledgment transmitter that message been successfully transmitted bus. This does necessarily mean that node(s) which message intended received only that least node received active nodes will acknowledge frame whether they have been programmed filter that particular transmitting node does detect dominant acknowledge bit, will repeat transmission frame. frame message indicated "end frame" field which consists seven recessive bits. Interframe space this normally consists intermission period 3-bit times plus idle period. Nodes cannot transmit data frames remote frames during intermission period will recessive during this 3-bit period. idle period arbitrary length nodes will recognize being free during this recessive state. arbitration fields standard extended formats shown Figure
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Summary Monitoring Arbitration
STANDARD Interframe space
Arbitration field
Control Field Data Field
(11bits)
(4bits) Data Field
EXTENDED Interframe space (11bits)
Arbitration field (18bits)
Control Field
(4bits)
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SOF: RTR: DLC: IDE: SRR:
Start Frame Identifier Remote Transmission Request reserved bits Data Length Code Extd. (CAN only) Replacement Std. format (CAN 2.0B)
Figure Standard Extended Arbitration Fields
Monitoring Arbitration
There certain rules that nodes must adhere keeping with protocol standard. These include stuffing, cyclic redundancy check, frame checks acknowledgment process. stuffing ensures that sufficient edges generated synchronization since (non-return-to-zero) coding used after five consecutive equal bits, additional complementary added, stuffed, transmitter. enforce these rules nodes must monitor bus. This means that active nodes network, receivers transmitters alike, will monitor every each message proper conformance protocol. soon violation detected node then those nodes will transmit error frame which consists consecutive dominant bits (except case error passive nodes which transmit recessive error frame Section Errors Fault Confinement). Since this violates stuffing, acts message other nodes that current message corrupt transmission should aborted. This monitoring bits transmitter serves another purpose i.e. arbitration. Since several nodes commence transmission same time, each message's unique within arbitration field used determine wins control bus. process follows: more nodes transmit dominant start same time both successfully monitor correct state bus. They then commence transmission arbitration bits until some point node transmits dominant other transmits recessive. nature physical interface, dominant prevails
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Freescale Semiconductor, Inc. Application Note
unsuccessful node detects this simply backs transmission waits current message before trying arbitration again, participates receiver current transmission. successful node continues transmission unaware that there ever conflict, arbitration, bus. arbitration process allows assignment priority giving highest priority messages numerical dominant system). Generally, high priority assigned rapidly changing data. nodes receiving message must check determine whether there useful data message use. highly integrated controllers (such TouCAN), hardware will provide filtering where mask permits only certain combinations filter through internal receive buffers. Less integrated controllers will provide hardware filtering thus application software will have burden with additional task testing message every message received bus.
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Errors Fault Confinement
Fault confinement possible nodes able distinguish between short disturbances permanent failures. This accomplished 8-bit error counters within each node transmit error counter receive error counter. summary, node will increase receive transmit counter when detects five possible error types (bit error, stuff error, error, form error acknowledgment error) will decrement when completes successful reception transmission. This means that temporary disturbances result small counts that recover back zero, whereas permanent failures result large counts. error counter increases error detected during reception. However first after transmission error flag dominant, which suggests that another node detect this same error, error counter increased error counter always increased error detected while node transmitting. error counter decreased after successful reception error counter decreased after successful transmission. This method incrementing counters ensures that fault local node then only error counters will increment rapidly. node will take three states depending value within error counters follows: error active this regular operational state node occurs when both counts less than 128. this state node participate usual communication. detects errors during
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Summary Timing
communication, indicates this transmitting ERROR ACTIVE FLAG which consists dominant bits therefor blocks current transmission. error passive this state occurs when either counters increment past indicates that there abnormal level errors this node. node still participates transmission reception, forced wait slightly longer after message transmission before initiate message transfer own. This extra delay error passive node known suspend transmission accomplished having node send additional recessive bits frame. This means that error passive node loses arbitration error active node regardless priority their IDs. When error passive node detects error during communication indicates this transmitting ERROR PASSIVE FLAG. This consists recessive bits which will disrupt current transmission (assuming another node transmitter) error turns local error passive node. this state occurs when transmit error count reaches 256. This indicates that node experienced consistent errors whilst transmitting. this state, node switches drivers longer influences bus. node will eventually re-enabled transmission become error-active after detected occurrences consecutive recessive bits which indicate periods inactivity.
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Timing
Nodes connected high frequency clock prescaler least bits which allows division this clock range least period this resulting lower frequency clock time quantum this basic unit measurement timing. transmission period node will multiple these time quanta. Referring Figure each composed four time segments follows: synchronisation segment this fixed size time quanta edge expected within this segment. Each node synchronizes transmitting node ensuring that first edge message lies within this segment. Further resynchronizations performed subsequent edges within message. propagation segment this programmable between time quanta compensates delays network. value must least twice maximum time signal takes propagate between nodes system, i.e.
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Freescale Semiconductor, Inc. Application Note
prop output driver delay line delay input comparator delay output driver input comparator delays dependent interface hardware line delay total length multiplied speed propagation (approx. depends cable used). phase segment pseg1 programmable between time quanta pseg2 will least equal length, usually down minimum minimum value pseg2 required allow node time process value since sampled pseg1. This minimum process time called information processing time node will automatically lengthen pseg1 shorten pseg2 upon detecting edges within message allow resynchronization with transmitting node. amount time quanta these segments altered must greater than resynchronization jump width, RJW, which limited size that pseg1 maximum time quanta. automatic adjusting pseg1 controller required allow each node resynchronise with current transmitter during each recessive dominant transmission. transmitter internal clock that slightly slower than receiver then transition will `late' will occur after sync. seg. within either prop pseg1 segments. this case, pseg1 lengthened compensate. Conversely, transmitter fast then transition will received `early' i.e. before sync. seg, within pseg2 previous time. this case, pseg2 shortened compensate. values assigned segments dependent rate required plus oscillator tolerance each node. Generally, propagation segment minimum amount time quanta that allow twice worst case signal propagation delay. maximum rates required, then pseg1 small with respect prop. seg. maximum resynchronization required allow tolerance clock oscillators then pseg1 large relation prop. seg. value Usually maximum value i.e. equal pseg1 maximum Refer Section 4.9.2 example TouCAN timing set-up.
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Summary Motorola Modules
nominal time -RJW sync. prop. seg. phase seg. +RJW phase seg. max(IP, pseg1)
sampling point
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sample mode only
Figure Timing
Motorola Modules
Motorola currently offer three different modules support each their 32-bit microcontroller families i.e. MCAN, MSCAN TouCAN. MCAN provides lowest performance highest overhead three available HC05 family. buffers provided. MSCAN higher level integration provides three buffers buffers. This module available slightly different versions HC08 HC12 families. MSCAN12 version 32-bit filtering which double that MSCAN08. TouCAN offers highest performance currently available HC16, 683xx PowerPC MPC500 families. provides message buffers each configurable 32-bit filter masks. TouCAN operation covered more detail Section 4.9.
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Freescale Semiconductor, Inc. Application Note MC68376 Overview
Motorola MC68376 member highly integrated 683xx modular family microcontrollers where modular building blocks shared throughout family connected internally inter-module (IMB). 68376 comes package consists several modules described following sections. modules described briefly with emphasis TouCAN module. full description refer reference
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CPU32
32-bit architecture based 68020 processor. operate 8-bit, 16-bit 32-bit operands, however only 16-bit data exists outside CPU. Contains eight 32-bit data registers, eight 32-bit address registers, 32-bit stack program counters plus 8-bit condition code register. Features built-in background debugging mode (BDM) which used debugging testing this application. CPU32 provides seven levels interrupt priority exception vectors. 10-bit analogue digital converter with direct input channels expandable multiplexed mode conversion time around micro-seconds. distinctive feature this queuing mechanism. does have intervene after every analogue conversion, instead queue conversion commands utilized. Each conversion command corresponding result word register which stores resulting 10-bit digital conversion. system makes extensive this queuing mechanism interrupts that there minimal overhead during audio sampling. Queued Serial Module consists independent ports (Serial Communications Interface) QSPI (Queued Serial Peripheral Interface). standard asynchronous serial interface, UART used system. QSPI synchronous interface similar Motorola used 8-bit micros, with important additions. first these sixteen word queue offering similar advantages queuing mechanism QADC. table sixteen serial transfer commands used which corresponding table sixteen receive transmit data registers. this queue allows reduction overhead since sixteen transfers without intervention possible. second addition port four (Programmable Chip Selects). Each sixteen queued command words activates required serial transfers. audio system makes both queue will described audio section.
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MC68376 Overview 7.5K SRAM
7.5K SRAM
There blocks byte block SRAM general purpose plus 3.5K byte block either general microcode emulation. internal SRAM sufficient application, additional external memory required. bytes masked available high volume users. most applications this used initialization start routines. essentially internal co-processor with sixteen dedicated input/output channels control timer based functions. This module very useful engine management motor control applications many other general purpose uses i.e. additional (UART) ports channels. required application. configurable timer module with 16-bit modulus counters, 16-bit free running counter, four double action submodules four pulse width modulation submodules provides additional timer counter functionality. required application. System Integration Module includes external interface, chip selects, system protection block with software watchdog, periodic interrupt timer, monitor generated system clock. TouCAN module communication controller that implements protocol maximum possible transfer rates 1Mbit/s. Both standard (11-bit identifier) extended (29-bit identifier) message formats supported specified protocol specification 2.0B. TouCAN module includes following features: message buffers receiving transmitting data frames. Programmable rate 1Mbit/s. serial message buffers double buffering both received transmitted data. 16-bit free-running timer provides time-stamp. Supports 2.0B both standard extended formats. overhead reduced implementing local fields within each message buffer plus masking using three 32-bit mask registers. Automatic reply mechanism available remote request frames. maskable interrupt sources. power sleep mode with wake-up mechanism.
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C
TouCAN
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4.9.1 Message Buffers TouCAN provides sixteen message buffers (MBs), each which assigned either transmit receive buffer each optionally generate interrupt after successful completion data transfer. Each buffer contains eight 16-bit registers which take slightly different formats depending whether standard extended format selected shown.
ID{28-18] DATA BYTE DATA BYTE DATA BYTE DATA BYTE TIME STAMP ID{28-18]
CODE
LENGTH
ID{17-15]
ID{14-0] DATA BYTE DATA BYTE DATA BYTE DATA BYTE RESERVED
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Extended Identifier TIME STAMP Standard Identifier
Figure TouCAN Message Buffer Structures code field initially written define operation i.e. inactive, receiver, transmitter, remote request, etc. updated TouCAN after activity indicate whether successful operation occurred. time stamp copied from free-running timer TouCAN indicate when reception transmission occurred. configured transmission, writes length data fields transmitted within data frame, whereas receive MBs, TouCAN writes these fields they were received from bus. field written including select either standard extended format both transmission reception. field transmitted written, whereas field combined with receive mask registers resulting filter used check comparison received frames. match made received frame, will then copied into MB's field, regardless contents mask register. code field initialized after power-up reset must manually inactive receiver (0000) inactive transmitter
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MC68376 Overview TouCAN
(1000) CPU. Once TouCAN registers have been initialized message buffers have their data fields configured, code active receiver (0100) active transmitter (1100 alternatively remote modes selected transmission. remote modes remote transmission request (1100 which means buffer transmits only request data, remote response (1010) which code transmit data only reception matching from frame. After transmission reception data bus, TouCAN will update code field corresponding IFLAG register will set.
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Reading control/status word receive will lock that that entire contents read without serial message buffer overwriting data. unlocked reading control/status word another reading 16-bit timer. When polling completion data transfer, IFLAG register should used code field within CONTROL/STATUS register this could lock prevent message from being transferred. length field specifies many data bytes contained within message zero eight. transmit buffers writes this value, whereas receive buffers TouCAN copies this field from field within message. During reception transmission data, time stamp captured when field appears bus. captured time stamp value transferred from TouCAN's free-running counter relevant only when entire message frame been successfully transferred. standard format used, 16-bits time stamp used, extended format only upper 8-bits timer used. ID_HIGH ID_LOW registers contain arbitration field just appears bus, i.e. SRR, bits embedded within 29-bit This layout bits slightly different standard extended formats. user must careful when writing these registers that value intended. RTR, bits specified specification i.e. remote frame request, extended format extended format should always data registers contain eight bytes data specified length field. with length field, these registers written transferred TouCAN transmit buffers, written received from receive buffers.
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Freescale Semiconductor, Inc. Application Note
TouCAN uses double buffering scheme where shadow serial message buffers employed temporary buffering data. This allows TouCAN buffer messages before transferring them matching message buffer. These message buffers accessible CPU. 4.9.2 TouCAN Timing TouCAN timing follows rules defined Section 3.5. 8-bit prescaler used divide system clock obtain serial clock TouCAN use. PRESDIV register used select this divide ratio resulting clock called S-clock, whose period time quanta. propagation, phase phase segment values programming PROPSEG[2:0], PSEG1[2:1] PSEG2[2:0] bits within CANCTRL1 CANCTRL2 registers. Since synchronous segment size always other segments more than value programmed register field, time length will time PROPSEG PSEG1 PSEG2 time quanta i.e. bits/s rate PRESDIV PROPSEG PWSEG1 PSEG2 resynchronization jump width programming RJW[1:0] field CANCTRL2 should greater than PSEG1. example, system clock frequency 20MHz maximum rate 1Mbit/s required then possible set-up follows: PRESDIV i.e. prescaler divide rate S-clock 10MHz, time quanta 100ns. PROPSEG[2:0] propagation segment time quanta. PSEG1[2:0] phase segment time quanta. PSEG2[2:0] phase segment time quanta. RJW[2:0] i.e. resynchronization time quanta. This allows propagation time 100ns i.e. 500ns which sufficient most transmission circuits. cannot bigger than PSEG1, limited 200ns. many systems, instance those with lengths less than 10m, PROPSEG could made smaller, allowing PSEG1 PSEG2 thus increased. Larger will compensate less accurate oscillators systems.
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MC68376 Overview TouCAN
There some restrictions that must observed when setting TouCAN timing. S-clock equal Fsys, i.e. PRESDIV then PSEG2[2:0] must least otherwise PSEG2[2:0] must least time should least system clocks length guarantee correct operation. This should pose problems most cases system clock will least 16MHz which means there will always more than system clocks time since maximum rate 1Mbit/s. 4.9.3 Configuration RXMODE[1:0] TXMODE[1:0] CANCTRL0 register allow receive transmit pins configured independently each other. 68376, only CANRX0 available RXMODE1 used. Clearing RXMODE0 defines logic CANRX0 dominant, which will case when using most transceiver ICs. However, custom designed interface circuits, either setting possible. 68376, only CANTX0 available following settings possible TXMODE[1:0]:
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drives dominant recessive. drives dominant recessive. drives dominant open drain recessive.
usual setting when using standard transceiver 4.9.4 Interrupts TouCAN sources interrupt, each MBs, off, error wake interrupts, enabled setting relevant bits CANMCR (WAKEMSK), CANCTRL0 (BOFFMSK ERRMSK) IMASK registers. Each these sources have individual enable bits status flags share common interrupt arbitration request levels. interrupt mechanism TouCAN similar other modules 683xx family. interrupt arbitration field (IARB[3:0] within CANMCR) take values through reset non-zero value must assigned otherwise will process spurious interrupt. interrupt priority level using ILCAN[2:0]. disables TouCAN interrupts, while highest priority. field within status register must value lower than ILCAN enable interrupts this level. CPU32 allows nested interrupts current
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Freescale Semiconductor, Inc. Application Note
interrupt increases field level equal interrupt priority level. This means that subsequent interrupts higher level will override current interrupt whereas lower equal requests disabled until afterwards. Finally, vector base address defined writing IVBA[2:0] other interrupts will occupy preceding vector entries vector table. location interrupt vectors calculated shifting IVBA value twice, adding offset then adding offset times buffer number shown following examples:
IVBA (vector 64), $0000,
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vector address
(IVBA[7:0] MB#) $100 $0000 $0100
IVBA (vector 96), $1000, vector address (IVBA[7:0] MB#) $180 $1000 $1188
4.9.5 Message Filters
There three 32-bit mask filter registers TouCAN which used make some bits within message buffers `don't care' bits. masks relevant receive buffers only. RXGMSK provides global mask MB0-13. RX14MSK RX15MSK used unique masks MB14 MB15. default state these registers after reset `1's which means that bits within message must match bits active receive message buffer before message accepted. user write these bits allow bits message ignored. bits mask register then active receive buffer will accept messages correct format (i.e. standard extended) from bus. mask register corresponds within arbitration field always `1', thus receive buffer cannot configured filter both standard extended formats. node accept messages then minimum message buffers must used extended other standard frames. Bits mask register correspond bits message. These bits always never compared corresponding with received frame. Although mask filters allow reception data frame with different field that originally written into MB's field, actual received will copied into This means within altered reception Mask filters used only data frames remote frames must match MB's field exactly.
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MC68376 Overview TouCAN
4.9.6 Error Counters
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described Section 3.4, fault confinement achieved using 8-bit error counters. TouCAN, these RXECTR TXECTR registers. These error counters automatically increased TouCAN detection errors decrement completion successful reception transmission. described Section node status changes from error active error passive either counter exceeds changes status error counter reaches 256. status node indicated FCS[1:0] bits ESTAT register generation interrupts enabled after detection error transition state. ESTAT register also sets either warning flags, TXWARN RXWARN, either error counters exceed this indicates heavily disturbed bus. After TouCAN reset (power-up, hard reset soft reset), control registers default their reset state message buffers initialized. TouCAN module will attempt communicate with this stage HALT within CANMCR register allowing access TouCAN registers. typical initialization procedure follows: Initialize configuration timings using following registers: CANCTRL0: RXMODE [1:0], TXMODE[1:0] define dominant recessive levels select CMOS open drain drive. CANCTRL1: SAMP, PROPSEG[2:0] select samples propagation delay between time quanta. PRESDIV select many clocks (1-256) make TouCAN time quanta. CANCTRL2: RJW[1:0], PSEG1[2:0], PSEG2[2:0] select phase segment delays between time quanta re-synchronize with time quanta. Adhere rules timing section. Make message buffers inactive writing their control field 0000. activated Rx/Tx they will begin arbitration process immediately TouCAN synchronized with (after step left inactive until ready communication. either case, following steps taken activate communication when required: Initialize fields required writing ID_HIGH ID_LOW registers necessary values, taking care embed SRR, bits within 29-bit identifier. used transmit, write data bytes length field. Finally, rewrite control field make active (0100) active (1100), remote codes remote frame set-up.
4.9.7 TouCAN Initialization
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Freescale Semiconductor, Inc. Application Note
Write 32-bit mask filter registers RXGMSK, RX14MSK RX15MSK filter messages with required with field take care embed three non-ID bits within filter. These registers default `1's each fields which mean that every compared with field message buffer. Also, corresponding (bit always which means that cannot masked therefor cannot configured receive both standard extended format frames. Refer section interrupts description interrupt operation. following registers effect interrupts: CANMCR: IARB[3:0] interrupt arbitration value non-zero interrupts enabled. CANICR: ILCAN[2:0] between (interrupts disabled) (highest priority). CANICR: IVBA[2:0] indicates location interrupt vector. Finally, select which TouCAN interrupt sources required IMASK write each corresponding 0-15 where interrupt required completion transmission reception. CANMCR: WAKEMSK wake-up interrupts required. CANCTRL0: BOFFMSK, ERRMSK bits error interrupts. Read free running timer ensure unlocked. Finally clear HALT flag CANMCR enable TouCAN synchronize with allow participation communication. Example TouCAN software initialization listed functions ain_toucan_init aout_toucan_init Section
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Audio Transfer TouCAN
Audio Transfer
system transmitting stereo audio over using TouCAN described. system makes extensive Motorola 68376 microcontroller which combines TouCAN, QADC, QSPI, 7.5K bytes SRAM, CPU32, other additional modules which used this system i.e. timers. audio input node consists stereo input jack audio input, typically from personal player which connects QADC analogue input pins. QADC samples approximately 60kHz i.e. 30kHz channel, data passed TouCAN which transmits over external transceiver audio output node also uses 68376 with TouCAN receiving audio data bus. 68376 uses internal SRAM buffer incoming data before outputting QSPI external serial DAC. provides power output audio signals which capable driving pair amplified speakers. hardware design described full Section
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.000011101011010011101110. CANH CANL CANH CANL
CANH CANL
TRANSCEIVER CANRX CANTX
TRANSCEIVER CANRX CANTX
TOUCAN MC68376 QADC
TOUCAN MC68376 QSPI
LEFT
RIGHT
LEFT
RIGHT
Figure Input Output Nodes Connected
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Freescale Semiconductor, Inc. Application Note Audio Input
5.1.1 Digital Audio Sampling basic task take pair analogue audio wave-forms sample them with regular sampling adequate resolution, quantization, allow them represented numerically. numerical digital data will then reproduced with minimal acceptable amounts noise distortion.
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Figure Analogue Wave-Form Digitized Version Typical hearing bandwidth starts around 20Hz goes between 20kHz. This range narrows with eardrum becomes less flexible. Nyquist's sampling theory states that signal must sampled least twice rate it's maximum frequency component information lost. This means that good audio reproduction, have sample frequency greater than 40kHz, even down 30kHz would still capture audible range detectable most comparison, uses sampling rate 44.1kHz with 16-bit accuracy (96dB SNR) audio reproduction 20kHz, whilst stereo broadcasting NICAM stereo sound system both sampling rate 32kHz with 14-bit accuracy (84dB SNR) audio 15kHz. Voice reproduction handsets uses bandwidth 300Hz 3.4kHz with 8-bit accuracy (48dB SNR). Sampling frequencies this range well within capabilities 68376's QADC, which operate sampling rates above 100kHz with typical conversion times 8.6µs. main limitation bandwidth. Running 1Mbit/s yields approx. 530kbit/s data using standard format 460kbit/s using extended format non-data fields within message. system will standard format higher data bandwidth assume that most this available audio, that some additional non-audio messages present bus. addition, some messages have
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Audio Transfer Audio Input
retransmitted event error. Because these reasons, will reserve available bandwidth audio transmission. simple calculation yields maximum sampling rate each audio channel follows: available bandwidth max. sampling frequency channels) bits sample) using 10-bit QADC 530000 0.90 24kHz -resolution (60dB SNR) sampling rate 24kHz will capture audio frequencies maximum 12kHz insufficient good quality playback. consider several options which would allow increase sampling rate: combine stereo inputs into single mono signal, data compression techniques mathematically compress data, iii) reduce resolution analogue samples. Option suitable since original requirement quality stereo reproduction. Option viable solution would additional loading CPU. system where transfer audio data sole task CPU, this would probably acceptable, other systems where additional tasks running, loading acceptable. Besides, digital data compression techniques out-with scope this note. Option iii) possible noise levels introduced using 8-bit sampling still give acceptable audio reproduction. Also, 8-bit data more suited data byte orientation CAN. Re-applying sampling rate calculation with 8-bit quantization gives: max. sampling freq. using 530000 0.90 29.8kHz -8-bit resolution (48dB SNR) system frequency critical 20MHz been selected simplicity. 68376 currently available 25MHz this required bandwidth limitation, processing power. QADC conversion times based QCLK which turn derived from system clock. minimum QADC conversion time QCLKs will used. prescaler QADC clock calculated give 29.8kHz sampling rate: QADC prescalar -(Samp. freq. Conversion clocks
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Freescale Semiconductor, Inc. Application Note
20000000 18.5 29800 prescaler value will used, resulting sampling frequency 29.2kHz, system clocks. This results bandwidth usage 88%. test audio sampling parameters, system developed using single 68376 with same QADC input circuitry QSPI output circuitry used final system (hardware described Section This system used test hardware, sampling rates quantization levels before moving onto more complicated two-node system with CAN. Simple software used which sampled audio input immediately output data QSPI. This system used digitally sample single audio channel from analogue `line-out' socket personal player playback using external amplified speakers. Experimentation sampling rates quantization levels demonstrated that 8-bit resolution gave reasonable results with little loss quality when compared 10-bit sampling. improvement gained with 30kHz sampling when compared with 24kHz much more noticeable final specification system shall follows:
sampling rate sampling resolution audio channels rate bandwidth 29.2kHz bits 1Mbit/s
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last subject digital audio sampling aliasing. Again, referring Nyquist's sampling theory avoiding detailed mathematics, sampled baseband signal, will reproduced harmonics sampling rate, shown Figure original data reproduced without loss data sampling frequency least twice highest component.
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Audio Transfer Audio Input
ORIGINAL SIGNAL Fs/2
HARMONIC (Fs+Fb)
HARMONIC (2Fs+Fb) freq.
Figure Sampled Signal Harmonics
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Aliasing
freq. Fs/2
Figure
Pass
Fs/2
freq.
Figure sampling frequency less than double, shown Figure reproduced signal first harmonic will overlap original signal resulting distortion called aliasing. avoid aliasing, sampling frequency should increased. this possible, pass filter must used remove some high frequency data within input signal, shown Figure expensive filter with sharp roll-off allows cut-off frequencies half Inexpensive filters with gentle roll-off requires cut-off frequency lower, thus even more original signal lost. trade between price quality must made. system, input signal from will have 20kHz bandwidth. Sampling 29.2kHz means that aliasing will exist without
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Freescale Semiconductor, Inc. Application Note
filter. Brief testing non-CAN test system using sinusoidal inputs showed that aliasing indeed present above 15kHz. However, with audio input, reproduced signal quality reasonable since audio content above 15kHz low. Adding fourth-order filter with cut-off frequency around 14kHz series with input produced little audible difference. these reasons, since filter design goal this note, shall avoid system. 5.1.2 QADC TouCAN Transfer main objective microcontroller audio input side sample analogue input using fixed sampling rate then transfer data onto bus. QADC will used `software triggered continuous-scan mode' which allows QADC itself control sampling rate 29.2kHz channel i.e. 58,400 samples second. single queue, queue with maximum length conversions will used reduce overhead minimum. This queue will configured sample left audio channel PQA0 then right audio channel PQA1 alternatively. Once conversions complete queue full, QADC will generate interrupt request empty conversion result queue transfer data TouCAN module. QADC (interrupt service routine) must move conversion results immediately QADC will loop back start queue overwrite previous results. particular, first conversion result must recovered within 17.1µs i.e. sampling period, first overwritten during next iteration queue. This process summarized Figure
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Audio Transfer Audio Input
10-BIT PQA0 PQA0 (AUDIO LEFT) PQA1 (AUDIO RIGHT) PQA0 (AUDIO LEFT)
PQA1
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PQA1 (AUDIO RIGHT) QADC QUEUE2
Figure QADC Continuous Sampling Operation assigning five available sixteen TouCAN message buffers transmit audio, each with eight data bytes, match bytes from QADC TouCAN data buffer size. first eight bytes data will transmitted from message buffer last eight from message buffer Setting TouCAN transmit lowest numbered buffer first, rather than lowest first (LBUF CANCTRL1), assured proper ordering sampled data. Once QADC completed conversion queue, bytes will transferred TouCAN five message buffers enabled together. TouCAN will then commence arbitration each five messages turn requires further action from until five messages, i.e. bytes, have been transferred. TouCAN setup detailed software section. discussed previously, available bandwidth will used. This means that average will transmit data faster than QADC deliver theory this means that TouCAN message buffers will always empty time QADC completed queue, allowing QADC transfer data bytes directly from result queue TouCAN. practice, there brief periods heavy activity, either from additional transmitter nodes retransmission error-induced message from transmitter. compensate brief periods additional activity, shall small buffer which used temporary store data
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Freescale Semiconductor, Inc. Application Note
from QADC event TouCAN completed transfer. temporary buffer large enough take bytes data from QADC i.e. five message lengths eight data bytes each will sufficient ensure audio data lost long there more than additional non-audio message every audio messages. shown Figure when running bandwidth, additional non-audio message every will keep within available bandwidth limit. small buffer will require only simple software control will protect against data loss when additional infrequent messages present bus. This mechanism suitable when additional data more consecutive messages with high priority appear bus. this situation, bytes buffer would overwritten QADC before TouCAN could retrieve them therefor bytes would lost. This situation could avoided assigning highest priority identifier audio data. system, audio data shall assigned high priority this reason. addition, each five audio messages from five message buffers shall assigned different identifiers. This will give better visibility debug environment also allows demonstration receiver filter mask audio output node. 11-bit message buffer shall i.e. highest possible priority, through message buffer receive mask shall used receiving side filter three least significant bits thus five audio message received using single receive plus three available 32-bit filter registers. Section 5.2.5 explanation receive filter.
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bytes QADC BLOCK QADC BLOCK QADC SAMPLING RATE
units
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TRANSMIT RATE
0.88% units
NON-AUDIO FRAME
Figure Additional Loading flowcharts QADC TouCAN ISRs shown Figure Figure respectively. control data flow from QADC into either TouCAN buffer handled flags CAN_BUSY RAM_FULL shown. These routines must mutually exclusive this easily accomplished assigning both ISRs same interrupt request level. TouCAN interrupt should triggered when five message buffers empty, only last message buffer, will used interrupt generation.
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Freescale Semiconductor, Inc. Application Note
QADC QUEUE FULL
CAN_BUSY MOVE BYTES QADC TOUCAN REACTIVATE
MOVE BYTES QADC
RAM_FULL
Freescale Semiconductor, Inc.
CAN_BUSY
SERVICE INTERRUPT
Figure QADC Flowchart
TOUCAN
RAM_FULL MOVE BYTES TOUCAN RAM_FULL CAN_BUSY REACTIVATE
CAN_BUSY
SERVICE INTERRUPT IFLAG
Figure TouCAN Flowchart
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Audio Transfer Audio Output
These ISRs, along with QADC's queued mechanism TouCAN's multiple message buffer structure, completely handle audio input function sampling dual analogue audio wave-forms transmitting numerical representation onto bus. This means that this function fully interrupt driven system, main audio input routine becomes `do-nothing' loop after performing initialization. other systems this significant audio transfer performed background task.
Audio Output
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node audio output receive data filter non-audio information. must then separate left right channel information reproduce original stereo audio signals. generate analogue wave-form, external (Digital Analogue Converter) will interfaced 68376. Serial input DACs abundant less expensive come smaller packages than corresponding parallel input DAC. QSPI offers ideal interface serial configured most, available. selection criteria follows: serial interface QSPI connection dual channel reproduce left right stereo minimum 8-bit resolution system currently uses 8-bit sampling, 10-bits QADC resolution implemented future revision bandwidth better utilized, i.e. making data compression techniques. single volt supply
5.2.1 Digital Analogue Converter
voltage output drive capable driving pair amplified multimedia speakers MAX549 considered. This cost, dual 8-bit, voltage output, serial input device 8-pin package. drawback with this device high output impedance limited 8-bit resolution. AD1866 more expensive device comes 16-pin package offers features required. dual 16-bit, voltage output, serial input device running from single volt supply. addition, this intended audio applications advantage offering audio compatible outputs i.e. volt 1mA. This chosen application examined more detail hardware sections later. This device requires serial input supplied 16-bit serial stream with two's compliment, first format. QADC offers digital conversions three formats Left Justified, Signed Result
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Freescale Semiconductor, Inc. Application Note
Register `LJSRR' format suitable this case will used audio input node. 5.2.2 QSPI Operation queuing mechanism QSPI will fully utilized output node just QADC input node. QSPI will initiate serial transfers DAC, thus will operate master mode. command queue entries will used perform serial transfers without intervention. addition, wrap-around mode will enabled allow continuous execution queued commands. QSPI output timing will match input sampling rate QADC. This greatly reduces overhead does have generate continuous output data approximately 58,400 bytes second this will task QSPI. merely ensure that there always updated audio data within word queue. Data serially shifted same continuous rate QADC sampling frequency, i.e. 58.4kHz (29.2kHz channel) i.e. every system clocks. Each serial transfer from QSPI consists three components delay before transfer, serial transfer itself delay after transfer, shown Figure Since AD1866 requires fixed 16-bit transfer, 8-bit digital word must zero extended. Maximum QSPI operating shift rate Fsys/4 will used, thus number system clocks actual 16-bit shift will i.e. system clocks. delay before transfer adjustable single system clocks range 127. delay after transfer adjustable steps system clocks from 8192. Choosing delay before delay after results total transfer time system clocks which matches sampling rate QADC.
word serial transfer time transfer frequency delay before transfer time delay after 20MHz system clocks 58.2
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5.2.3 QSPI Data Output Timing
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DELAY BEFORE
SERIAL TRANSFER
DELAY AFTER
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Figure QSPI Serial Data Transfer This setup performed function aout_SPI_init file aout.c software section. 5.2.4 QSPI Data Updating Mechanism Once command entries queue have been executed, QSPI Finished Flag, SPIF, asserted. wrap-around mode, next data word start queue latched into shift register transmission almost immediately after SPIF flag asserted. this reason, cannot simply wait SPIF then reload data entries QSPI would already have latched data transmission from first word queue. SPIF flag more suited serial reception data when used wrap-around mode rather than transmission. around this issue, will load data into queue halves. Referring Figure when queue pointer passes mid-point table, i.e. first eight queued words have been transmitted (CPTQP will load eight data words queue. When QSPI transmits last word queue SPIF triggers, will load eight data words bottom queue. This stage loading mechanism allows QSPI continuously since data will loaded into queue approximately eight transmit periods before they transmitted. latency time after CPTQP SPIF eight transmit times 58.4kHz word i.e. latency QSPI load 137µs 58400 Since only SPIF generate interrupt CPTQP shall interrupts QSPI. Instead shall poll both these conditions before loading data into QSPI transmit data queue. another system where polling possible, SPIF interrupts could
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used capture queue condition timer interrupt could used interrupt just after mid-queue condition.
QSPI QUEUE FRAME EIGHT AUDIO BYTES CPTQP FRAME EIGHT AUDIO BYTES SPIF
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Figure QSPI Queue Mechanism QSPI updating mechanism shown Figure 5.2.5 Receiving Data from Receiving audio data from will relatively straight forward process. Although five message buffers used transmit audio onto CAN, this required only match data buffer size bytes that QADC result buffer. Only message buffer required receive data from CAN. This message buffer will three available mask filter registers exclude non-audio messages. sixteen available message buffers chosen. system will which shares RXGMSK (Receive Global Mask Register) with MB13. This shall 0xFF0FFFFE i.e. mask three bits (MD18-20 correspond first three bits standard format) that differ five audio that five will pass filter process. Receive interrupt will enabled setting bit-6 IMASK register. resulting must take eight data bytes from make them available QSPI. explained previously, cannot write directly QSPI data queue this only done certain
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instances. this reason, must move eight data bytes into temporary buffer. source code this listed aout_MB6_ISR file aout.c further explained software section.
TOUCAN READ CONTROL LOCK MOVE BYTES TOUCAN->RAM SERVICE INTERRUPT FLAG
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READ TIMER UNLOCK
Figure TouCAN Flowchart 5.2.6 Synchronizing Audio Output Input Since micro-processors using separate crystal oscillators used, unavoidable that data output rate will differ slightly from input sampling rate. Although this slight difference speed cannot detected ear, will result gaps audio sound that will audible. output rate slower than input, then buffer between TouCAN QSPI will eventually fill. When this happens, newly received data must discarded there nowhere store Since message consists eight data bytes, data will lost blocks eight bytes time. This equivalent audio transmission discarding this data, output buffer will recover short period then overflow again. Similarly, output rate faster than input, there will periods when QSPI data queue been updated with fresh data. Since QSPI running wrap-around mode, will continue output data regardless will repeat previously transmitted data. Typical crystal accuracy's region ppm. addition, many 68376 systems make internal (phase-locked loop). long term clock jitter resulting clock generated 68376 listed 0.0625% with `long term' defined practice resulting clock will much more accurate than this figure,
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shall these figures calculating worst case rate data loss follows worst case data loss rate variation crystal variation
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0.0625 1310ppm 0.131%
data rate 58.4kHz, this equates maximum loss bytes second. This loss data will produce small gaps output transmission would certainly detected ear. effect will depend large variation between clock rates actually would manifest itself noise audio signal must avoided. question synchronize output input thus avoid loss data? answer avoid select highly accurate crystal oscillator. This would cost system would still result slight differences between clock rates. Another suggestion external oscillator share clock between both processors. most systems using communicate between remote nodes, transmission clock signal would practical. final suggestion have audio output node dynamically adjust output rate QSPI that there always data available within buffer. This achieved without additional hardware cost other than that used buffer data output node. system already 7.5K bytes SRAM internal 68376 will make this technique. buffer used shown Figure This buffer must circular buffer i.e. there beginning end, instead loop where data continuously pushed pulled from bottom. TouCAN routine discussed previous section, will take eight data bytes from receive message buffer place them onto circular buffer position defined
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`data-in' pointer. will then transfer them into bottom half QSPI data queue.
QSPI
CIRCULAR BUFFER data data data data data data data data data data data
LOWER LIMIT
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DATA AVAILABLE BUFFER
POINT
TOUCAN
UPPER LIMIT
Figure Audio Output Data Buffer function QSPI control loop move data from buffer QSPI monitor amount data within circular buffer i.e. distance between data-in data-out pointer. QSPI output rate will then adjusted that amount data buffer less than upper limit avoid having discard data from TouCAN, greater than lower limit avoid QSPI being starved data. algorithm will used where three possible QSPI data rates selected follows: NORMAL nominal QSPI speed will that previously calculated i.e. system clock periods. This will selected when circular buffer data size reaches mid-way. FAST fast speed will selected when circular buffer data size greater than upper limit allow QSPI empty data more rapid rate will system clocks.
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SLOW slow speed will selected when circular buffer data size less than lower limit allow TouCAN build data stack upwards avoid zero data situation will system clocks. These small variations approximately 0.3% NORMAL will little effect quality audio output. operation QSPI circular buffer analyzed. After system reset, data size will zero i.e. less than lower limit QSPI SLOW rate will come into effect. SLOW speed will such that QSPI removes data slower rate than TouCAN places incoming data onto buffer. data size will slowly increase until reaches mid-point. QSPI NORMAL rate will selected restrict increase data buffer. nodes have identical clock rates, buffer will remain centered mid-point NORMAL rate will remain. However, input clock faster than output, buffer content will continue increase, although slower rate than before. Eventually upper limit will reached FAST rate will selected which will lead reduction buffer content until once again mid-point reached. This will result continual switching QSPI output rate between NORMAL FAST buffer size fluctuating between mid-way upper limit. This adjustment audio output rate very small will audible. similar description applied when input clock slower than output. Here QSPI will toggle between NORMAL SLOW buffer size will fluctuate between midway lower limit. 5.2.7 Altering QSPI Output Rate Buffer Size minimum adjustment QSPI output rate system clock achieved adjusting DSCKL field i.e. delay before transfer. Since nominal speed system clocks, adjustment clock period either gives QSPI output frequency variation approximately 0.3%. This sufficient override maximum possible clock difference between input output nodes which shown 0.131%. Choosing buffer size bytes will allow buffer messages eight data bytes each. explained previously, `data-in' pointer will traverse between either lower limit mid-point mid-point upper limit i.e. QSPI speed will alter after approximately data bytes have accumulated. Since output node running QSPI 0.3% variation from input sampling rate, minimum time speed alteration calculated: buffer size min. QSPI output rate adjustment period -max. data accumulation rate
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bytes seconds 58.4K bytes/s 0.3% Therefor choosing buffer size bytes cause QSPI output rate alter often every seconds. smaller buffer used i.e. buffer bytes would still allow buffering data frames bytes each. system using 68376 with 7.5K bytes RAM, bytes problem. possible adjust QSPI output rate time. DSCKL field within SPCR1 register which cannot altered while QSPI running operation will disrupted. algorithm altering speed will involve following steps: clear WREN SPCR2 disable wrap-around mode that QSPI output ceases once last word queue sent wait transmission last word monitoring SPIF SPSR (QSPI status register). iii) re-enable wrap around mode setting WREN bit. write value DSCKL start continuous transmission setting SPE, both within SPCR1 register. These steps must completed quickly possible that interruption audio output detected. software QSPI paused only three instructions i.e. approximately micro-second thus change over almost unobservable. QSPI updating mechanism shown Figure coded file aout.c.
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POINTER
CHECK QSPI SPEED. CLEAR WREN CHANGE REQD.
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BYTES, QSPI
SPIF
QSPI SPEED CHANGE
WREN SPCR2 SPEED ENABLE
CLEAR SPIF. BYTES, QSPI 8-15
Figure Audio Output Main Routine
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Hardware Design Audio Output
Hardware Design
audio hardware consists biasing filtering analogue audio signal from audio input (i.e. QADC output node, interface from QSPI amplified speakers. hardware consists transceiver both nodes termination resistors either transmission line.
Audio Input Node
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MC68376 BIASING QADC TOUCAN TRANSCEIVER Audio Output Node MC68376 TRANSCEIVER TOUCAN QSPI SPEAKERS
Figure Hardware Circuitry
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Freescale Semiconductor, Inc. Application Note Audio Input Hardware
VDDA MC68376 0.1uF 0.7V 470K 100R 470K LEFT VSSA VDDA 0.01uF VSSA
PQA0
Freescale Semiconductor, Inc.
0.1uF 0.7V
470K 100R 470K 0.01uF VSSA
PQA1
RIGHT VSSA VDDA VDDA 100R 0.1uF 120R 100R 3.44V 0.1uF 1.56V
VSSA
VSSA
Figure Audio Hardware audio output signal from line jack personal player typically 0.7V maximum. open-circuit output voltage from headphone socket high volt. both cases, voltage centered around volts. Referring Figure provide biasing audio input signal center around Vdd/2 i.e. 2.5V. This circuit also high pass filter with cutoff frequency 1/2RC where parallel with Choosing large values prevents lower audible frequencies being off. cutoff frequency component values 0.1µF, 235k) 7Hz, allowing audible frequency 20Hz pass.
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Hardware Design Audio Input Hardware
second stage audio input circuit comprising pass circuit recommended QADC analogue pins. This pass filter designed filter high frequency noise from external digital circuitry clocks. This particular circuit uses smaller values than usually recommended that cutoff frequency high enough prevent attenuation audio frequency band. Using 0.01µF results cutoff frequency which high enough pass upper audio band 20kHz, enough filter most digital noise which system will around from system clock.
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With 0.7V input centered Vdd/2, signal range into PQA0 PQA1 pins will from volts. achieve full-scale, full-range results from QADC, this input range should match reference voltage range pins. this using methods: amplify input voltage range factor approximately three input range almost volts, match audio input voltage range. Both these methods have their relative merits. first requires additional circuitry i.e. non-inverting amplifier, would help reduce error noise assuming could amplify audio signal before injection noise from digital circuitry. second method requires simple circuitry, i.e. only simple potential divider circuit bias VRL. disadvantage here that below minimum specified reference voltage differential range QADC i.e. volts. QADC will still function using reduced reference voltage range, full accuracy guaranteed over smaller range. simplify hardware design will choose option reduce VREF differential range match audio input range. loss accuracy analogue conversions caused QADC operating outside guaranteed range critical audio system, especially ours where have discarded LSBs conversion. Choosing values 100, respectively gives 1.56V 3.44V which sets QADC close full scale over non-amplified audio input voltage range. Finally, provide capacitive bypassing help reduce noise analogue supply reference voltage.
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Freescale Semiconductor, Inc. Application Note Audio Output Hardware
reasons described Section Audio Output, audio output hardware will consist AD1866N dual 16-bit audio 68376's QSPI synchronous serial interface port. hardware connections shown Figure
VDDA
AD1866N
MC68376 PCS1 PCS0 MOSI MISO
0.1uF
Freescale Semiconductor, Inc.
VSSA 0.1uF LEFT 470R 0.01uF RIGHT 470R 0.01uF
4.7uF AGND VSSA 4.7uF VSSA
Figure Audio Hardware 6.2.1 Digital Signals Since QSPI will operating master mode, supplies serial transfer clock (SCK) data output (MOSI). MISO required since there incoming data QSPI. QSPI will supply data both left right channels from MOSI pin, left right data input pins, tied together. programmable chip selects, PCS0 PCS1, used control DAC's left right channel latch enables will assert alternative 16-bit data transitions. data transfer summarized below.
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PCS0
PCS1
MOSI
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clocks Delay After Delay Before clocks
Figure Audio Output Data Transfer 6.2.2 Analogue Signals left right audio analogue signals driven from respectively. supply bias equal center output voltage swing providing coupling pair amplified speakers. Simple first order pass filters comprising R10/C7 R11/C8 with cut-off frequency that required refine quantized edges high frequency harmonics sampled signal outwith human hearing range anyway. output voltage range from volt will directly drive pair amplified personal multimedia speakers with input impedance above AD1866 separate power supplies limit effect digital noise analogue signals. DGND connected digital supply AGND should connected separate power supply available. separate analogue supply available then good layout would provide separate traces from main power input digital analogue portions circuitry. Finally, capacitors reduce output noise contributed DAC's internal voltage reference circuitry.
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Figure shows TouCAN interface physical using 82C250 transceiver TouCAN CANRX0 CANTX0 pins connected directly transceiver. CANH CANL signals connect directly physical bus. typically wire twisted pair, possibly shielded must terminated with resistors each bus. VREF tied ground select high speed operating mode i.e. slope control. high floating signal input from TouCAN forces transceiver into dual transmit receive mode. It's CANH CANL pins float approx. equal voltages around 2.5V (recessive). other node drives then output drives high indicate recessive. another node drives dominant level bus, transceiver drives low. TouCAN transmitting this instant, then this usually means that lost arbitration node that transmitted dominant bit. signal input from TouCAN forces transceiver into transmit mode. CANH CANL pins drive dominant state onto bus. CANH will approximately 3.5V CANL approximately 1.5V i.e. differential. This condition forces which echo's dominant state back TouCAN.
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82C250 VREF CANH CANL
MC68376 CANRX0 CANTX0
0.1µF TWISTED PAIR 120R TERMINATION
Figure Interface
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Software File Summary
Software
This section describes software required TouCAN, QADC QSPI set-up control audio transfer described previously includes source code software comprises three source code files plus three header files. General initialisation provided assumed that system clock been 20MHz internal software watchdog been disabled.
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File Summary
ain.c this code which will audio input node provides functionality sample audio into system using QADC channels transfer data bus. aout.c code audio output node will receive data from CAN, buffer SRAM then transfer QSPI external where replayed pair amplified speakers. toucan.c this file contains functions that common both audio input output nodes will included linking process both object files. audio.h general defines constants ain.c aout.c. regs.h this header file contains declarations subset 68376 registers used plus type definitions. toucan1.h constants field definitions used toucan.c file.
Generic TouCAN Routines file `toucan.c'
There four generic routines file `toucan.c' three provide basic TouCAN functionality allows alteration interrupt mask status register. These functions common both audio input audio output nodes will linked with ain.c aout.c respectively form object files input output nodes. functions follows: general TouCAN initialization performed writing CANMCR, CANCTRL0, CANCTRL1, PRESDIV, CANCTRL2 CANICR registers. TouCAN module left HALT mode message buffers left inactive state. Instead passing lengthy string arguments this function, table constants defined header file `toucan1.h'. These constants define parameters that usually fixed design time i.e. timing, etc. used nodes bus.
7.2.1 toucan_init_ global
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7.2.2 toucan_MB_ TouCAN message buffers will reset undetermined state after power-up must initialized before enabling TouCAN module. This routine resets buffers inactive state writing code field control/status registers. This function also clears IFLAG register zero completeness. This function called commence TouCAN activation after registers message buffers have been initialized required. free running timer read unlock receive buffers HALT flag negated start TouCAN synchronization with external bus. This function included this file generic both audio audio out. enables maskable interrupts writing required level mask within CPU32 Status Register. assembler instruction required access Status Register. File `ain.c' linked with `toucan.c' described above form object code audio input node. Referring back Section 5.1, audio input functionality provided interrupt service routines shown Figure Figure QADC TouCAN. These ISRs plus their initialization formed four functions ain.c follows: This function initializes TouCAN transmission with 0-4. three generic TouCAN routines used here. following operations performed: Initialize TouCAN global registers including timing configuration. interrupt request arbitration fields. MB0-MB4 transmit buffers, each with eight data bytes i.e. data bytes total match QADC queue size. Enable interrupts transfer completion. Enable TouCAN participation. 7.3.2 ain_QADC_ init Here, QADC initialized perform audio sampling required frequency audio channels. following parameters set: Continuous conversions QADC queue using 40-word conversion queue enable interrupts queue completion.
7.2.3 toucan_bus_
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7.2.4 set_ip
Audio Input file `ain.c'
7.3.1 ain_toucan_ init
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Software Audio Output file `aout.c'
58.48kHz sampling rate (342 system clocks) using alternating input channels from left right audio inputs i.e. PQA0 PQA1. 7.3.3 ain_Q2_ISR This interrupt service routine QADC queue complete shown Figure Software loops avoided here reduce execution time expense slightly larger code size. This routine transfers conversion results either TouCAN temporary buffer SRAM. This interrupt service routine TouCAN transmission complete shown flowchart Figure This interrupt indicates that MB0-MB4 have completed transmission ready more data. data available SRAM then transferred into MB0-MB4 otherwise exited QADC will refill short time later. interrupt serviced clearing relevant bits TouCAN's IFLAG register. idles nothing loop' awaiting either ISRs. another system, perform additional tasks here. File aout.c plus generic routines toucan.h linked together form object code audio output node. This functionality described Section 5.2. main loop polls QSPI make slight adjustments QSPI transfer rate control size data queue SRAM buffer system frequency variations nodes. reception data subsequent transfer into SRAM buffer performed TouCAN interrupt routine. following functions provided: Initialize TouCAN global registers including timing configuration. interrupt request arbitration fields. Receive Global Mask Register receive audio data frames Enable interrupts data reception. Enable TouCAN participation.
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7.3.4 ain_MB4_ISR
7.3.5 Audio-in main routine
Audio Output file `aout.c'
7.4.1 aout_toucan _init
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7.4.2 aout_SPI_init This function initializes QSPI output audio data external replay. Enable QSPI master with 16-word queue wrap-around transfer. alternate transfers activate either audio left audio right chip selects i.e. PCS0 PCS1. Start QSPI transmitting nominal transfer rate i.e. system clocks match audio input sampling rate. This function tests size SRAM buffer QSPI transfer rate. data buffer out-with maximum minimum limits, then QSPI transfer rate must adjusted allow buffer return mid-position. Since QSPI transfer rate cannot adjusted until transfer complete, this routine merely disables QSPI wrap-around mode sets parameter indicate required speed main polling routine. This routine receives eight audio data bytes from places them SRAM buffer. five audio transmitted five message buffers filtered captured this single message buffer output node. data will pulled from opposite buffer transferred QSPI main routine. Here QSPI updated described Section 5.2.6 Section 5.2.7. Data transferred from SRAM buffer blocks eight bytes either bottom half 16-word QSPI queue ensure that output transfer mechanism continuous. main loop polls QSPI's CPTQP pointer SPIF flag verify when transfer upper lower half queue complete. addition, main routine responsible adjusting QSPI transfer rate directed `testSPIspeed' ensure synchronization with audio input node. flowchart this routine shown Figure
7.4.3 testSPIspeed
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7.4.4 aout_MB6_
7.4.5 Audio-out main routine
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Source Listings
7.5.1 ain.c
COPYRIGHT MOTOROLA 1998 FILE NAME: ain.c Audio input function 68376: QADC ->TouCAN INCLUDE FILES: regs.h (68376 registers plus basic type defs) toucan1.h (Constants defs TouCAN) audio.h (General constants audio demo) DESCRIPTION: This file performs audio functionality 68376. Stereo audio data sampled QADC pins (PQA0,1) into single 40-word queue. Only upper 8-bits 10-bit QADC conversion used limited bandwidth approx. 550kbit/s using 1Mbit/s rate. completion QADC conversion queue, bytes transferred into five TouCAN message buffers transmission over bus. main loop `do-nothing' loop both QADC TouCAN interrupt driven. This code intended demonstration purposes only guaranteed function given application. COMPILER: Crosscode VERSION: AUTHOR: Allan Dobbin LAST EDIT DATE: 10/Jun/98 LOCATION: East Kilbride, Scotland. UPDATE HISTORY AUTHOR DATE DESCRIPTION CHANGE Dobbin 10/Jun/98 First release file. include files #include "regs.h" #include "toucan1.h" #include "audio.h"
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68376 registers plus basic type defs*/ Constants defs TouCAN*/ General constants audio demo*/
Global variables volatile char can_busy=0; volatile char ram_full=0; volatile union BYTE4 buffer[10]; buffer access bytes longs*/
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Function prototypes void ain_toucan_init(void); initialise TouCAN MB0-4 interrupt void ain_QADC_init(void); init QADC, word queue, interrupt full ISRs void ain_Q2_ISR(void); void ain_MB4_ISR(void);
QADC full completed
Main routine
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void main (void) Initialise TouCAN QADC modules ain_toucan_init(); ain_QADC_init(); set_ip(3); initialise TouCAN MB0-4 interrupt init QADC, word queue, interrupt full enable interrupts level above
Loop forever audio input routine interrupt service routines for(;;) MAIN function
Function declarations Function ain_toucan_init() Parameters Void Return Void Description TouCAN module initialisation routine AUDIO (QADC TouCAN). Five message buffers initialised audio transmit. will last buffer transmit interrupt enabled completion. void ain_toucan_init(void) WORD *buf; toucan_init_global ();/* Initialise TOUCAN global registers, disable IMASK BIT4; enable buffer interrupts MB0.id MB1.id MB2.id MB3.id MB4.id AUDIO0_ID; AUDIO1_ID; AUDIO2_ID; AUDIO3_ID; AUDIO4_ID; Audio0 Audio1 Audio2 Audio3 Audio4 AN1776
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Software Source Listings
&MB0.control; while (buf &MB4.control) *buf TX_ENABLE toucan_bus_on Function ain_QADC_init() Parameters Void Return Void Description QADC initialsation routine AUDIO (QADC TouCAN). void ain_QADC_init(void) WORD *ccw; QADCMCR 0x008F; QADCINT 0x0554; QACR0 0x00C5; QACR1 0x0000; Queue disabled interrupt arbitration level (high) Queue uses (same TouCAN), interrupt vector i.e. offset $150 comp $154) mux, PSH=13, PSL=6 i.e. QCLK FSYS/19. Fsys 20MHz Sample rate 58.5KHz i.e. clocks clock conversion)
scan through MB0-MB4 control words each with data bytes point next turn TouCAN release MB's clear HALT
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(ccw=CCW; ccw<(CCW+40); ccw+=2) each pair control words *ccw 0x0034; sample's PQA0 (audio left) *(ccw+1) 0x0035; even sample's PQA1 (audio right) QACR2 0xB100; Function declarations Function ain_Q2_ISR() INTERRUPT SERVICE ROUTINE Parameters Void Return Void Description QADC queue full interrupt service routine AUDIO TouCAN busy then results stored buffer. Otherwise they transferred TouCAN. loop used here that interrupt routine fast possible. #pragma interrupt() void ain_Q2_ISR(void) (!can_busy) AN1776 MOTOROLA declare that next function interrupt function Enable comp. interrupts, start cont. scan, word queue
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Freescale Semiconductor, Inc. Application Note
/*************** TouCAN busy *****************/ move Conversions from QADC Left Justified Signed Result table (high byte only) TouCAN Message Buffers MB0.data.b[0] MB0.data.b[1] MB0.data.b[2] MB0.data.b[3] MB0.data.b[4] MB0.data.b[5] MB0.data.b[6] MB0.data.b[7] LJSRR.no[0]; LJSRR.no[2]; LJSRR.no[4]; LJSRR.no[6]; LJSRR.no[8]; LJSRR.no[10]; LJSRR.no[12]; LJSRR.no[14]; LJSRR.no[16]; LJSRR.no[18]; LJSRR.no[20]; LJSRR.no[22]; LJSRR.no[24]; LJSRR.no[26]; LJSRR.no[28]; LJSRR.no[30]; LJSRR.no[32]; LJSRR.no[34]; LJSRR.no[36]; LJSRR.no[38]; LJSRR.no[40]; LJSRR.no[42]; LJSRR.no[44]; LJSRR.no[46]; LJSRR.no[48];/* BUFFER LJSRR.no[50]; LJSRR.no[52]; LJSRR.no[54]; LJSRR.no[56]; LJSRR.no[58]; LJSRR.no[60]; LJSRR.no[62]; LJSRR.no[64]; LJSRR.no[66]; LJSRR.no[68]; LJSRR.no[70]; LJSRR.no[72]; LJSRR.no[74]; LJSRR.no[76]; LJSRR.no[78]; BUFFER BUFFER
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MB1.data.b[0] MB1.data.b[1] MB1.data.b[2] MB1.data.b[3] MB1.data.b[4] MB1.data.b[5] MB1.data.b[6] MB1.data.b[7] MB2.data.b[0] MB2.data.b[1] MB2.data.b[2] MB2.data.b[3] MB2.data.b[4] MB2.data.b[5] MB2.data.b[6] MB2.data.b[7] MB3.data.b[0] MB3.data.b[1] MB3.data.b[2] MB3.data.b[3] MB3.data.b[4] MB3.data.b[5] MB3.data.b[6] MB3.data.b[7] MB4.data.b[0] MB4.data.b[1] MB4.data.b[2] MB4.data.b[3] MB4.data.b[4] MB4.data.b[5] MB4.data.b[6] MB4.data.b[7] MB0.control MB1.control MB2.control MB3.control MB4.control
BUFFER
BUFFER
TX_ENABLE TX_ENABLE TX_ENABLE TX_ENABLE TX_ENABLE
activate each message buffer
can_busy
then flag show that busy AN1776
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else
/****** otherwise TouCAN busy ***********/ buffer[0].b[0] buffer[0].b[1] buffer[0].b[2] buffer[0].b[3] buffer[1].b[0] buffer[1].b[1] buffer[1].b[2] buffer[1].b[3] buffer[2].b[0] buffer[2].b[1] buffer[2].b[2] buffer[2].b[3] buffer[3].b[0] buffer[3].b[1] buffer[3].b[2] buffer[3].b[3] buffer[4].b[0] buffer[4].b[1] buffer[4].b[2] buffer[4].b[3] buffer[5].b[0] buffer[5].b[1] buffer[5].b[2] buffer[5].b[3] buffer[6].b[0] buffer[6].b[1] buffer[6].b[2] buffer[6].b[3] buffer[7].b[0] buffer[7].b[1] buffer[7].b[2] buffer[7].b[3] buffer[8].b[0] buffer[8].b[1] buffer[8].b[2] buffer[8].b[3] buffer[9].b[0] buffer[9].b[1] buffer[9].b[2] buffer[9].b[3] ram_full LJSRR.no[0]; LJSRR.no[2]; LJSRR.no[4]; LJSRR.no[6]; LJSRR.no[8]; LJSRR.no[10]; LJSRR.no[12]; LJSRR.no[14]; LJSRR.no[16]; LJSRR.no[18]; LJSRR.no[20]; LJSRR.no[22]; LJSRR.no[24]; LJSRR.no[26]; LJSRR.no[28]; LJSRR.no[30]; LJSRR.no[32]; LJSRR.no[34]; LJSRR.no[36]; LJSRR.no[38]; LJSRR.no[40]; LJSRR.no[42]; LJSRR.no[44]; LJSRR.no[46]; LJSRR.no[48]; LJSRR.no[50]; LJSRR.no[52]; LJSRR.no[54]; LJSRR.no[56]; LJSRR.no[58]; LJSRR.no[60]; LJSRR.no[62]; LJSRR.no[64]; LJSRR.no[66]; LJSRR.no[68]; LJSRR.no[70]; LJSRR.no[72]; LJSRR.no[74]; LJSRR.no[76]; LJSRR.no[78]; Transfer justified, signed byte SRAM written BYTE time since QADC table values every byte
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then flag show that full
QASR ~BIT13; Clear QASR service interrupt
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Freescale Semiconductor, Inc. Application Note
Function ain_MB4_ISR() INTERRUPT SERVICE ROUTINE Parameters Void Return Void Description TouCAN transmit interrupt service routine AUDIO (QADC->TouCAN).If buffer full then data bytes transferred from TouCAN module transmitted. Otherwise can_busy flag cleared module waits QADC interrupt. #pragma interrupt() void ain_MB4_ISR(void) (ram_full) This method transferring bytes from buffer used faster transfer data long words rather than Bytes. MB0.data.l[0] MB0.data.l[1] MB1.data.l[0] MB1.data.l[1] MB2.data.l[0] MB2.data.l[1] MB3.data.l[0] MB3.data.l[1] MB4.data.l[0] MB4.data.l[1] ram_full can_busy MB0.control MB1.control MB2.control MB3.control MB4.control else can_busy TX_ENABLE TX_ENABLE TX_ENABLE TX_ENABLE TX_ENABLE activate each buffer[0].l; buffer[1].l; buffer[2].l; buffer[3].l; buffer[4].l; buffer[5].l; buffer[6].l; buffer[7].l; buffer[8].l; buffer[9].l; fill message buffer fill message buffer fill message buffer fill message buffer fill message buffer declare that next function interrupt function
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/******************** BUFFER FULL THEN ******/ transfer bytes from TouCAN
/*** ELSE (RAM ISN'T FULL) ***/ clear busy flag /*****************************/ Read write IFLAG clear Clear MB0-4.
IFLAG 0xFFE0;
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7.5.2 aout.c
COPYRIGHT MOTOROLA 1998 FILE NAME: aout.c Audio output function 68376: TouCAN QSPI INCLUDE FILES: regs.h (68376 registers plus basic type defs) toucan1.h (Constants defs TouCAN) audio.h (General constants audio demo) DESCRIPTION: This file performs audio functionality 68376. Audio data received from into TouCAN then shifted QSPI external conversion back original stereo audio analogue signals. internal SRAM used buffer several hundred bytes data. amount data within buffer monitored controlled adjusting speed QSPI transfer. This buffering dynamic adjustment QSPI rate allows slight differences frequency oscillators used input output MCUs. This code intended demonstration purposes only guaranteed function given application. COMPILER: Crosscode VERSION: AUTHOR: Allan Dobbin LAST EDIT DATE: 10/Jun/98 LOCATION: East Kilbride, Scotland. UPDATE HISTORY AUTHOR DATE DESCRIPTION CHANGE Dobbin 10/Jun/98 First release file.
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include files #include "regs.h" #include "toucan1.h" #include "audio.h"
68376 registers plus basic type defs Constants defs TouCAN General constants audio demo
Global variables volatile union BYTE4 aout_buffer[BUFF_SIZE]; aout buffer access bytes long words*/ volatile buffer_cnt=0; Count data currently held aout_buffer. Units longword.*/
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Function prototypes void aout_toucan_init(void); initialise TouCAN interrupt driven void aout_SPI_init(void); init QSPI AOUT. WORD testSPIspeed (void); aout subroutine tests speed changes reqd. ISRs void aout_MB6_ISR(void);/* TouCAN full. AOUT Main routine
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void main (void) volatile SPIptr Points aout_buffer remove data volatile SPIchanged Variable debug indicates often speed changes WORD SPIupdate; old_ip; extern ip_level; Initialise TouCAN QSPI modules aout_toucan_init(); aout_SPI_init(); set_ip(3); Loop forever for(;;) while SPSR 0x0F transfer data bytes from buffer upper half QSPI TRAN.RAM TRANRAM.data[0] aout_buffer[SPIptr].b[0]; TRANRAM.data[2] aout_buffer[SPIptr].b[1]; TRANRAM.data[4] aout_buffer[SPIptr].b[2]; TRANRAM.data[6] aout_buffer[SPIptr++].b[3]; TRANRAM.data[8] aout_buffer[SPIptr].b[0]; TRANRAM.data[10] aout_buffer[SPIptr].b[1]; TRANRAM.data[12] aout_buffer[SPIptr].b[2]; TRANRAM.data[14] aout_buffer[SPIptr++].b[3]; (SPIptr BUFF_SIZE-1) SPIptr old_ip ip_level; set_ip(7); buffer_cnt set_ip(old_ip); Read current value field disable interrupts while updating variable Decrement data counter enable interrupts level above initialise TouCAN interrupt driven init QSPI AOUT. enable interrupts level above
Here check size buffer QSPI speed requires adjustment keep input output nodes synchronised. speed does require changed, function clears WREN halt QSPI continuous transfer sets SPIupdate nonzero. AN1776
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SPIupdate testSPIspeed(); while (!(SPSR BIT7)) function before SPIF save time wait until finished transmitting*/
(SPIupdate)/* Change speed while stopped (queue comp wrap SPCR2 BIT14; Turn wrap-around SPCR1 SPIupdate; speed activate setting SPIchanged++; Debug only
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SPSR ~BIT7; transfer data bytes from TRANRAM.data[16] TRANRAM.data[18] TRANRAM.data[20] TRANRAM.data[22] TRANRAM.data[24] TRANRAM.data[26] TRANRAM.data[28] TRANRAM.data[30] buffer lower half QSPI TRAN.RAM aout_buffer[SPIptr].b[0]; aout_buffer[SPIptr].b[1]; aout_buffer[SPIptr].b[2]; aout_buffer[SPIptr++].b[3]; aout_buffer[SPIptr].b[0]; aout_buffer[SPIptr].b[1]; aout_buffer[SPIptr].b[2]; aout_buffer[SPIptr++].b[3];
clear SPIF
(SPIptr BUFF_SIZE-1) SPIptr old_ip ip_level; set_ip(7); buffer_cnt set_ip(old_ip); MAIN function Read current value field disable interrupts while updating variable Decrement data counter enable interrupts level above
Function declarations Function aout_toucan_init() Parameters: Void Return Void Description: TouCAN module initialisation routine AUDIO (TouCAN QSPI). message buffer initialised audio receive buffer. void aout_toucan_init(void) toucan_init_global IMASK BIT6;
Initialise TOUCAN global registers, disable enable buffer interrupts.
MB6.id AUDIO0_ID; audio mask will audio msgs AN1776 MOTOROLA
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MB6.control RX_ENABLE; RXGMSK AUDIO_MASK; toucan_bus_on buffer active receiver. global mask receive audio turn TouCAN release MB's clear HALT
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Function aout_SPI_init() Parameters Void Return Void Description QSPI initialisation routine AUDIO (TOUCAN QSPI). void aout_SPI_init(void) index; QSMCR 0x0080; QILR 0x0000; PQSPAR 0x7B; PORTQS 0x0000; DDRQS 0xFE; SPCR0 0x8302; SPCR1 NORMAL&(~BIT15); SPCR2 0x4F00; SPCR3 0x00; scanning command transmit interrupt arbitration level Disable QSPI interrupts pins PORTQS serve QSPI/SCI. Clear data register Configure PortQS QSPI operation Master mode, bits transfer, data. changed rising edge, Fsys/4 i.e. 4MHz transfer rate Deactivate QSPI speed. interrupts, queue with wrap-around.*/ loop halt mode, mode fault interrupts.*/
/*********** command *********/ (index=0; index<16; index+=2) each pair command bytes COMMRAM.data[index] 0x7D; COMMRAM.data[index+1] 0x7E; (index=0; index<32; index++) TRANRAM.data[index] 0x00; SPCR1 BIT15; Function testSPIspeed() Parameters Void Return WORD FAST, NORMAL SLOW indicate reqd. speed QSPI. Description This routine tests size buffer indicates whether speed alter compensate. speed change required, QSPI LOOP mode disabled that calling routine adjust QSPI rate once transfer stops. AN1776 first activates PCS0 (audio left) second activates PCS1 (audio right)
Clear bytes transmit dataRAM Activate QSPI setting
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WORD testSPIspeed (void) (buffer_cnt BUFF_MAX (SPCR1 FAST) SPCR2 ~BIT14; Disable wrap-around, will stop queue return(FAST); (buffer_cnt BUFF_MID) (SPCR1 SLOW) SPCR2 ~BIT14; Disable wrap-around, will stop queue return(NORMAL);
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(buffer_cnt BUFF_MID) (SPCR1 FAST) SPCR2 ~BIT14; Disable wrap-around, will stop queue return(NORMAL); (buffer_cnt BUFF_MIN) (SPCR1 SLOW) SPCR2 ~BIT14; Disable wrap-around, will stop queue return(SLOW); return(0); Function declarations Function aout_MB6_ISR() INTERRUPT SERVICE ROUTINE Parameters Void Return Void Description TouCAN receive interrupt service routine AUDIO OUT. Places data from TouCAN into buffer updates pointer. Interrupt source serviced re-enabled next receive. #pragma interrupt()/* declare that next function interrupt function void aout_MB6_ISR(void) WORD tmr_temp; used read TIMER unlock static volatile buffer_error Debug variable shows overflow aout_buffer static volatile CANptr Points next free location aout_buffer tmr_temp MB6.control; (buffer_cnt BUFF_SIZE buffer_error++; AN1776 MOTOROLA Read control register lock receive buffer Return buffer data within limits
Debug this should never increment past
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Freescale Semiconductor, Inc. Application Note
else aout_buffer[CANptr++].l MB6.data.l[0]; move data from message buffer buffer aout_buffer[CANptr++].l MB6.data.l[1]; (CANptr BUFF_SIZE-1 CANptr buffer_cnt IFLAG ~BIT6; tmr_temp TIMER; Read IFLAG then clear read free running timer release last buffer read Increment data counter
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7.5.3 toucan.c
COPYRIGHT MOTOROLA 1998 FILE NAME: toucan.c Generic functions TouCAN INCLUDE FILES: regs.h (68376 registers plus basic type defs) toucan1.h (Constants defs TouCAN) audio.h (General constants audio demo) DESCRIPTION: This file contains generic TouCAN functions follows void toucan_MB_off (void) MB's inactive, clear IFLAG void toucan_bus_on (void) Activates TouCAN negating HALT flag void toucan_init_global (void) Initialise TOUCAN global registers void set_ip (int Enables interrupts setting This code intended demonstration purposes only guaranteed function given application. COMPILER: Crosscode VERSION: AUTHOR: Allan Dobbin LAST EDIT DATE: 10/Jun/98 LOCATION: East Kilbride, Scotland. UPDATE HISTORY AUTHOR DATE DESCRIPTION CHANGE Dobbin 10/Jun/98 First release file.
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include files #include "regs.h" 68376 registers plus basic type defs #include "toucan1.h" Constants defs TouCAN #include "audio.h" General constants audio demo Global variables ip_level
initial value after reset
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Function toucan_MB_off() Parameters Void Return Void Description TouCAN MB's inactive clear IFLAG register. void toucan_MB_off (void) WORD *buf; WORD mbiflag;
reading TouCAN iflag register
&MB0.control; while (buf &MB15.control) *buf RX_DISABLE; mbiflag IFLAG; IFLAG
scan through each MB's control word declare each buffer inactive point next buffer
Clear bits IFLAG register reading then writing
Function toucan_bus_on() Parameters Void Return Void Description Unlocks message buffers activates TouCAN negating HALT flag allow synchronisation with external bus. void toucan_bus_on (void) WORD tmr_temp; tmr_temp TIMER; CANMCR ~BIT12;
used read TIMER unlock read free running timer release last buffer read activate TouCAN module clearing HALT
Function toucan_init_global() Parameters Void Return Void Description Initialise TOUCAN global registers (CANMCR, CANICR, CANCTRL0/1, PRESDIV, CANCTRL2) timing, control interrupts. TouCAN MB's inactive. Mask registers IMASK register configured here. TouCAN left HALT mode. AN1776 MOTOROLA
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void toucan_init_global (void) CANMCR 0x5400; asm(" NOP" while CANMCR BIT9 force SOFT RESET TouCAN Delay cycle before accessing wait reset cycle complete
user def. error interrupt masks Rx/Tx configuration CANCTRL0 (BOFFMSK%2 <<7) (ERRMSK%2 <<6) (RXMODE%4 (TXMODE%4); user def. bits including prop seg. quanta CANCTRL1 (SAMP%2 <<7) (TSYNC%2 <<5) (LBUF%2 <<4) (PROPSEG%8);
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Configure user defined prescale value PRESDIV PRES_D%256; Configure user defined timings CANCTRL2 (RJW%4 <<6) (PSEG1%8 <<3) (PSEG2%8); Enable TouCAN clocks into debug mode. user defined bits CANMCR (FRZ%2 <<14) BIT12 (WAKEMSK%2 <<10) (SUPV%2 <<7) (SELFWAKE%2 <<6) (APS%2 <<5) (CAN_IARB%8); Configure user def. interrupt level base address CANICR (ILCAN%8 <<8) (IVBA%8 <<5); toucan_MB_off Function set_ip() Parameters value written field. Return Void Description This routine enables interrupts different levels setting field status register. Assembler instructions must used here. Note value passed value written. This will enable interrupts higher levels only i.e. enables IRQ5-7. void set_ip (int switch (ip) case asm(" ANDI.W case asm(" ANDI.W case asm(" ANDI.W case asm(" ANDI.W TouCAN MB's inactive
ORI.W #0xF0FF,SR" ORI.W #0xF1FF,SR" ORI.W #0xF2FF,SR" ORI.W #0xF3FF,SR"
#0x0700,SR", Enable level break; #0x0700,SR", Enable level break; #0x0700,SR", Enable level break; #0x0700,SR", Enable level break; AN1776
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case asm(" ANDI.W case asm(" ANDI.W case asm(" ANDI.W ORI.W #0xF4FF,SR" ORI.W #0xF5FF,SR" ORI.W #0xF6FF,SR" #0x0700,SR", Enable level break; #0x0700,SR", Enable level break; #0x0700,SR", Enable level break; #0x0700,SR", Enable level break;
case default: asm(" ORI.W ANDI.W #0xF7FF,SR"
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ip_level
Record value
7.5.4 audio.h
COPYRIGHT MOTOROLA 1998 FILE NAME: audio.h Header file containing definitions audio files. INCLUDE FILES: none DESCRIPTION: This header file containing definitions constants used audio input (ain.c) audio output (aout.c) files. This code intended demonstration purposes only guaranteed function given application. COMPILER: Crosscode VERSION: AUTHOR: Allan Dobbin LAST EDIT DATE: 10/Jun/98 LOCATION: East Kilbride, Scotland. UPDATE HISTORY AUTHOR DATE DESCRIPTION CHANGE Dobbin 10/Jun/98 First release file. Constants aout #define BUFF_SIZE size aout buffer long words #define BUFF_MAX change speed when buffer full #define BUFF_MID change speed when buffer full #define BUFF_MIN change speed when buffer full AN1776 MOTOROLA
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Freescale Semiconductor, Inc. Application Note
Define QSPI output rate delay before=22, delay after=8x32=256. Total word time (4x16) 342. This equal QADC sampling rate. Slow rate system clocks. Fast rate system clocks. Slow fast used dynamically adjust QSPI output rate allow small variations between clocks audio input audio output. #define SLOW 0x9708 #define NORMAL 0x9608 #define FAST 0x9508 definitions Standard format used i.e. ID's consist bits. Five separate ID's will exist audio match five message buffers used audio routine (ain). audio mask will `don't care' 3-bit audio number (0.4). #define AUDIO0_ID 0x0000 ID=000 0000 0000 RTR=0 RSVD=0000 #define AUDIO1_ID 0x0001 ID=000 0000 0001 RTR=0 RSVD=0000 #define AUDIO2_ID 0x0002 ID=000 0000 0010 RTR=0 RSVD=0000 #define AUDIO3_ID 0x0003 ID=000 0000 0011 RTR=0 RSVD=0000 #define AUDIO4_ID 0x0004 ID=000 0000 0100 RTR=0 RSVD=0000 #define AUDIO_MASK 0xFF0FFFFE Clear MID18-20 mask audio lsbs
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7.5.5 regs.h
COPYRIGHT MOTOROLA 1998 FILE NAME: regs.h Header file containing definitions registers. INCLUDE FILES: none DESCRIPTION:*/ This header file containing definitions registers type definitions. Only registers used audio functions declared here. This code intended demonstration purposes only guaranteed function given application. COMPILER: Crosscode VERSION: AUTHOR: Allan Dobbin LAST EDIT DATE: 10/Jun/98 LOCATION: East Kilbride, Scotland.
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UPDATE HISTORY AUTHOR DATE DESCRIPTION CHANGE Dobbin 10/Jun/98 First release file. General constants #define TRUE #define FALSE #define ENABLE #define DISABLE
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define register bits #define BIT0 0x0001 #define BIT1 0x0002 #define BIT2 0x0004 #define BIT3 0x0008 #define BIT4 0x0010 #define BIT5 0x0020 #define BIT6 0x0040 #define BIT7 0x0080 #define BIT8 0x0100 #define BIT9 0x0200 #define BIT10 0x0400 #define BIT11 0x0800 #define BIT12 0x1000 #define BIT13 0x2000 #define BIT14 0x4000 #define BIT15 0x8000 Type Definitions typedef unsigned long LWORD; typedef volatile unsigned long VLWORD; typedef unsigned short WORD; typedef volatile unsigned short VWORD; typedef unsigned char BYTE; typedef volatile unsigned char VBYTE; union BYTE2{ WORD BYTE b[2]; union BYTE4{ LWORD WORD w[2]; BYTE b[4]; union BYTE8{ LWORD l[2]; WORD w[4]; BYTE b[8]; AN1776 MOTOROLA Declare byte union readable byte, word
Declare byte union byte, word lword
Declare byte union byte, word lword
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Freescale Semiconductor, Inc. Application Note
Register Definitions 683xx family, 0xFFFFF000 more efficient than 0x00FFF000. Change 0x007FF000 MM=1 #define reg_base 0xFFFFF000 QADC Module #define QADC_base (reg_base+0x200)
Freescale Semiconductor, Inc.
typedef volatile struct BYTE no[80]; byte_table; typedef volatile struct WORD no[40]; word_table; typedef volatile struct LWORD no[20]; lword_table; #define #define #define #define #define #define #define #define #define #define #define #define QADCMCR (*(WORD QADC_base) QADCINT (*(WORD (QADC_base+0x4)) QACR0 (*(WORD (QADC_base+0xA)) QACR1 (*(WORD (QADC_base+0xC)) QACR2 (*(WORD (QADC_base+0xE)) QASR (*(VWORD (QADC_base+0x10)) (WORD (QADC_base+0x30) RJURR (*(byte_table (QADC_base+0xB0)) RJURRW (*(word_table (QADC_base+0xB0)) RJURRL (*(lword_table (QADC_base+0xB0)) LJSRR (*(byte_table (QADC_base+0x130)) LJURR (*(byte_table (QADC_base+0x1B0)) Queue complete flag
#define CF2_CLR 0xDFFF
module (QSPI, SCI) #define QSM_base (reg_base+0xC00) typedef volatile struct BYTE data[32]; tr_struct; typedef volatile struct BYTE data[16]; cr_struct; allow tran treated bytes
allow command treated bytes
AN1776
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#define QSMCR (*(WORD (QSM_base+0x00)) #define QILR (*(BYTE (QSM_base+0x04)) #define QIVR (*(BYTE (QSM_base+0x05)) #define PORTQS (*(VBYTE (QSM_base+0x15)) #define PQSPAR (*(BYTE (QSM_base+0x16)) #define DDRQS (*(BYTE (QSM_base+0x17)) #define #define #define #define #define #define #define SPCR0 (*(WORD (QSM_base+0x18)) SPCR1 (*(WORD (QSM_base+0x1A)) SPCR2 (*(WORD (QSM_base+0x1C)) SPCR3 (*(BYTE (QSM_base+0x1E)) SPSR (*(VBYTE (QSM_base+0x1F)) TRANRAM (*(tr_struct (QSM_base+0x120)) COMMRAM (*(cr_struct (QSM_base+0x140))
General registers
port
QSPI sub-module
Freescale Semiconductor, Inc.
TouCAN module #define TCAN_base (reg_base+0x080) typedef volatile struct WORD control; WORD WORD time; union BYTE8 data; WORD reserved; can_msg_buf; #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define AN1776 MOTOROLA structure access buffer
allows access data byte, word long
CANMCR (*(VWORD (TCAN_base+0x00)) CANICR (*(WORD (TCAN_base+0x4)) CANCTRL0 (*(BYTE (TCAN_base+0x6)) CANCTRL1 (*(BYTE (TCAN_base+0x7)) PRESDIV (*(BYTE (TCAN_base+0x8)) CANCTRL2 (*(BYTE (TCAN_base+0x9)) TIMER (*(VWORD (TCAN_base+0xA)) RXGMSK (*(LWORD (TCAN_base+0x10)) RX14MSK (*(LWORD (TCAN_base+0x14)) RX15MSK (*(LWORD (TCAN_base+0x18)) ESTAT (*(VWORD (TCAN_base+0x20)) IMASK (*(WORD (TCAN_base+0x22)) IFLAG (*(VWORD (TCAN_base+0x24)) RXECTR (*(VBYTE (TCAN_base+0x26)) TXECTR (*(VBYTE (TCAN_base+0x27)) (*(can_msg_buf (TCAN_base+0x80)) (*(can_msg_buf (TCAN_base+0x90)) (*(can_msg_buf (TCAN_base+0xA0)) (*(can_msg_buf (TCAN_base+0xB0)) (*(can_msg_buf (TCAN_base+0xC0)) (*(can_msg_buf (TCAN_base+0xD0)) (*(can_msg_buf (TCAN_base+0xE0)) (*(can_msg_buf (TCAN_base+0xF0)) (*(can_msg_buf (TCAN_base+0x100)) (*(can_msg_buf (TCAN_base+0x110)) MB10 (*(can_msg_buf (TCAN_base+0x120)) MB11 (*(can_msg_buf (TCAN_base+0x130))
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Freescale Semiconductor, Inc. Application Note
#define #define #define #define MB12 MB13 MB14 MB15 (*(can_msg_buf (*(can_msg_buf (*(can_msg_buf (*(can_msg_buf (TCAN_base+0x140)) (TCAN_base+0x150)) (TCAN_base+0x160)) (TCAN_base+0x170))
7.5.6 toucan1.h
COPYRIGHT MOTOROLA 1998 FILE NAME: toucan1.h SYNOPSIS: Header file containing definitions toucan functions. INCLUDE FILES: none DESCRIPTION: This header file containing definitions constants fields used toucan.c file. This code intended demonstration purposes only guaranteed function given application. COMPILER: Crosscode VERSION: AUTHOR: Allan Dobbin LAST EDIT DATE: 10/Jun/98 LOCATION: East Kilbride, Scotland. UPDATE HISTORY AUTHOR DATE DESCRIPTION CHANGE Dobbin 10/Jun/98 First release file. Function prototypes void toucan_MB_off (void); TouCAN MB's inactive void toucan_bus_on (void); turn TouCAN release MB's clear HALT void toucan_init_global (void); Initialise TOUCAN global regs reset void set_ip (int); Enables interrupts setting
Freescale Semiconductor, Inc.
Constants TouCAN TouCAN Message Buffer codes #define RX_DISABLE 0x00 buffer active #define RX_ENABLE 0x40 buffer active #define RX_FULL 0x20 buffer full #define RX_OVER 0x60 buffer overrun #define RX_BUSY 0x01 buffer busy AN1776
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#define #define #define #define #define TX_DISABLE TX_ENABLE TX_REM_REQ TX_REM_REP TX_EN_REM_REP 0x80 0xC0 0xC0 0xA0 0xE0 buffer buffer buffer buffer buffer active active remote transmission request remote transmission reply active, then remote reply
Freescale Semiconductor, Inc.
following static parameters passed TouCAN initialisation function initialise global registers CANMCR register #define DISABLE Enables debug mode during #define WAKEMSK DISABLE Configure wake-up interrupts #define SUPV Supervisor access TouCAN: 0=USER, 1=SUPERVISOR #define SELFWAKE DISABLE Configure self-wake enable #define DISABLE Configure auto power save #define CAN_IARB2 TouCAN Interrupt arbitration, 1-15 interrups enabled CANICR register #define ILCAN #define IVBA CANCTRL0 register #define BOFFMSK DISABLE #define ERRMSK DISABLE #define RXMODE #define TXMODE
Configure TouCAN level. 0=disabled, 7=highest priority Configure interrupt vector base address,
Configure Configure Configure Configure
interrupt mask error interrupt mask control, control,
CANCTRL1 register Loop mode longer supported TouCAN. #define SAMP Configure sampling mode: 0=ONE SAMPLE, 1=THREE SAMPLES #define TSYNC DISABLE Configure timer reset #define LBUF Configure 1st: 0=LOWEST 1=LOWEST #define PROPSEG TIMING: propagation (-1): PRESDIV register #define PRES_D CANCTRL2 register #define #define PSEG1 #define PSEG2 TIMING FSYS 20MHz 1MHz PRES_D PROPSEG(+1) PSEG1(+1) PSEG2(+1)) (1+6+6+7)
TIMING: clock prescal divide factor (-1): 0-255
TIMING: resync jump width (-1): TIMING: phase segment (-1): TIMING: phase segment (-1):
AN1776 MOTOROLA
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Freescale Semiconductor, Inc. Application Note References
following documents referred this applications note. Motorola document (BCANPSV2.0/D) MC68336/376 User's Manual (MC68336/376UM/AD) programming Language, Kernighan Ritchie, Prentice Hall Programming Microcontrollers Sickle, Hightext publications inc.
Freescale Semiconductor, Inc.
AD1866 specification, Analog Devices PCA82C250 objective specification, Phillips Semiconductors
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Freescale Semiconductor, Inc.
Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters which provided Motorola data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. Motorola registered trademarks Motorola, Inc. Motorola,
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