AN1758 Freescale Semiconductor, Inc. Addressable Switches HC
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AN1758
Freescale Semiconductor, Inc.
Addressable Switches HC05
Mark Glenewinkel Field Applications Engineering Consumer Systems Group Austin, Texas
Introduction
This application note describes interface between HC05 microcontroller (MCU) DS2405 addressable switch from Dallas Semiconductor Corporation. address structure uses 1-Wireinterface that reduces overhead control, data, address, power pins. DS2405 combines these functions. DS2405 provides means assigning identification particular node location with additional control capability open-drain N-channel MOSFET. This MOSFET switch remotely addressed turned 1-Wire bus. This structure allows user number switches simply adding twisted pair cable containing 1-Wire signal ground. 1-Wire interface also used with DS2407. This device similar DS2405. addition DS2405 features, switchable MOSFETS 1024 bits user-programmable Onetime-programmable EPROM. This allows user information about system switch hooked This information easily read over 1-Wire identify switch system properties.
1-Wire trademark Dallas Semiconductor Corporation.
Motorola, Inc., 1998
AN1758
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Freescale Semiconductor, Inc. Application Note
Circuitry example code provided Code Listing demonstrate interface between DS2405 HC05. Although example code given DS2407, serial drivers 1-Wire make easy user application-specific functions utilize additional features DS2407.
DS2405 DS2407 Features
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DS2405 Features
DS2405 provides these features: Open drain controlled matching 64-bit, laser-engraved registration number associated with each device Logic level open drain output determined over 1-Wire closed-loop control sink capability greater than Multiple DS2405s identified switched independent other devices Unique, factory-lasered tested 64-bit registration number assures that parts alike. Reduces control, address, data, power single data Directly connects single port microcontroller Communicates 16.3 Kbits second Zero standby power required Low-cost TO-92 6-pin TSOC package 1-Wire communicates over wide voltage range from
DS2407 Features
addition those features DS2405, DS2407 provides these features: Dual switches available with TSOC package
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Application Note Description
Better current sink capability: Channel Channel 1024 bits user one-time programmable (OTP) EPROM Seven bytes user-programmable status memory control device
Freescale Semiconductor, Inc.
Description
DS2405 64-bit lasered that unique each device. first bits signify 1-Wire family member being addressed. next bits unique each DS2405 device allowing over trillion different devices field. last eight bits (cyclic redundancy check) first bits. 64-bit allows multiple DS2405s bus. 1-Wire network controller circuitry search algorithm embedded determine identity each device bus. Once code device matched, toggled open-drain N-channel MOSFET. logic level each device also sensed reported back host bus.
DS2405 Hardware Interface
Pinout Descriptions
DS2405
Figure DS2405 TO-92 Pinout
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DATA
Freescale Semiconductor, Inc. Application Note
bidirectional DATA only interface microcontroller. Parasitic power derived from required pullup resistor DATA pin. other power input needed DS2405. data transceived between master DS2405 read written least significant (LSB) first.
Block Diagram
PARASITIC POWER
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1-WIRE DATA
1-WIRE FUNCTION CONTROL
64-BIT LASERED
CONTROL
OPEN-DRAIN MOSFET
Figure DS2405 Block Diagram 1-Wire Interface Figure shows hardware interface 1-Wire bus. single master more slave devices. cases, DS2405 slave. important that each device able drive appropriate time. Thus, each device must have open drain three-state outputs. maximum rate allowed 16.3 Kbits second. idle state high. reason transaction suspended, must left idle state transaction resume later time. held more than more slave devices could reset. pullup resistor required
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Application Note DS2405 Hardware Interface
ensure proper idling provide parasitic power DS2405.
MASTER DATA DS2405 1-WIRE PORT
PORT DIRECTION
Freescale Semiconductor, Inc.
Figure 1-Wire Interface
1-Wire Timing
1-Wire protocol divided into types transactions. These are: Reset presence pulse Write read data
When device idling high state, master starts communicating DS2405 issuing reset pulse. master must drive least After this time, master turns port into high impedance input allows pullup resistor bring back high. Over next master reads looking low. DS2405 active ready communicate, will drive low. master does receive presence pulse, further communication cannot occur. Figure shows reset presence pulse timing.
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Freescale Semiconductor, Inc. Application Note
MASTER VPullup VPullup tRSTL
RESISTOR
DS2405
RESISTOR tRSTH
tPDL
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tPDH tRSTL tRSTH INFINITE, INCLUDES RECOVERY TIME tPDH tPDL
Figure Reset Presence Pulse Timing After presence pulse received, data communicated between master slave. transceived specific time slots that initiated master sending falling edge sync pulse. sync pulse defines start time slot that least long. After this time slot finished, recovery time least required give DS2405 time respond next being transmitted. time slot recovery time together which defines maximum communication speed 16.3 Kbits second. Three different time slots generated. They are: Write-one time slot Write-zero time slot Read data time slot
timing diagrams these time slots shown Figure Figure Figure
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Application Note DS2405 Hardware Interface
MASTER VPullup VPullup tSlot tLOW1 tREC INFINITE tLOW1
RESISTOR
DS2405 SAMPLING
tSlot
tREC
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Figure Write-One Time Slot
MASTER VPullup TLOW0 tSlot tLOW0 tSlot tREC INFINITE tREC DS2405 SAMPLING VPullup RESISTOR
Figure Write-Zero Time Slot
MASTER VPullup tSlot tLOWR tRelease tREC INFINITE tRDV tLOWR tRDV tSlot tRelease tREC MASTER SAMPLING VPullup RESISTOR DS2405 RESISTOR
Figure Read Data Time Slot
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Freescale Semiconductor, Inc. Application Note
step-by-step example protocol needed match DS2405's 64-bit code master transmits reset pulse. master waits presence pulse from DS2405. Once detected, step master sends match command DS2405. code match %01010101 sent first.
Freescale Semiconductor, Inc.
Write-one Write-zero Write-one
Write-zero Write-one Write-zero
Write-one Write-zero After match function been sent, DS2405 will toggle pin. transaction complete. issue another command, DS2405 must reset again.
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Application Note DS2405 Software Interface
DS2405 Software Interface
transaction sequence access DS2405 over 1-Wire illustrated Figure
1-WIRE INITIALIZATION
Freescale Semiconductor, Inc.
1-WIRE FUNCTION READ MATCH SEARCH ACTIVE-ONLY SEARCH SKIP
READ DATA
Figure DS2405 Transaction Sequence Initialization transactions start with device initialization routine. This accomplished master sending reset pulse then reading presence pulse from DS2405.
Function Commands Read
Once master detected presence pulse, commands issued. functions eight bits long. This command allows master read DS2405's unique 64-bit code. This command only used there single DS2405 bus. Otherwise, data collision will occur. 1-Wire devices have this 64-bit lasered ROM. first eight bits signify 1-Wire family. next bits unique DS2405. last eight bits (cyclic redundancy check) first bits. Consult DS2405 data sheet more detail 64-bit ROM. more than DS2405 bus, this command allows master address specific DS2405. DS2405 that exactly matches 64-bit sequence will toggle pin. open-drain
Match
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Freescale Semiconductor, Inc. Application Note
N-channel device off, will Likewise, will off. other devices will inactive until reset pulse sent. After last been read been toggled, additional read data time slots will cause DS2405 transmit logic state pin. pulldown device turned logic DS2405 will transmit read data time slot. pulldown device turned logic DS2405 will transmit read data time slot. external pullup resistor required bring high when MOSFET been turned off. Additional read data time slots will indicate state until reset pulse sent bus. Search When system many devices bus, master know number devices their 64-bit codes. This command allows master determine contents devices bus. search command uses tedious process elimination determine identity devices bus. 3-step process used each 64-bit code. steps are: master reads position 64-bit code. master reads complement position. With this information, master writes match those devices that have same value. This turn deselects other devices that have matched bit. This process repeated until eventually devices eliminated except device that matches exactly 64-bit code that just transmitted. Once device found, master issue read data time slots read pin. process started over find next device bus. search command deserves further treatment beyond scope this application note. Consult DS2405 data sheet more detailed explanation this command.
Freescale Semiconductor, Inc.
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Application Note DS2405 Software Interface
Active-Only Search
active-only search command very similar search command. difference that this command only searches devices that have their MOSFET turned pulled low. Consult DS2405 data sheet more detailed explanation this command. protocol 1-Wire includes command bypass 64-bit code. This useful only device bus. Many 1-Wire devices have other functions that different each device. skip command shortens access time needed execute internal functions particular device. Since DS2405 contains only 64-bit with additional data fields functions, skip command applicable DS2405.
Skip
Freescale Semiconductor, Inc.
Memory
DS2405 memory other than 64-bit code. code shown Figure
8-BIT CODE
48-BIT SERIAL NUMBER
8-BIT FAMILY CODE ($05)
Figure DS2405 Memory
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Freescale Semiconductor, Inc. Application Note MC68HC705J1A Hardware Interface
This application note uses MC68HC705J1A (J1A) member HC05 Family test interface between DS2405 HC05. With only pins, smaller members HC05 Family. MC68HC705J1A has:
Freescale Semiconductor, Inc.
1240 bytes erasable programmable read-only memory (EPROM) bytes Timer pins
schematic used testing J1A-to-DS2405 interface MMEVS development system shown Figure port used transmit receive data DATA DS2405. further information HC705J1A, consult MC68HC705J1A Technical Data.
DS2405 MMEVS INTERFACE DATA
Figure DS2405 Interface Test Circuit
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Application Note MC68HC705J1A Software Interface
MC68HC705J1A Software Interface
driving manipulation process toggling pins with software instructions create certain hardware peripheral. HC05 provides special instructions specifically manipulate single pins. serial transmission driver been into three subroutines:
Freescale Semiconductor, Inc.
RESET_PULSE Sends reset pulse DS2405 waits presence pulse. presence pulse found, routine goes into error loop. Takes byte data creates eight time slots either write-one write-zero, depending being transmitted. Transmits eight read data time slots. Each read shifted into byte RAM.
flowcharts DS2405 serial drivers shown Figure Figure Figure flowchart main test routine Figure step-by-step sequence tests Read ROM. This command asks DS2405 64-bit code bus. loop retrieve total eight bytes. Store each byte into buffer DS2405_ROM. location DS2405_ROM+7 will have contents code. location DS2405_ROM will have contents code. Match ROM. This command allows user select DS2405 toggle pin. loop transmit total eight bytes. Transmit each byte from buffer DS2405_ROM starting first. Execute command. This will read value pin.
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Freescale Semiconductor, Inc. Application Note
high (MOSFET turned off), value DS2405_PIO will $FF. (MOSFET turned on), value DS2405_PIO will $00. toggle pin, restart code step This routine demonstrates interface software needed communicate with DS2405. Although used, HC05 device could utilize this interface code. Minor adjustments port pins memory maps might necessary.
Freescale Semiconductor, Inc.
assembly code test routine provided Code Listing.
Development Tools
interface created tested using following development tools. M68MMPFB0508 Motorola MMEVS platform board M68EM05J1A Motorola emulation module Version 1.02 Editor, assembler, debugger Microcomputer Systems
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Application Note Flowcharts Serial Drivers
Flowcharts Serial Drivers
RESET_PULSE
DATA START RESET PULSE
WAIT LOOP,
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MAKE DATA INPUT
CLEAR TEST AccA LOOP
DATA DELAY LOOP
PRESENCE PULSE DETECTED TEST
DECREMENT AccA
AccA
DS2405 DEAD TEST YES, DS2405 ALIVE DATA MAKE DATA OUTPUT ERROR LOOP
RETURN FROM
Figure RESET_PULSE Subroutine Flowchart
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Freescale Semiconductor, Inc. Application Note
COUNTER 8-BIT TRANSMIT
DATA START TIME SLOT
SHIFT RIGHT BUS_WRITE CARRY BUS_WRITE
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CARRY DATA
DATA
DRIVE DATA
DATA
DECREMENT
YES, TRANSMISSION DONE RETURN FROM
Figure Subroutine Flowchart
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Application Note Flowcharts Serial Drivers
COUNTER 8-BIT TRANSMIT
DATA START TIME SLOT
MAKE DATA INPUT
Freescale Semiconductor, Inc.
WAIT DS2405 DRIVING DATA
DATA CARRY DATA ROTATE RIGHT BUS_READ PUTS CARRY INTO BUS_READ
WAIT COMPLETE TIME SLOT
DATA MAKE DATA OUTPUT
DECREMENT
YES, RECEIVED 8-BIT DATA RETURN FROM
Figure Subroutine Flowchart
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Freescale Semiconductor, Inc. Application Note
START
INITIALIZE PORTA DATA DIRECTION PORTA
TRANSMIT RESET_PULSE
READ_ROM
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COUNTER
READ BYTE, BUS_READ
STORE BUS_READ DS2405_ROM+COUNTER OFFSET
DECREMENT COUNTER
COUNTER
YES, LOOP DONE CODE BEEN INTO DS2405_ROM BUFFER
Figure Flowchart Main Test Routine (Sheet
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Application Note Flowcharts Serial Drivers
TRANSMIT RESET_PULSE
MATCH_ROM
COUNTER
Freescale Semiconductor, Inc.
LOAD DS2405_ROM+COUNTER OFFSET STORE BUS_WRITE
BUS_WRITE
DECREMENT COUNTER
COUNTER
YES, LOOP DONE CODE BEEN TRANSMITTED BEEN TOGGLED READ READ BYTE DS2405_PIO
INFINITE LOOP
Figure Flowchart Main Test Routine (Sheet
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Freescale Semiconductor, Inc. Application Note Code Listing
File name: DS2405.ASM Example Code MC68HC705J1A Interface Dallas DS2405 Addressable Switch Ver: Date: June 1998 Author: Mark Glenewinkel Motorola Field Applications Consumer Systems Group Assembler: 1.02 code explanation flow charts, please consult Motorola Application Note "Add Addressable Switches Microcontroller System" Literature AN1758/D NOTE: timing functions based 2MHz internal clock SYSTEM DEFINITIONS EQUATES Internal Register Definitions PORTA ;PortA DDRA ;data direction PortA Application Specific Definitions DATA DATA_DIR Function Commands READ_ROM MATCH_ROM SEARCH_ROM ACT_SEARCH_ROM SKIP_ROM Memory Definitions EPROM RESET
Freescale Semiconductor, Inc.
;PortA, data signal ;PortA Data DATA signal
;read ;match ;search ;active-only search ;skip
$300 $07FE
;start EPROM ;start ;vector reset
VARIABLES BUS_WRITE ;storage byte write BUS_READ ;storage byte read TEST ;test result presence
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Application Note Code Listing
DS2405_PIO DS2405_ROM
COUNTER
;PIO level ;power-on reset makes high ;storage DS2405 64-bit code ;DS2405_ROM ;DS2405_ROM+7 ;temporary counter
Freescale Semiconductor, Inc.
MAIN ROUTINE EPROM ;start begining EPROM Intialize Ports START #$01 ;init PORTA PORTA #$01 ;config outputs PORTA DDRA Issue "READ ROM" command RESET_PULSE #READ_ROM BUS_WRITE ROM_Cycle1 COUNTER BUS_READ COUNTER DS2405_ROM,x COUNTER ROM_Cycle1
;send reset
;send Read
;set counter bytes ;receive data from byte
;store byte read into DS2405_ROM ;loop done?
Issue "MATCH ROM" command RESET_PULSE #MATCH_ROM BUS_WRITE ROM_Cycle2 COUNTER
;send reset
;send Match
;set counter bytes
COUNTER DS2405_ROM,x BUS_WRITE COUNTER ROM_Cycle2 Read DS2405, read BUS_READ DS2405_PIO DUMMY DUMMY AN1758 MOTOROLA
;read byte from DS2405_ROM ;transmit data ;loop done? ;receive data from byte ;store result DS2405_PIO ;test sequence over byte
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Freescale Semiconductor, Inc. Application Note
SUBROUTINES Routine creates reset pulse then checks presence pulse from DS2405 presence pulse, goto error loop Create greater then µsec reset pulse RESET_PULSE bclr DATA,PORTA #160T wait µsec deca bclr DATA,DDRA ;DATA input Wait greater than µsec, look presence pulse, TEST will equal presence detected TEST #69T ;wait µsec brset DATA,PORTA,J3 DATA=1? bset 0,TEST DATA=0, presence detected TEST deca branch same time decrement Acca done?
Freescale Semiconductor, Inc.
Check TEST, TEST=$01, then TEST=$00, then goto error routine brset 0,TEST,J5 ERROR3 ERROR3 bset DATA,PORTA bset DATA,DDRA
;TEST ;presence pulse detected, error ;TEST passed, DATA=1 ;DATA output
Routine takes contents BUS_WRITE transmits serially serially bus, first ;set counter Drive DATA=0 µsec WRITE bclr bset bclr
DATA,PORTA BUS_WRITE DATA,PORTA DATA,PORTA
DATA=0, start time slot Carry DQ=1 branch clock_it ;5DQ=0 ;3evens
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Application Note Code Listing
this point, 10.5 µsec expired either being transmitted DATA must wait least 49.5 µsec, routine below µsec #17T deca Make sure DATA=1, then wait more than µsec recovery time bset DATA,PORTA DATA=1 decx WRITE bits transmitted? ;return from
Freescale Semiconductor, Inc.
Routine clocks read data from DATA, first contents BUS_READ ;set counter Drive DATA=0 µsec, READ bclr DATA,PORTA bclr DATA,DDRA Wait µsec, then sample DATA deca read data wait µsec brclr DATA,PORTA,J10 BUS_READ
DATA=0, start time slot make DATA input
carry DATA carry into BUS_READ
this point, 15.5 µsec expired since time slot started must wait least 44.5 µsec, routine below µsec #15T deca Make sure DATA=1, then wait more than µsec recovery time bset DATA,PORTA DATA=1 bset DATA,DDRA make DATA output decx READ bits received? ;return from
VECTOR TABLE RESET START
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Freescale Semiconductor, Inc. Application Note References
MC68HC705J1A Technical Data, Motorola document order number C68HC705J1A/D, 1996. M68HC05 Applications Guide, Motorola document order number M68HC05AG/AD, 1996. DS2405 Datasheet, Dallas Semiconductor Corporation, 1997.
Freescale Semiconductor, Inc.
DS2407 Datasheet, Dallas Semiconductor Corporation, 1997.
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