AN1744 Freescale Semiconductor, Inc. Resetting Microcontroll

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AN1744 Freescale Semiconductor, Inc. Resetting Microcontroll

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AN1744
Freescale Semiconductor, Inc.
Resetting Microcontrollers During Power Transitions
Greg Racino Consumer Systems Group Austin, Texas
Introduction
simple function such resetting during application removal power cause many problems handled properly. Symptoms improperly handled reset during power transitions range from slight delay response after power-up very erratic, inconsistent behavior total system failure. This document covers main issues relating this problem aims lead user HC05, HC08, HC11 devices safe reliable approach transitioning power their application. Although information this application note applies most HC05, HC08, HC11 devices, some variations sources reset implementation internal circuits exist. Consult pertinent device specification addition this document make sure your system will operate properly during power transitions.
Motorola, Inc., 1998
AN1744
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Freescale Semiconductor, Inc. Application Note Document Outline
Reset most basic function ensures that starts restarts executing software code controlled manner. This document covers those situations that related resetting when power applied removed from MCU. does cover general system protection features such (computer operating properly), illegal instruction reset, illegal address reset except where pertains directly guaranteeing safe reliable power transition. general these types protection features covered other application notes. These factors determine whether will receive proper reset signals, both internally externally generated, during power transitions: Influences reset during power-up: power-on reset function (POR) System power-up sequence Oscillator startup time effects delay
Freescale Semiconductor, Inc.
External reset Low-voltage reset (LVR) Effects (mask option register) (onetime programmable) devices
Influences reset during power down: System protection mechanisms Low-voltage reset (LVR) Protecting non-volatile memory
most applications, several reset sources occur same time. combination these must considered safe operation application.
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Application Note Document Outline
Influences During Power-Up
power begin executing software controlled manor, certain sequence events must occur beginning with power-on reset circuit. Referring Figure Figure will help explain sequence events that occurs inside outside during power-up sequence.
Freescale Semiconductor, Inc.
Power-On Reset Function (POR)
power-on reset function accomplished through several circuits inside MCU. three main components this function are: circuit counter chain logic Internal reset logic Refer Figure block diagram components within MCU. HC05s, HC11s, HC08s contain internal circuit. purpose circuit pre-condition certain logical circuits within begins rise. circuits that preconditioned circuit internal reset generation logic counter chain logic.
NOTE:
circuit itself does hold reset predetermined amount time, combination circuit, counter chain logic, MCU's reset logic will create power-on delay (tPOR shown Figure
seen Figure internal signal operates only during early stages power-up. fact, just above voltage level required CMOS logic begin recognizing logical states, this signal will longer asserted. mechanism that negates internal signal feedback from circuits that indicating that initialization completed. This takes place short period time early power-up sequence. Once circuit initializes reset logic, which turn asserts internal reset signal, counter delay logic holds reset state 4064 (HC05 HC11) 4096 (HC08) oscillator clock
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Freescale Semiconductor, Inc. Application Note
cycles during power-up sequence. This referred most databooks oscillator stabilization time. time, tPOR, will vary depending crystal frequency used, voltage which oscillations start, rise time. Because purpose circuit only precondition internal circuits/logic, will detect loss power MCU. fact, voltage must fall level much below logic operating level, usually about remain there several tens milliseconds re-arm itself detect next rise VDD. temporary loss VDD, sometimes called brown-out, cause internal logic storage elements change state thus potentially disrupt proper operation. this case, which covered this application note's section Influences Reset During Power Down page circuit required protect give clean reset.
Freescale Semiconductor, Inc.
System Power-Up Sequence
begins experience rising voltage pin, several things begin happen: Once reaches level sufficient CMOS logic begin operating (~1-V range, typically), internal oscillator circuits will begin oscillate regardless type oscillator used (crystal, ceramic resonator, resistor capacitor (RC), etc.). This voltage given term VOS. Once oscillator (and hence internal systems clocks) begin run, internal logic that must initialized during power-up must correct logical state. this point, counter chain reset logic will continue assert internal reset signal period 4064 (HC05 HC11) 4096 (HC08) clock cycles. Once this period time (which depends oscillator frequency) expired, circuit will negate input into reset logic. other sources reset occur, will come reset will begin executing code.
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Application Note Document Outline
RESET INTERNAL RESET SIGNAL
OTHER RESET SOURCES LVR, COP, ILLADDR, ETC.
RESET LOGIC
CIRCUIT COUNTER CHAIN LOGIC OSC1 CLOCK
Freescale Semiconductor, Inc.
SYSTEM CLOCK GENERATION
PERIPHERAL CLOCKS
OSC2
Figure Internal Power-On Reset Functional Blocks When relying only provide initialization during powerup, rate which rises (the slew rate) becomes very important. important make sure VRun reaches exceeds MCU's minimum operating voltage, VDDMIN, chosen oscillator frequency ambient operating temperature before time tPOR shown Figure This simple equation help calculate slew rate sufficient. HC05s HC11s: 4064 slewrate HC08s: 4096 slewrate
these equations, VRun never exceed level VDD.
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Freescale Semiconductor, Inc. Application Note
VRUN VDDMIN
INTERNAL RESET
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INTERNAL SIGNAL
OSC2
tPOR
INTERNAL CLOCK 4064 HC05/HC11 CYCLES 4096 HC08 CYCLES INTERNAL CLOCK
oscillator clock rate number clock cycles drawn scale. These internal signals shown active high; instance, they cause internal reset condition when high. time between point when begins rise point which internal clock starts.This includes time oscillator begin oscillating, does include stabilization time. tPOR 4064 (HC05 HC11) 4096 (HC08) internal clock cycles voltage which internal logic begins operate. instance, oscillator will begin start clock begin run. VDDMIN Minimum operating voltage specification particular oscillator frequency temperature specification VRun voltage which MCU's clocks start will begin execute code
Figure Proper Power-Up Sequence
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Application Note Document Outline
fOSC frequency crystal, resonator, external clock source connected MCU. Recall that VRun voltage which MCU's will attempt execute code perform intended functions. These equations assume that clock will start running when reaches VOS. This worse case condition will case when external clock already present powering Example:
Freescale Semiconductor, Inc.
HC05 with rise VOS= fOSC= 4064 VDDMIN specification greater than then this slew rate low. solution either speed slew rate hold reset some other means until reaches VDDMIN.
Effects Oscillator Startup Time
previous example, rise time fast enough, example then VRun would easily exceed VDDMIN. this case, will begin execute code after oscillator starts when using 2-MHz crystal (4064/2 MHz). When using MCU's internal crystal oscillator circuit crystal frequency 4-MHz range, oscillator startup time typically will vary depending components used, board layout, levels, slew rate. When using lower frequency crystals, such 32.768 kHz, startup time much longer 300- 500-ms range very lowpower oscillator circuits long seconds. main concern crystal startup time comes applications with rapid power-up, required begin executing code very quickly. these cases, reliable startup usually problem, since often will rise safe levels (VRun VDDMIN) before oscillator starts before tPOR. rises fast enough make significant contributor startup time, then oscillator startup time should assumed
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Freescale Semiconductor, Inc. Application Note
cases when rising moderate rate tPOR about same oscillator startup time, best assume that oscillator will start immediately when reaches VOS. Take precautions make sure held reset state until safely reaches VDDMIN.
External Reset
Freescale Semiconductor, Inc.
counter chain times MCU's level safe operating range, some other mechanism (either internal external) continue hold reset state until reached VDDMIN. mentioned earlier, VDDMIN level will depend MCU's voltage, temperature, frequency specifications. case external reset pin, simple low-cost ensure that device stays reset long enough delay reset shown Figure component values must chosen create enough delay keep RESET input below specification (typically VDD) until reaches VDDMIN. consideration when choosing values ensure that R1's value does high interfere with ability drive RESET high given worst case input leakage current pin. example, Kohms, input leakage specification then input voltage RESET will minimum (100 This would acceptable, values could possibly create input level RESET that would below specification. addition, capacitor also should large when using MCUs that have active internal RESET pull down device. this case, surge current from into RESET when pull down device turns large damage circuitry. general, limiting this current less than will sufficient.
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Application Note Document Outline
this example circuit, diode used quickly discharge capacitor when falls. This helps ensure proper RESET input subsequent power-up, should occur soon after power down. general, external network approach only practical rise time fairly fast. slow, values must large, costly, interfere with normal operation. When designing RESET circuitry, consider this signal shared with other components within system. many MCUs, RESET actively driven when internal reset condition exists. Knowing what active drive characteristics should also considered when calculating value
Freescale Semiconductor, Inc.
+VDD RESET
>VDDMIN RESET
RESET (0.2 TYPICALLY) TIME
Figure Circuit External Reset Low-Voltage Reset external circuit suitable means generating external RESET signal during power-up also desired reset during power down during brown-out condition, then low-voltage reset best choice.
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Freescale Semiconductor, Inc. Application Note
function low-voltage reset circuit continuously monitor MCU's voltage level generate reset signal ever falls below certain trigger voltage, VLVRINH (see Figure circuit will continue hold reset until voltage reaches another trigger voltage called recovery voltage, VLVRRCV. difference between VLVRRCV VLVRINH called hysteresis, VLVRHYS. VLVRHYS exists ensure does bounce reset with small amounts noise which typically exist system. VLVRHYS usually
Freescale Semiconductor, Inc.
low-voltage reset come from either internal external source RESET (see Figure does have internal circuit, then externally generated performed with device such Motorola MC34064, MC34164, MC33464, MC33465 series. Sometimes MCU's internal circuit that performs this function called (low-voltage inhibit). Most time, VLVRIHN VLVRRCV trip points circuit fixed single voltages. trigger levels internal suitable prevent device from operating outside voltage, frequency, temperature specification, then external must used. Since rise fall times many systems vary greatly, internal circuits designed balance quiescent operating current response time. rises falls extremely fast, then circuit generate reset input precisely specified VLVRIHN VLVRRCV trip points. case rising VDD, VLVRRCV trip point will appear little higher than that specified VLVRIHN trip point will appear little lower. reliable power down power-up concerned, this problem rise, could pose problem fall slew rate exceeds about V/ms. many HC05 HC08 MCUs with internal circuit, counter chain cleared prevented from counting while output asserted. This provides extra stabilization time allowing rise little higher extra operating voltage margin. This seen Figure internal reset signal. addition, HC08, oscillator also prevented from starting while reset asserted.
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Application Note Document Outline
VLVRRCV VLVRINH VLVRHYS
OUTPUT
Freescale Semiconductor, Inc.
INTERNAL RESET
INTERNAL SIGNAL
OSC2
INTERNAL CLOCK 4064 HC05/HC11 CYCLES SOME HC05/HC11s
OSC2
INTERNAL CLOCK 4064 HC05/HC11 CYCLES 4096 HC08 CYCLES HC08s SOME HC05/HC11s VLVRRCV Low-voltage recovery voltage. voltage which circuit output negated. VLVRINH Low-voltage inhibit voltage. voltage which circuit output asserted. VLVRHYS Low-voltage reset hysteresis voltage. difference between recovery inhibit voltage. These internal signals shown active high; example, they cause internal reset condition when
Figure Low-Voltage Reset Operation
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Freescale Semiconductor, Inc. Application Note
Effects Mask Option Register Devices Several Motorola MCUs with internal circuits have version that uses some sort internal non-volatile memory main user memory: MC68HC705xx MC68HC805xx MC68HC908xx
Freescale Semiconductor, Inc.
These commonly referred (one-time programmable) devices. Because these devices have through mask cycle fabrication process install application software select mask options, mask options some MCUs implemented same non-volatile memory cells that used build main memory array. non-volatile register that contains mask option bits called mask option register (MOR). Many times, enable/disable will present MOR. During power-up periodically thereafter, these non-volatile, bits read periodically refreshed. logical state nonvolatile copied into static latch. output static latch controls circuitry which connected. Since some HC05 MCUs with internal circuits were designed originally excessively slow rise fall times, this pose problem these applications because signals that enable available until reaches 2.0- 2.5-V level internal clocks begin run. There reasons this: First, many times bits built into main memory array MCU's internal clocks must running voltage must sufficient level read memory array. Second, level required read non-volatile memory usually higher than that required read mask programmed option bit. Consequently, operation bits only guaranteed down specific level.
result, with enable/disable will work better emulate functions during power down than during powerAN1744 More Information This Product, www.freescale.com MOTOROLA
Application Note Document Outline
However, also limitations during power down. those cases, will operate properly point. Then, refresh operation, turn LVR, which could release internal reset signal. rise fall times slow, then best external circuit RESET external circuit when dealing with some HC05 devices. mask equivalent device, used safely power-up well power down. case MC68HC908xx Family MCUs, enable/disable bit, which implemented with only static latch non-volatile bit, contained CONFIG register. This initialized enable during reset must turned software operation required. This approach robust during power transitions immune sudden severe transients brown-out conditions implementation, which uses non-volatile with periodic refresh.
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Influences Reset During Power Down
addition encountering problems during power-up, application designer also must consider possibility operating incorrectly system powering down.
System Protection Mechanisms
Fortunately, there robust means protecting system during power loss that readily available. Among them computer operating properly (COP) function, illegal address reset (IAR), illegal instruction reset (IIR,) circuit. COP, IAR, available nearly HC05, HC11, HC08 devices should used protect system only during power transitions under normal operating conditions. begins fall, begin operate outside specified operating range (VDD falls below VDDMIN). When this happens, internal circuits perform expected could result performing erratically erroneously. COP, IAR, use, then will receive reset before operates under this
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Freescale Semiconductor, Inc. Application Note
condition very long. take anywhere between several cycles, even several hundreds thousands cycles, before reset from COP, IAR, will asserted. case reset, depends when last serviced. case IIR, will depend long takes erroneous data read from memory interpreted CPU. There predict long this will take. many applications, especially those which falls rapidly, this issue, since many clock cycles will elapse during power down time.
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During Power Down
applications which tolerant even single erroneous cycle, either internal external will protect system even further. shown Figure VLVRINH voltage above minimum operating voltage VDDMIN, then system will forced into reset once falls unsafe level.
Protecting Non-Volatile Memory
MCU's common subsystems on-chip erasable programmable EEPROM FLASH memory particularly vulnerable permanent data corruption during power loss. This only problem when on-board memory process being altered (programmed erased) during power down. Since usually takes more perform program erase operation, there wide window opportunity lose power interrupt program erase sequence. Even system makes prevent erratic operation during power down, there guarantee that program erase operation complete successfully before reset occurs. preventing this problem circuit hardware source reset serve indicator software. many devices, status polled predict when started fall, software decide whether program erase operation time occur before below VDDMIN. Once decision action have been taken, software into reset using external circuitry.
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Application Note Document Outline
Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc. Application Note
Freescale Semiconductor, Inc.
Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters which provided Motorola data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. Motorola registered trademarks Motorola, Inc. Motorola, Inc. Equal Opportunity/Affirmative Action Employer.
reach USA/EUROPE/Locations Listed: Motorola Literature Distribution, P.O. 5405, Denver, Colorado 80217, 1-800-441-2447 1-303-675-2140. Customer Focus Center, 1-800-521-6274 JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 141, 4-32-1 Nishi-Gotanda, Shinigawa-Ku, Tokyo, Japan. 03-5487-8488 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd., Ping Industrial Park, Ting Road, N.T., Hong Kong. 852-26629298 MfaxTM, Motorola Back System: RMFAX0@email.sps.mot.com; http://sps.motorola.com/mfax/; TOUCHTONE, 1-602-244-6609; Canada ONLY, 1-800-774-1848 HOME PAGE: http://motorola.com/sps/
Mfax trademark Motorola, Inc. Motorola, Inc., 1998
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AN1744 Freescale Semiconductor, Inc. Resetting Microcontroll

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