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AN2333/D Rev. 10/2002 Maximizing Performance Fast Ethernet Links MSC8101 FCCs
Philippe Chartier
Freescale Semiconductor, Inc.
CONTENTS
IEEE 802.3 Ethernet Basics. Ethernet Transceiver. Media Independent Interface (MII). MSC810ADS FCCs Running Ethernet Control Data path FCCs Project Hardware Set-up Software Modules. Software Configuration Options Performance Accesses MSC8101 Internal SRAM. Buffers Buffer Descriptors. Interrupt Service Routine Interrupt Handler Timer Statistics. Results Conclusions Performance Tool. Related Reading
This application note describes implement dual full-duplex Fast Ethernet driver MSC8101ADS board. examines on-board Ethernet transceiver configuration fast communication controller (FCC) Ethernet configuration MSC8101. considers different ways optimize these configurations illustrates them with example MSC8101 data processing set-up that yields high performance terms Ethernet link bandwidth. Example code provided with this application note reusable rapidly integrated into projects real-time operating system (RTOS) board software package (BSP).
IEEE 802.3 Ethernet Basics
Ethernet most widely used local area network (LAN) technology specified IEEE 802.3 standard. Ethernet different media: coaxial cable, unshielded twisted pair copper wires, radio frequencies, fiber, These Ethernet work different frequencies, such Mbps, Mbps, Gpbs, even Gbps/s. Operating computers, terminal equipment, other devices that interconnect between them switch. Devices connect medium compete access using carrier sense multiple access with collision detection (CSMA/CD) protocol. Ethernet frame structured follows: 7-byte preamble alternating ones zeros. Start frame delimiter (SFD) that marks beginning frame. 48-bit destination address 48-bit source address. Ethernet type IEEE 802.3-length field that signifies protocol. Length field that specifies length data portion frame. Ethernet IEEE 802.3 frames exist same LAN, length field must unique Ethernet. This requirement limits length data portion frame 1,500 bytes therefore total frame length 1,518 bytes. Data (46-1500 bytes). Four-byte frame-check sequence (FCS), which standard 32-bit CCITT-cyclic reduncancy check (CRC) polynomial used many protocols.
Frame Length 64-1,581 Bytes Start Frame Delimiter Byte Destination Address Bytes Source Address Bytes Type Length Bytes Frame Check Sequence Bytes
Preamble Bytes
Data 46-1500 Bytes
Figure Ethernet Frame Format
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IEEE 802.3 Ethernet Basics
Ethernet Transceiver
most systems, Ethernet medium accessed from controller through Ethernet transceiver. This section discusses Ethernet transceiver MSC8101ADS configured also describes interface between this transceiver MSC8101. MSC8101ADS uses LXT970 Ethernet transceiver access 10/100 Base-T Ethernet port that ends with standard RJ-45 Ethernet jack. main features this Ethernet transceiver follows: IEEE 802.3 compliant. Base-T Base-TX using single RJ-45 connection. Support auto negotiation Media-independent interface (MII) with extended register capability.
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100Base-FX fiber optic capable. Standard CSMA/CD full-duplex operation. Configurable serial port external control pins. Configurable switch applications. Integrated drivers. Ethernet transceiver hardware configuration pins determine default behavior transceiver when connected line. These pins also provide transceiver with 5-bit address. MSC8101 device interconnects through pins, MDIO, that provide bidirectional serial access device registers configuration. Several Ethernet transceivers share MDIO serial interface signals long they have different addresses. Also, Ethernet transceivers from same manufacturers have common base subset registers, facilitating their control software design.1 Table shows transceiver registers bits that must configured. Table Main Transceiver Registers
Register
Register Control Register
Bits
0.15 Reset chip 0.14 Enable Loopback 0.13 Link Speed Selection 0.12 Auto-Negotiation Mode Enable 0.09 Restart Auto-Negotiation Process 0.08 Link Duplex Mode Link Status (Up/Down) 100BASE-TX full-duplex capable 100BASE-TX half-duplex capable 10BASE-T full-duplex capable 10BASE-T half-duplex capable 4.4:0 Selector Field <00001> IEEE 802.3 20.12 Duplex Mode 0.11 Speed
Register Status Register Register Auto-Negotiation Advertisement Register
Register Chip Status Register
details, Intel® data sheet LXT970/970A Fast Ethernet transceiver, which available http://www.intel.com under Networking Communications Design Components.
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IEEE 802.3 Ethernet Basics
Media Independent Interface (MII)
There different interconnect formats interfacing Ethernet controllers transceivers, such MII, reduced media independent interface (RMII), serial media independent interface (SMII). MSC8101 FCCs format. Table Table show device pinout FCC2 FCC1. parentheses delineate pinout MSC8101ADS board. Table FCC2 Device Pinout Board Pinout
Port Line
Port (D04) Port (C01)
Function
CLK4/TX_CLK TX_ER TX_EN TXD0 TXD1 TXD2 TXD3
Direction
Function
FCC2 Ethernet FCC2 Ethernet FCC2 Ethernet FCC2 Ethernet FCC2 Ethernet FCC2 Ethernet FCC2 Ethernet
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Port (C03) Port (C10) Port (C09) Port (C08) Port (C07)
Port (D03) Port (C04) Port (C02) Port (C11) Port (C12) Port (C13) Port (C14)
CLK3/RX_CLK RX_ER RX_EN RXD0 RXD1 RXD2 RXD3
FCC2 Ethernet FCC2 Ethernet FCC2 Ethernet FCC2 Ethernet FCC2 Ethernet FCC2 Ethernet FCC2 Ethernet
Port (C06) Port (C05)
FCC2 Control Ethernet FCC2 Control Ethernet
Port (D20) Port (D19)
MDIO
In/Out
PHY2 Management PHY2 Management
Table
Port Line
Port (PC31) Port (PA29) Port (PA28) Port (PA21) Port (PA20) Port (PA19) Port (PA18)
FCC1 Device Pinout Board Pinout
Direction
Function
CLK2/TX_CLK TX_ER TX_EN TXD0 TXD1 TXD2 TXD3
Function
FCC1 Ethernet FCC1 Ethernet FCC1 Ethernet FCC1 Ethernet FCC1 Ethernet FCC1 Ethernet FCC1 Ethernet
Port (PC30) Port (PA26) Port (PA27)
CLK1/RX_CLK RX_ER RX_EN
FCC1 Ethernet FCC1 Ethernet FCC1 Ethernet
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IEEE 802.3 Ethernet Basics
Table
Port Line
Port (PA17) Port (PA16) Port (PA15) Port (PA14)
FCC1 Device Pinout Board Pinout (Continued)
Function
RXD0 RXD1 RXD2 RXD3
Direction
Function
FCC1 Ethernet FCC1 Ethernet FCC1 Ethernet FCC1 Ethernet
Port (PA30) Port (PA31)
FCC1 Control Ethernet FCC1 Control Ethernet
Port (D20)
MDIO
In/Out
PHY1 Management PHY1 Management
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Port (D19)
MSC810ADS FCCs Running Ethernet
MSC8101 communications processor module (CPM) includes fast communication controllers (FCCs) that operate Ethernet mode 100Mbits/s. features these FCCs, which make easy SC140 core handle Ethernet payload traffic, follows:2 layer functions fast Ethernet IEEE 802.3x Framing functions Full collision support rates MBPS Multi-buffer data structure generation Logical. 64-bin group address hash table plus broadcast address checking Promiscuous mode Special RMON counters monitoring network statistics.3 This counters monitor receive side Ethernet mode. They provide approximate measure incoming network traffic without need implement software counters.
Control Data path
block diagram shown Figure gives overview different control data flows MSC8101-based systems Ethernet operation.
details MSC8101 FCCs, consult MSC8101 Reference Manual (MSC8101RM/D). details RMON counters, consult chapter Fast Ethernet Controllers MSC8101 Reference Manual (MSC8101RM/D).
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2FCCs Project
Ethernet Transceiver Analog
MSC8101 FCCx Interrupt Transport SC140 Core
Clock Generation Transmit Receive Ethernet Link Modulation Demodulation Ethernet Frames
Interrupt Generation Internal SRAM Data Framing Deframing Buffer Descriptors
Interrupt Management
Buffer Management Data Fabric
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Transmit Receive Buffers Collision Management GPIO Control Registers DPRAM Initialization Control Parameters
FCCx Initialization Transceiver Initialization
Transceiver Control
Figure Control Data Paths
2FCCs Project
This section describes hardware set-up software modules 2FCCs project.
Hardware Set-up
There example hardware configurations 2FCCs project. first uses MSC8101ADS boards, FCC1 available must disabled software project configuration file. second set-up involves both MSC8101ADS communication (ECOM) board, which peripheral extension board designed connect MPC8260ADS.4 FCC1 uses ECOM on-board Ethernet transceiver.
2.1.1 Two-MSC8101ADS Set-up
Figure shows, two-MSC8101ADS set-up defined follows: Crystal 16,384 MHz; MODCLK40 (yielding SC140 core/CPM/60x-compatible system speeds 196/98/39 MHz). switches factory defaults. with suitable ports (PCI parallel) JTAG probes download, tune, debug software. JTAG probe MSC8101ADS (Macraigor Systems LLC's OCDemonWiggler)5 twisted Ethernet cable Ethernet switch straight Ethernet cables
Documentation ECOM board available Motorola site listed back this document. Consult MPC8260 product information. Visit http://www.ocdemon.net/.
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2FCCs Project
JTAG Link MSC8101ADS Ethernet Link FCC2 PHY2 PHY2 FCC2
JTAG Link
MSC8101ADS
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Twisted Ethernet Cable NOTE: Ethernet link Straight Ethernet Cables.
Ethernet Switch
Figure Set-up Using MSC8101ADS Boards
2.1.2 MSC8101ADS ECOM Set-up
MSC8101ADS-ECOM set-up preferable two-MSC8101ADS set-up because allows MSC8101 device handle fast Ethernet connections over both FCC1 FCC2 simultaneously. MSC8101ADS-ECOM set-up that used 2FCC project described this application note. Note: ECOM also replaced second with same board interconnections. However, small piece code required second enable Ethernet transceiver disable local GPIO. code downloaded from directly from on-board Flash memory.
JTAG Link Connection FCC1 MSC8101ADS Ethernet Link FCC2 PHY2 PHY1 ECOM
Twisted Ethernet Cable NOTE: Ethernet link Straight Ethernet Cables.
Ethernet Switch
Figure Set-up Using MSC8101ADS ECOM Board
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2FCCs Project
Software Modules
Table Control Data Paths
FCC1 MSC8101ADS Signal
TX_ER RX_DV TX_EN RX_ER
PHY1 (for FCC1) ECOM Signal
FETHTXER FETHRXDV FETHTXEN FETHRXER FETHCOL FETHCRS FETHTXD3 FETHTXD2 FETHTXD1 FETHTXD0 FETHRXD1 FETHTXD0 FETHRXD0 FETHRXD1 FETHRXD2 FETHRXD3 FETHTXCK FETHRXCK RSTBRD 3.3V 5.0V PA29 PA27 PA28 PA26 PA31 PA30 PA21 PA20 PA19 PA18 PA17 PA16 PA15 PA14 PC20 PC21 PC10 PC09 HRESET 3.3V 5.0V
PA29 PA27 PA28 PA26 PA31 PA30 PA21 PA20 PA19 PA18 PA17 PA16 PA15 PA14 PC30 PC31 PC13 PC12 HRESET 3.3V 5.0V
Location
(P1) B01-B03 (P1) A[20-24] (P1) A[26-32] (P1)
Location
(P1) B01-B03 (P1) A[20-24] (P1) A[26-32] (P1)
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TXD3 TXD2 TXD1 TXD0 RXD0 RXD1 RXD2 RXD3 CLK2 CLK1 PC13 PC12 HRESET 3.3V 5.0V
This section describes 2FCCs software project, which available file. When this file expanded, project files located folder tree, Figure shows.
Root folder specific project Executable, memory linker README.txt Application note Source folder MSC8101ADS board support Ethernet Transceiver driver FCC1 running Ethernet Init. FCC2 running Ethernet Init. Runtime FCCs driver Init FCCs driver Interrupt controller Main project file Payload creation Standard Includes files Timer driver statistics
2FCCs_DATA BOARD_SUPPORT ENET_PHY FCC1_ENET FCC2_ENET FCCs_DRV FCCs_INIT INT_CRL MAIN PAYLOAD STD_INCLUDES TIMER
Figure Control Data Paths
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2FCCs Project
2FCCs project developed using Metrowerks® CodeWarrior® Windows. However, compiler independent therefore runs suitable IDE. Moreover, project host-independent Solaris, Linux, When project compiled, should generate neither errors warnings. executable file downloaded MSC8101ADS, where enter Debug mode step-by-step.
2.2.1 Board Initialization
Before executable image downloaded, MSC8101ADS must initialized command script directory. This script disables watchdog timer configures memory controller, enabling memory accesses. Then 2FCCs binary image downloaded into MSC8101ADS memory. example discussed here, downloaded into MSC8101 internal SRAM. Then SC140 core executes bootstrap code (provided compiler) until start main function. this point, program starts setting parallel ports GPIO inputs, resetting CPM, initializing interrupt controller. payloads dummy Ethernet frames, which contain source destination addresses, frame length, random payload. frame size determined compile time, FCCs transmit over Ethernet link.
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2.2.2 Ethernet Transceiver (PHY) Initialization
initialization performed twice, each Ethernet transceiver, follows: GPIO signals configured MDIO signals. this set-up MDIO signals common Ethernet transceivers. According input parameters, code configures each Mbps speed, half- full-duplex operation, auto-negotiation mode. output, link status returned and, relevant, results auto-negotiation.
2.2.3 Driver Initialization
driver initialization performed twice, once each FCC. This process configures work Ethernet mode programming following parameters: Configure external Ethernet modem. Configure General Mode Registers (GFMRx), which define options common FCC, regardless protocol select channel protocol mode. this case, Ethernet protocol selected: GFMRx[Mode2] 1100). clock route. clocks provided Ethernet transceivers internally routed correct FCC. Enable RMON frame counters statistics throughput calculation. Specify events which FCCs trigger interrupt. Connect interrupt handler interrupt controller. Initialize allocate buffers buffer descriptor memory. code configures work Promiscuous mode, mode need changed code reused.
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2FCCs Project
2.2.4 Interrupt controller
interrupt controller used here basic, performs required tasks: context saving, interrupt source determination, interrupt handler address match plus execution, context restoring. Before MSC8101 device enters normal run-time mode, interrupt controller configures MSC8101 programmable interrupt controller (PIC) SIU-CPM interrupt controller (SIC) handle both edge triggered interrupts. interrupt controller features switch either complete reduced context saving/restoring. reduced context switching requires fewer cycles, also requires interrupt handlers reduced SC140 registers. write interrupt handlers assembly language compiler options Figure shows, interrupts generated FCCs then transmitted SIC, which manages priorities serial (SDMA) peripherals. Then (PIC) manages interrupt.6 last, interrupt arrives SC140 core.
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2.2.5 Driver/Interrupt Handler
interrupt handler short function that first determines type interrupt (received transmitted frame/buffer, frame discarded, on). decision logic section depends application. application, simply receives sends frames without treatment. other applications, this decision logic might handle buffer management other tasks. Frame management occurs through buffer descriptors (BDs), which indicate buffer transmit, received frame, interrupt handler acknowledges interrupt setting appropriate bits value memory space which both driver have access. This memory space mapped structure convenience. contains information each transmit receive buffer, such status bits attributes), size bytes), address (pointer start buffer). conjunction with interrupt controller, there switch either complete reduced context saving/restoring. These switches must both cleared.
2.2.6 Timer Statistics
timer displays RMON frame counters window every seconds. procedure initializing this timer much like that initializing FCCs. During initialization, timer registers configured, timer interrupt handler connected interrupt controller. timer period crystal-dependent, check on-board crystal required. changes crystal MODCLK should reflected appropriate files.
Software Configuration Options
This section discusses files containing global parameters, with listings default values, which provide best throughput. 2FCCs.h. Enable/disable FCC1 FCC2: #define #define #define #define #define #define
FCC1_ENABLED FCC2_ENABLED FCC1_RX_ENABLED FCC2_RX_ENABLED FCC1_TX_ENABLED FCC2_TX_ENABLED
also manages priorities among rest MSC8101 peripherals.
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Performance
Timer.h. Reflects value on-board crystal: #define DIV16 #define BRG_VALUE Payload.h. Sets frame size: #define FRAME_SIZE_1 #define FRAME_SIZE_2 must even number must even number refer table
FCCs_Int_Handler.h. Uses hand-optimized (reduced register set) version: #define INTHANDLER
FCC1_ENET.h FCC2_ENET.h. Sets unsets internal loopback, sets address, determines number size buffers both transmit receive paths:
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#define FCCx_INTLPBK #define ENETx_PADDR_H #define ENETx_PADDR_M #define ENETx_PADDR_L #define FCCx_TX_BUF_SIZE #define FCCx_RX_BUF_SIZE #define FCCx_TX_NUM_BUF #define FCCx_RX_NUM_BUF
0x00E0 0x0C12 0x3472 //Physical Addr.1 (MSB) //Physical Addr.1 //Physical Addr.1 (LSB)
0x5EE //1518 decimal 0x5EE //1518 decimal
IRQ.h. Specifies normal reduced context switching: #define OPTIMIZATIONS parts 2FCCs project that remain follows: Most initialization board Most initialization Ethernet Most initialization FCCs interrupt controller normal mode parts 2FCCs project that need changed adapted follows: Buffer descriptor initialization Buffer management
Performance
MSC8101 target markets include media (voice/fax/data) over packet gateways. such embedded systems, packet traffic characterized moderate high bandwidth consumption. Packets usually shorter than bytes. MSC8101 Ethernet links, this traffic impact frequency interrupt, final throughput, packet latency. This section discusses optimize Ethernet parameter values. Modifications needed Ethernet network traffic differs from that described here.
Accesses MSC8101 Internal SRAM
SC140 core should memory offset access internal SRAM. Such access requires cycle. contrast, accessing SRAM CS10 memory offset 0x02000000 system requires many more cycles. setting memory offset default, which reconfigured. Read write operations consume four cycles, assuming SC140 core/bus speed ratio (MODCLK 40), such operations require SC140 core cycles
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Performance
because read write requests must cross Q2PPC bridge system bus/local bridge. This requirement directly affects MSC8101 internal loading global system speed, well memory space accessed both SC140 core CPM, such buffers buffer descriptors.
Buffers
MSC8101 buffers enable data transfers to/from to/from memory through SDMA transactions that transparent user. Buffers located three types memory: Internal SRAM. Provides rapid one-cycle access buffer. External SDRAM. Accesses buffer consume more SC140 core cycles free internal memory that payload fabric work temporary space internal SRAM while transfers occur to/from external SDRAM. This memory space increases frame latency. Internal DPRAM. This right choice applications which SC140 core does access data directly forward communications channel. Otherwise, offers advantages. This choice impact RSTATE register common parameters. complete MSC8101-based embedded system, choice memory location buffers trade-off based upon available internal SRAM SDRAM space, frame latency, load system bus/local bus, Buffers 4-bye aligned not, depending memory space allocation. communications channels (SCC, MCC, FCC) access their buffers SDMA. data transfers, alignment 4-byte boundary (for 32-bit systems such MSC8101) provides best performance. 2FCC project, these values yield best balance between SRAM consumption throughput. More buffers receive side allow greater burst frame; more buffers transmit side allow larger frame burst generation. course, allocating fewer buffers both receiving transmitting data saves memory space. simplify buffer management, allocate buffer frame rather than several buffers frame. This practice increases buffer size that memory space less flexible. However, depending Ethernet protocol, partial chunk checksum must computed (such UDP), allocating buffer frame results faster simpler algorithms because data always contiguous. buffer size 1500 (Ethernet MTU) (Ethernet encapsulation). When system connected unfamiliar environment, this safest choice. When system connected entirely defined environment, setting buffer size known maximum frame size saves memory space. allocating several buffers frame, size smaller value than known maximum frame size (for example, bytes). Because 2FCCs project must handle frame sizes range 64-1500 bytes, mandatory that buffer size 1500 (Ethernet MTU) (Ethernet encapsulation). Note: Once that points buffer full empty (for transmit buffers) empty fully (for receive buffers), neither SC140 core MSC8101 peripherals should write even read contents buffer. Doing result crash freeze and/or SC140 core.
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Performance
Buffer Descriptors
structures containing information buffer size, status, properties, pointers. provide means manage buffers. CPM/FCC reads writes SDMA transfers that transparent user. rings should located internal SRAM because they consume much memory they allow flexibility buffer servicing methods interrupt handler. Locating external SDRAM decreases system performance without offering advantages. Locating internal DPRAM offer advantage interrupt frequency, accesses DPRAM increase SC140 core cycle consumption latency. Also, locating internal DPRAM impact RSTATE common parameters. noted Section 3.2, rings should 4-byte aligned.
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transmit buffer descriptor three ways, setting direct impact interrupt frequency thus system global performance: each transmit buffer. soon smart buffer management buffer queuing system implemented, this choice must. 2FCCs project uses this option order count transmitted frames. last buffer transmit ring, which suitable basic systems. none, which simplifies design interrupt handler. receive buffer descriptor three ways: each receive buffer. soon smart buffer management buffer queuing system implemented, this choice must. last buffer receive ring, which suitable basic systems. none: polling. systems which main task intensive repetitive (such traffic aggregation), polling received buffers advantageous. interrupt mechanism then longer mandatory, system scheduler must implemented. Note: Once that points buffer full empty (for transmit buffers) empty fully (for receive buffers), neither SC140 core MSC8101 peripherals should write even read contents buffer. Doing result crash freeze and/or SC140 core.
Interrupt Service Routine
interrupt service routine (ISR) runs when SIU-CPM interrupt controller (SIC) generates interrupt. determines resource(s) responsible interrupt launches appropriate resource interrupt handler. routine encapsulated context saving restoring functions. Context switching either complete reduced, follows: Complete. normal conditions, complete register context saving/restoring consumes cycles. Reduced. 2FCCs project, number cycles decreased saving/restoring registers (r[0-7] d[0-7]). choice between reduced complete context switching direct impact Ethernet frame latency real-time aspects global system. Context switching great source errors, care must taken designing this module. Other important aspects ISRs that warrant consideration design time reentrance whether edge level triggered.
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Performance
decision logic implemented through either Interrupt Vector Register (SIVEC) through Interrupt Pending Register (SIPNR_H SIPNR_L), follows: SIVEC. This register contains 6-bit code representing unmasked interrupt source highest priority level. SIVEC results interrupt service that generic independent peripherals. SIPNR_H SIPNR_L. Each interrupt pending registers corresponds interrupt source. When interrupt received, interrupt controller sets corresponding SIPNR bit. These registers used conjunction with their respective mask (SIMR_H SIMR_L). these registers slightly improve performance. most compilers, defined adding line source code just before function definition, follows: "#pragma interrupt Name_of_the_ISR_function"
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interrupt handler function differs from other functions main ways. Context saving restoring surrounds function, runs Exception mode, forcing compiler generate instructions that differ slightly from instructions issued Normal mode.
Interrupt Handler
2FFC project, interrupt handler simple manager. complete system, would also provide hooks upper protocol layers (software) function entry point payload fabric. coding language either assembly assembly language permits reduction SC140 core cycles required when working with reduced context switching. Assembly code great source errors, especially ISR, care must taken writing Assembly code. language default option more portable more easily maintainable. There many possible buffer servicing methods interrupt handler. Calls interrupt handler consume SC140 core cycles. servicing method directly determines call frequency. Thus choice servicing method interrupt handler design critical system design. Buffers serviced time that each received transmitted buffer generates interrupt. This method result non-serviced buffer, which then breaks rings stops reception transmission. Such breakages occur high throughputs more than buffer transmitted received between Interrupt handler calls. Alternatively, buffers serviced once that each received transmitted buffer generates interrupt. This method consumes many SC140 core cycles ensures that buffers serviced that rings broken. third buffer service option minimum FCCINTHandler conjunction with dynamic buffer allocation/management. flag/semaphore separate handler launched scheduler/RTOS also added decrease cycles spent handler, thus improving real-time aspect global system. goal 2FCCs project provide simple example with high Ethernet throughput. Therefore, implements method servicing buffers time because simplicity. real, more complex systems, using minimum FCCINTHandler conjunction with dynamic buffer allocation/management similar schema) would necessary because flexibility. maximum reachable throughput should similar, regardless buffer servicing method. Note: reasons provided here, interrupt handler should reduce access FCCE other DPRAM registers/memory areas minimum make optimized code.
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Results Conclusions
Timer Statistics
default configuration, 2FCC project works with reduced context switching conjunction with interrupt handler. However, timer interrupt handler written potentially registers that saved when timer interrupt occurs. most systems, this would lead crashes, 2FCC project, main program empty infinite loop that executes instructions. Thus, fact that timer interrupt handler written impact.
Results Conclusions
direct application 2FCCs project benchmarking Voice over (VoIP) systems. array shown Table gives Ethernet frame size VoIP/G711 communications. test runs project different frame sizes, from 1500 bytes with several steps including values shown. hardware software assumptions this test described previous sections this document. Table G711 Figures Frame Size
G711 (Ms) Frequency (Hz) Voice payload (bytes) (bytes) (bytes) (bytes) Ethernet (bytes) Ethernet (bytes) Total size packet (bytes) Throughput full duplex channel (kbits/s) 249.6 156.8 110.4 87.2
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validity test limited. fact, software tool called CPM_Perf (see Section indicates that RISC processor does under normal conditions (saturation) when frame size less than approximately bytes. maximum MSC8101 speed configuration SC140 core/CPM/system 300/150/100 MHz, minimum frame size approximately bytes. calculations these scenarios results matrix 2FCCs test (Table Table 2FFCs Throughput Performances
G711 (Ms) Ethernet frame length FCC1 throughput (Mbits/s) FCC2 throughput (Mbits/s) Total throughput (Mbits/s) Interrupt frequency (1/s) Number channels 54.9 60.5 115.4 1803125 65.4 60.4 125.8 1612821 77.8 78.4 156.2 1593878 1217391 1522 89.3 89.3 178.6 819266 2048 94.8 94.8 189.6 379200 1000 96.8 96.8 193.6 193600 1500 97.2 97.2 194.4 129600
throughput divergence between FCCs confirmation expected limit (138 bytes) given CPM_Perf tool. full speed, this limitation disappears. Sometimes debugger window displayed message discarded frames because resynchronization after timer
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Performance Tool
interrupt, itself basic buffer management. expected, interrupt frequency increases when frame size decreases. This demonstrates need care both interrupt controller interrupt handler design. results obtained show high performance MSC8101 CPM. They prove that MSC8101 suitable most applications requiring high throughput. There technical ways increase Ethernet throughput. example, several packets concatenated into Ethernet frame, with additional software mechanisms control packet latency. Another would implement microcode and, even upper layers, encapsulation/desencapsulation RISC processor.
Performance Tool
This section describes test PowerQUICC product-based systems such MSC8101and MPC8260. four steps, possible know loads RISC processor internal buses (local 60x-compatible system bus): Launch CPM_Perf application, read first screen, then acknowledge.
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Figure Performance Tool, Opening Screen main screen, speed, speed, access scheme. Then, specify location buffer local (SRAM) (SDRAM, DPRAM).
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Performance Tool
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Figure Performance Tool, Screen speed, buffer size other parameters both FCC1 FCC2.
Figure Performance Tool, Screen
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Performance Tool
Directly watch results save them into text file.
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Figure Performance Tool, Screen assumptions underlying 2FCCs project settings follows: access schemes: System memory wait states Local memory wait states configuration: Data placed local (internal SRAM) Buffer descriptors placed local (internal SRAM) Receiver baud rate Mbps (Fast Ethernet) Transmitter baud rate Mbps (Fast Ethernet) Buffer length 1500 bytes frame fragmentation) Unaligned buffers (optimum) Table shows results simulations scenarios. Table Performance Tool Results
Speed Configuration Frame Size (Bytes)
CPM/Buses Clock 98/39 Busy
150.22 122.26 96.10 71.56
CPM/Buses Clock 150/100 Busy
98.15 79.87 62.79 46.75
Busy
75.11 61.13 48.05 35.78
Busy
49.07 39.94 31.39 23.38
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Related Reading
Table Performance Tool Results (Continued)
Speed Configuration Frame Size (Bytes)
1000 1500
CPM/Buses Clock 98/39 Busy
50.82 42.62 39.14
CPM/Buses Clock 150/100 Busy
33.20 27.84 25.57
Busy
25.41 21.31 19.57
Busy
16.60 13.92 12.79
Related Reading
MSC8101 Reference Manual, MSC8101RM/D, available website shown back cover this document. MSC8101ADS User's Manual, available website shown back cover this document. Ethernet quick reference, inspired from source available http://www.whatis.com Intel LXT970 data sheet (PDF document available http://developer.intel.com). Metrowerks Enterprise compiler documentation available with Metrowerks CodeWarrior® StarCore®.
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NOTES:
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AN2333/D

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