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Order Number AN2144/D: Rev. 6/12/2001 Programming MSC8101 Periodi


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Order Number AN2144/D: Rev. 6/12/2001
Programming MSC8101 Periodic Interrupt Timer (PIT)
Liccese
Contents
Periodic Interrupt Timer Set-up
Baud-Rate Generator Parallel Ports Timer Clock Periodic Interrupt Timer Interrupt Programming Model. Interrupt Handler Model datatypes.h source. msc8101.h source pit.c source.
Handling Interrupts
Freescale Semiconductor, Inc.
This document describes steps configuring Baud-Rate Generator (BRG) registers, Parallel Port registers, Periodic Interrupt Timer (PIT) registers, SIU-CPM Interrupt Controller (SIC) registers, Programmable Interrupt Controller (PIC) registers generate interrupts. System Interface Unit (SIU) timers, Time Counter (TMCNT), same clock source, TIMERSCLK, which derived from several sources. This application note describes set-up necessary Baud-Rate Generator (BRG) clock source Timer Clock PIT. This document also describes set-up necessary enabling handling interrupts.
Programming Example
Motorola, Inc. 1996, 2001
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Programming MSC8101 Periodic Interrupt Timer (PIT)
Figure illustrates integration MSC8101 clock synthesizer, BRG, timer clock, signals required registers used clock timer.
PostDiv, System PostDiv, SC140 core PreDiv
Baud-Rate Generator
Parallel Programming BRGC1 BRGC1 [EXTC] [DIV] BRGC1 [CD] Parallel Programming
Timers Clock
PISCR [PTF]
Freescale Semiconductor, Inc.
PC[27]
Clock Source Multiplex
Divide
Pre-scale BRG1CLK 1-4096
Clock Source Multiplex
Divide
Divide Source Mulitplex
TMRSCLK
Divide
BRGCLK
PC[26]
Divide
PISCR [PTE]
PITC
Delay Lock Loop
Clock Enable
16-Bit Modulus Counter
PISCR[PS]
Interrupt period (PITC TMRSCLK Frequency
SPLL [MF]
Multiplication Factor
PISCR[PIE]
Periodic Interrupt Timer
SPLL [PDF]
Pre-Divide Factor
MSC8101 Clock Synthesizer
Figure Clocking Diagram
Periodic Interrupt Timer Set-up
subsections that follow walk through main sections clocking diagram shown Figure describe procedure each.
Programming MSC8101 Periodic Interrupt Timer (PIT)
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Baud-Rate Generator
Baud-Rate Generator
Communications Processor Module (CPM) contains eight independent, identical baud-rate generators with Fast Communications Controller (FCC), Serial Communication Controller (SCC), Serial Management Controller (SMC). clocks produced BRGs sent bank-of-clocks selection logic, where they routed controllers. output also routed external (see Figure clock source BRGCLK external clock. BRGCLK internal signal generated MSC8101 clock synthesizer specifically BRGs. BRGCLK times clock; clock, based MODCLK settings, runs MHz, then BRGCLK runs MHz. This section describes parallel port registers BRGCLK source that produces 32.768KHz BRG1 clock source timer clock. MSC8101 Clock synthesizer module discussed. However, keep mind that MODCLK configuration uses crystal produce BRGCLK 6.25 BRG. MODCLK setting chosen mode (see page MSC8101 Reference Manual volume revision June 2000 details). MODCLK setting used. This chosen simply illustrate setup within source. With on-board crystal MHz, setting MODCLK mode System Clock Control Register (SCCR) division factor bits (30-31) (divide produces 6.25 BRGCLK BRG. Table
Table MODCLK Mode
Component/Register Bits Crystal SPLL[DF] (divide SPLL[MF] (multiply SCCR[DF] (divide 16.25 (BRG1 clock) Frequency
Freescale Semiconductor, Inc.
only that used clock source timer clocks BRG1. configure BRGCLK source BRG1, BRGC1[16-17]:ETXC bits Next, determine value Clock Divider, BRGC1[19-30]:CD bits. clock divider presets internal 12-bit counter that decrements DIV16 output rate. When counter reaches zero, reloaded with value 0xFFF produces minimum clock rate (divide 4096) while value 0x000 produces maximum rate (divide Since ours 32.768 BRG1 clock, with BRGCLK 6.25 bits 0x0BE, effectively dividing BRGCLK (0xBE+1), resulting BRG1 clock approximately 32.723 KHz. BRGC1[31]:DIV16 selects divide-by-1 divide-by-16 prescaler before reaching clock divider. demonstration, this (divide since have already achieved desired BRG1 clock rate. enable count, BRGC1[15]:EN bit. BRGC1 begins generating 32.723 clock. value actually loaded into BRGC1 0x0001017C. This completes set-up BRG1, timer clock's source clock.
Programming MSC8101 Periodic Interrupt Timer (PIT)
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Parallel Ports
Parallel Programming
BRGC1 BRGC1 [EXTC] [DIV]
BRGC1 [CD]
PC[27] BRGCLK
Clock Source Multiplex
Divide
Pre-scale 1-4096
BRG1CLK
Freescale Semiconductor, Inc.
Figure Baud-Rate Generator
Parallel Ports
supports four general-purpose (GPIO) ports, A-D. Each ports configured GPIO signal dedicated peripheral interface signal. Port unique that eight pins generate interrupts interrupt controller. Whether operates GPIO dedicated peripheral depends settings Port Assignment Register (PPARx). Each independently configured GPIO corresponding PPARx cleared dedicated peripheral set. configured input corresponding control Port Data Direction Register (PDIRx) cleared output set. PPARx PDIRx bits cleared system reset. Data written Port Data Register (PDATx) stored output latch. port configured output, output latch gated onto port pin. When PDATx read, port itself read. Port Open-Drain Register (PODRx) determines whether corresponding actively driven output open-drain driver. Clearing PODRx configures actively driven output, setting PODR configures open-drain driver. Port Special Options register (PSORx) bits effective only corresponding PPARx bits (dedicated peripheral). With corresponding PPARx set, PSOR cleared selects dedicated peripheral option PPARx set, then dedicated peripheral option selected.1 source example configures PPAR, PSOR, PDIR, PODR registers follows:
PSORC 0x00000000 PDIRC 0x00000005 PPARC 0x00000001 PODR 0x00000000 Port pins option Configures PC[31] PC[29] outputs other Port pins inputs Configures PC[31] dedicated peripheral (BRG1) Dedicated output pins actively driven output
Refer Tables 41-1 through 41-4 MSC8101 Reference Manual proper configuration port pins.
Programming MSC8101 Periodic Interrupt Timer (PIT)
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Periodic Interrupt Timer
Port pins [31] [29] used debug purposes only. PortC[31] monitors BRG1 clock signal, PORTC[29] output toggled within interrupt service routine (ISR) monitor period.
Timer Clock
Timer Clock module generates TIMERSCLK signal TMCNT timers. source TIMERSCLK derived from several external sources BRG1. TIMERSCLK source selected setting Parallel Port registers Periodic Interrupt Status Control Register (PISCR).1 application discussed here, desired TIMERSCLK 8.192 KHz. produce this desired interval using 32.723 source, PISCR Periodic Interrupt Frequency (PTF) (14) This results divide producing approximately 8.192 TIMERSCLK signal.
Freescale Semiconductor, Inc.
Parallel Programming
BRG1CLK
Clock Source Multiplex
Divide
PISCR [PTF]
Divide Source Mulitplex
TMRSCLK
Divide
PC[26]
Figure Timer Clock
Periodic Interrupt Timer
Periodic Interrupt Timer (PIT) consists 16-bit counter clocked TIMERSCLK. 16-bit counter decrements zero when loaded with value from Count register (PITC). After counter reaches zero, PISCR[PS] interrupt generated, PISCR[PIE] set. next input clock edge, value PITC again loaded into counter process repeats. When value loaded into PITC, updated, divider reset, counter begins counting. Setting PISCR[PS] creates pending interrupt that remains pending until PISCR[PS] cleared. write PITC stops current countdown, count resumes with PITC value. PISCR[PTE] cannot count retains count value.
parallel port configuration, refer section Parallel ports Chapter MSC8101 Reference Manual.
Programming MSC8101 Periodic Interrupt Timer (PIT)
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Periodic Interrupt Timer
Periodic Interrupt Timer Count Register (PITC) contains bits loaded into modulus counter.Since TIMERSCLK generating 8.192 KHz, generate period 10ms write 0x00510000 PITC register. Using PITC Period formula shown Figure following values: period (pitc TIMERSCLK period (81+1)/8192 period 0.010 (every 10ms generates interrupt)
PITR, read-only register that shows current count down value PIT. This counter affected reads.
PISCR [PTE]
Freescale Semiconductor, Inc.
PITC
TIMERSCLK
Clock Enable
16-Bit Modulus Counter
PISCR[PS]
Interrupt period (PITC TMRSCLK Frequency
PISCR[PIE]
Figure Periodic Interrupt Timer
Handling Interrupts
MSC8101 interrupt scheme consists three different interrupt controllers: Programmable Interrupt Controller (PIC), which operates SC140 core SIU-CPM Interrupt Controller (SIC), which generates interrupt requests External SIU-CPM Interrupt Controller (SIC_EXT), which generates interrupt requests external host CPU.
receives interrupts from internal sources such TMCNT, from from external sources such port parallel pins interrupt requests (IRQs). generates interrupt requests handled SC140 core. receives interrupts from peripherals, DMA, external IRQ[2-3], EONCE SIC. When detects interrupt request (IR) more inputs, arbitrates each according priority level location generates following: signal SC140 core, indicating that input requested interrupt service from SC140 Core. RIPL[2-0] signal indicating priority
Programming MSC8101 Periodic Interrupt Timer (PIT)
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Interrupt Programming Model
entry predefined vector address (VAB), determined location
Programming System Interface Unit (SIU) mask registers, SIMR_H SIMR_L, provides means masking interrupt requests core. Each SIMR corresponds interrupt source. enable interrupt; write corresponding SIMR bit. When masked interrupt source pending interrupt request, corresponding Interrupt Pending Register (SIPNR) set, even though interrupt generated core. Pending unmasked interrupts presented core order priority. interrupt vector that allows core locate Interrupt Service Routine (ISR) made available core reading Interrupt Vector Register (SIVEC). interrupt controller passes interrupt vector corresponding highest priority, unmasked, pending interrupt. registers fall into three categories:
Freescale Semiconductor, Inc.
Interrupt controller registers control configuration, prioritization, masking interrupts include registers determining interrupt sources. System configuration protection registers configures SIU, defines base address internal memory map, configures watchdog timer, specifies characteristics, well general functionality local buses; such arbitration, error status, control. Periodic Interrupt registers configure provide status periodic interrupts.
peripheral module serve NMIs received from MSC8101 peripherals pins. memory mapped SC140 Core accessed SC140 Core QBus. peripheral (Qbus) interface provides control status registers address decoding generation. serves total NMIs. Each configured edge-triggered level-triggered assigned priority range through where priority masks interrupt. system reset masked configured level-triggered. addition Core Status Register (SR) bits effectively disabling interrupts.
Interrupt Programming Model
interrupt programming model, applies toward interrupts, consists following steps:
interrupt table base address Vector Base Address (VBA) register Clear previous interrupt (sipnr_h 0x00000002) Enable interrupt (simr_h 0x00000002) Clear previous interrupt Pending Register (IPRB 0x00000000) Configure Edge/Level-Triggered Priority Register (ELIRE) enable IRQ16 (SIC interrupt) (ELIRE (ELIRE 0xFFF0) 0x0003 IRQ16 level-triggered, IRQ16 priority level Configure Core Status Register (SR) permit level interrupts (sr_h 0xffbf) Locate interrupt handler (ISR) appropriate offset (VBA+0x0c00) Enable Interrupts (ei)
Programming MSC8101 Periodic Interrupt Timer (PIT)
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datatypes.h source
Interrupt Handler Model
programming model handling interrupt consists following steps:
Clear Periodic Interrupt Status bit, PISCR[PS] (8); Remember this when PISR count Writing PISCR[PS] clears this bit. (piscr 0x0080) Clear interrupt Interrupt Pending Register (sipnr_h 0x00000002) Clear interrupt Interrupt Pending Register (iprb 0x0001) Execute handler. example simply toggle PC[29] monitor period. (pdatc 0x0004)
Freescale Semiconductor, Inc.
Programming Example
datatypes.h source
/*-* File: datatypes.h Description: This file contains general data definitions software shared Netcomm software group. *-*/ GENERAL CONSTANTS DEFINITIONS #define #define #define #define TRUE FALSE
/*-*/ Fundamental Data Types /*-*/ typedef typedef typedef typedef typedef typedef typedef typedef typedef typedef typedef typedef typedef typedef char unsigned short unsigned long unsigned unsigned volatile volatile volatile volatile volatile volatile volatile BYTE; UBYTE; HWORD; short UHWORD; WORD; long UWORD; char BOOL; char char unsigned short unsigned long unsigned unsigned VBYTE; VUBYTE; VHWORD; VUHWORD; VWORD; VUWORD; VBOOL;
char short long char
Programming MSC8101 Periodic Interrupt Timer (PIT)
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msc8101.h source
msc8101.h source
#include "datatypes.h" /*-* File: MSC8101.H Description: Main Internal Memory Maps MSC8101. Notes: Different structures overlaid same offsets different modes operation. Tested with MSC8101 Enterprise Compiler. Please retest different compiler used. This file does support Aparameter (i.e. structure that begins with pram.atm). This Enterprise compiler does support packing bytes inside structure. *-*/ #ifndef _MSC8101_H #define _MSC8101_H PARAMETER (PRAM) EACH PERIPHERAL Each subsection contains protocol-specific PRAM each peripheral, followed PRAM common protocols that peripheral. These structs used needed main MSC8101 memory structure. Note that different modes operation will require different PRAM structs, that certain structs overlay conflict with other PRAM areas. Consult MSC8101 Reference Manual details what unavailable when certain protocols certain peripherals. /*-*/ SERIAL COMMUNICATION CONTROLLER (SCC) /*-*/ /*-*/ HDLC /*-*/ typedef struct VUBYTE reserved1[4]; Reserved area VUWORD c_mask; constant VUWORD c_pres; preset VUHWORD disfc; discarded frame counter VUHWORD crcec; error counter VUHWORD abtsc; abort sequence counter VUHWORD nmarc; nonmatching address VUHWORD retrc; frame transmission counter. this area reserved.*/ VUHWORD mflr; maximum frame length VUHWORD max_cnt; maximum length counter VUHWORD rfthr; received frames threshold VUHWORD rfcnt; received frames count VUHWORD hmask; user defined addr mask VUHWORD haddr1; user defined address VUHWORD haddr2; user defined address
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Programming MSC8101 Periodic Interrupt Timer (PIT)
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msc8101.h source
VUHWORD haddr3; VUHWORD haddr4; VUHWORD tmp; VUHWORD tmp_mb; t_HdlcScc_Pram; /*-*/ Ethernet /*-*/ typedef struct VUWORD c_pres; VUWORD c_mask; VUWORD crcec; VUWORD alec; VUWORD disfc; VUHWORD pads; VUHWORD ret_lim; VUHWORD ret_cnt; VUHWORD mflr; VUHWORD minflr; VUHWORD maxd1; VUHWORD maxd2; VUHWORD maxd; VUHWORD dma_cnt; VUHWORD max_b; VUHWORD gaddr1; VUHWORD gaddr2; VUHWORD gaddr3; VUHWORD gaddr4; VUWORD tbuf0_data0; VUWORD tbuf0_data1; VUWORD tbuf0_rba0; VUWORD tbuf0_crc; VUHWORD tbuf0_bcnt; VUHWORD paddr1_h; VUHWORD paddr1_m; VUHWORD paddr1_l; VUHWORD p_per; VUHWORD rfbd_ptr; VUHWORD tfbd_ptr; VUHWORD tlbd_ptr; VUWORD tbuf1_data0; VUWORD tbuf1_data1; VUWORD tbuf1_rba0; VUWORD tbuf1_crc; VUHWORD tbuf1_bcnt; VUHWORD tx_len; VUHWORD iaddr1; VUHWORD iaddr2; VUHWORD iaddr3; VUHWORD iaddr4; VUHWORD boff_cnt; VUHWORD taddr_h; VUHWORD taddr_m; VUHWORD taddr_l; t_EnetScc_Pram; /*-*/ UART /*-*/ typedef struct user user temp temp defined address defined address
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preset constant mask*/ error counter alignment error counter discarded frame counter Short frame character. Retry limit threshold. Retry limit counter. maximum frame length minimum frame length DMA1 length register. DMA2 length register. DMA. counter. buffer descriptor byte count. group address filter group address filter group address filter group address filter Saved area current frame. Saved area current frame.
physical address (MSB) physical address physical address (LSB) persistence first pointer. first pointer. last pointer. Saved area next frame. Saved area next frame.
frame length counter individual address filter. individual address filter. individual address filter. individual address filter. back-off counter temp address (MSB) temp address temp address (LSB)
Programming MSC8101 Periodic Interrupt Timer (PIT)
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msc8101.h source
VUBYTE reserved1[8]; VUHWORD max_idl; VUHWORD idlc; VUHWORD brkcr; VUHWORD parec; VUHWORD frmec; VUHWORD nosec; VUHWORD brkec; VUHWORD brkln; VUHWORD uaddr1; VUHWORD uaddr2; VUHWORD rtemp; VUHWORD toseq; VUHWORD cc[8]; VUHWORD rccm; VUHWORD rccr; VUHWORD rlbc; t_UartScc_Pram; /*-*/ Transparent /*-*/ typedef struct VUWORD c_mask; VUWORD c_pres; t_TransScc_Pram; /*-*/ Bisync /*-*/ typedef struct VUBYTE reserved1[4]; VUWORD crcc; VUHWORD prcrc; VUHWORD ptcrc; VUHWORD parec; VUHWORD bsync; VUHWORD bdle; VUHWORD cc[8]; VUHWORD rccm; t_BisyncScc_Pram; /*-*/ Common PRAM /*-*/ typedef struct VUHWORD rbase; VUHWORD tbase; VUBYTE rfcr; VUBYTE tfcr; VUHWORD mrblr; VUWORD rstate; VUWORD rptr; VUHWORD rbptr; VUHWORD rcount; VUWORD rtemp; VUWORD tstate; VUWORD tptr; Reserved area maximum idle characters idle counter (internal) break count register parity error counter framing error counter noise counter break character counter Receive break length address character address character temp storage sequence char control characters control char mask control char register Receive last break char
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constant preset
Reserved area Constant Temp Value Preset Receiver CRC-16/LRC Preset Transmitter CRC-16/LRC Receive Parity Error Counter BISYNC SYNC Character BISYNC Character control characters Receive Control Character Mask
base address base address function code function code buffer length internal state internal data pointer Pointer internal byte count temp internal state internal data pointer
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msc8101.h source
VUHWORD tbptr; pointer VUHWORD tcount; byte count VUWORD ttemp; temp VUWORD rcrc; temp receive VUWORD tcrc; temp transmit union t_HdlcScc_Pram t_EnetScc_Pram t_UartScc_Pram t_TransScc_Pram t_BisyncScc_Pram SpecificProtocol; VUBYTE t_Scc_Pram; /*-*/ FAST COMMUNICATION CONTROLLER (FCC) /*-*/ /*-*/ HDLC /*-*/ typedef struct VUBYTE reserved1[8]; VUWORD c_mask; VUWORD c_pres; VUHWORD disfc; VUHWORD crcec; VUHWORD abtsc; VUHWORD nmarc; VUWORD max_cnt; VUHWORD mflr; VUHWORD rfthr; VUHWORD rfcnt; VUHWORD hmask; VUHWORD haddr1; VUHWORD haddr2; VUHWORD haddr3; VUHWORD haddr4; VUHWORD tmp; VUHWORD tmp_mb; t_HdlcFcc_Pram; /*-*/ Ethernet /*-*/ typedef struct VUWORD stat_bus; VUWORD cam_ptr; VUWORD c_mask; VUWORD c_pres; VUWORD crcec; VUWORD alec; VUWORD disfc; VUHWORD ret_lim; VUHWORD ret_cnt; VUHWORD p_per; VUHWORD boff_cnt; VUWORD gaddr_h; VUWORD gaddr_l; VUHWORD tfcstat;
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Reserved area constant preset discarded frame counter error counter abort sequence counter nonmatching address maximum length counter maximum frame length received frames threshold received frames count user defined addr mask user defined address user defined address user defined address user defined address temp temp
Internal buffer. address. constant mask*/ preset error counter alignment error counter discarded frame counter Retry limit threshold. Retry limit counter. persistence back-off counter group address filter, high group address filter, sequece staus.
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msc8101.h source
VUHWORD VUWORD VUHWORD VUHWORD VUHWORD VUHWORD VUHWORD VUHWORD VUHWORD VUHWORD VUBYTE VUWORD VUWORD VUHWORD VUHWORD VUHWORD VUHWORD VUHWORD VUHWORD VUHWORD VUHWORD VUHWORD VUHWORD VUHWORD VUHWORD tfclen; tfcptr; mflr; paddr1_h; paddr1_m; paddr1_l; ibd_cnt; ibd_start; ibd_end; tx_len; ibd_base[0x20]; iaddr_h; iaddr_l; minflr; taddr_h; taddr_m; taddr_l; pad_ptr; cf_type; cf_range; max_b; maxd1; maxd2; maxd; dma_cnt; sequece length. sequece data pointer. maximum frame length physical address (MSB) physical address physical address (LSB) internal counter. internal start pointer. internal pointer. frame length counter internal micro code usage. individual address filter, high individual address filter, minimum frame length temp address (MSB) temp address temp address (LSB) pad_ptr. RESERVED (flow control frame type coding) flow control frame range. buffer descriptor byte count. DMA1 length register. DMA2 length register. DMA. counter.
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counter: VUWORD octc; VUWORD colc; VUWORD broc; VUWORD mulc; VUWORD uspc; VUWORD frgc; VUWORD ospc; VUWORD jbrc; VUWORD p64c; VUWORD p65c; VUWORD p128c; VUWORD p256c; VUWORD p512c; VUWORD p1024c; VUWORD cam_buf; VUHWORD rfthr; VUHWORD rfcnt; t_EnetFcc_Pram; /*-*/ Common PRAM /*-*/ typedef struct VUHWORD riptr; VUHWORD tiptr; VUHWORD reserved0; VUHWORD mrblr; VUWORD rstate; VUWORD rbase; VUHWORD rbdstat; VUHWORD rbdlen; VUWORD rdptr; VUWORD tstate;
received octets counter. estimated number collisions received good packets broadcast address received good packets multicast address received packets shorter then octets. uspc packets received packets longer then 1518 octets. ospc packets received packets octets. received packets 65-128 octets. received packets 128-255 octets. received packets 256-511 octets. received packets 512-1023 octets. received packets 1024-1518 octets. respond internal buffer. received frames threshold received frames count
internal temporary data pointer. internal temporary data pointer. Reserved buffer length internal state base address status control data length data pointer internal state
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msc8101.h source
VUWORD tbase; VUHWORD tbdstat; VUHWORD tbdlen; VUWORD tdptr; VUWORD rbptr; VUWORD tbptr; VUWORD rcrc; VUWORD reserved_1[0x1]; VUWORD tcrc; union t_HdlcFcc_Pram t_EnetFcc_Pram SpecificProtocol; t_Fcc_Pram; base address status control data length data pointer pointer pointer Temp receive Temp transmit Protocol-Specific parameter
/*-*/ MULTICHANNEL COMMUNICATION CONTROLLER (MCC) /*-*/ Note that each uses multiple logical channels. first define PRAM logical channel (which used either HDLC Transparent mode; wherever there differences, specified), followed PRAM itself. /*-*/ Logical Channel /*-*/ typedef struct VUWORD tstate; internal state. VUWORD zistate; Zero insertion machine state. VUWORD zidata0; Zero insertion high. VUWORD zidata1; Zero insertion low. VUHWORD tbdflags; internal flags. VUHWORD tbdcnt; internal byte count VUWORD tbdptr; internal data pointer. VUHWORD intmask; Interrupt mask flags. VUHWORD chamr; channel mode register. VUWORD tcrc; Transparent: reserved. Hdlc: Temp receive CRC.*/ VUWORD rstate; internal state. VUWORD zdstate; Zero deletion machine state. VUWORD zddata0; Zero deletion high. VUWORD zddata1; Zero deletion low. VUHWORD rbdflags; internal flags. VUHWORD rbdcnt; internal byte count VUWORD rbdptr; internal data pointer. VUHWORD maxrlen; Transparent: receive buffer length. Hdlc: receive frame length. VUHWORD sync_maxcnt; Transparent: Receive synchronization pattern*/ Hdlc: length counter. VUWORD rcrc; Transparent: reserved. Hdlc: Temp receive CRC.*/ t_Mch_Pram; /*-*/ Logical Channel Extra Parameters /*-*/ typedef struct
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Programming MSC8101 Periodic Interrupt Timer (PIT)
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msc8101.h source
VUHWORD tbase; TxBD base address. VUHWORD tbptr; Current TxBD pointer. VUHWORD rbase; RxBD base address. VUHWORD rbptr; Current RxBD pointer. t_MchXtra_Pram; /*-*/ PRAM /*-*/ typedef struct VUWORD mccbase; pointer starting address rings. VUHWORD mccstate; Controller state. VUHWORD mrblr; Maximum receive buffer length. VUHWORD grfthr; Global receive frame threshold. VUHWORD grfcnt; Global receive frame counter. VUWORD rinttmp; Temp location interrupt table entry. VUWORD data0; Temporary location holding data. VUWORD data1; Temporary location holding data. VUWORD tintbase; Transmit interrupt table base address. VUWORD tintptr; Transmit interrupt table pointer. VUWORD tinttmp; Temp location interrupt table entry. VUHWORD sctpbase; Pointer super channel transmit table*/ VUBYTE res0[0x2]; Reserved area VUWORD c_mask32; constant. VUHWORD xtrabase; Pointer beginning extra parameters VUHWORD c_mask16; constant. VUWORD rinttmp0; Temp location interrupt table entry. VUWORD rinttmp1; Temp location interrupt table entry. VUWORD rinttmp2; Temp location interrupt table entry. VUWORD rinttmp3; Temp location interrupt table entry. VUWORD rintbase0; interrupt table base address. VUWORD rintptr0; interrupt table pointer. VUWORD rintbase1; interrupt table base address. VUWORD rintptr1; interrupt table pointer. VUWORD rintbase2; interrupt table base address. VUWORD rintptr2; interrupt table pointer. VUWORD rintbase3; interrupt table base address. VUWORD rintptr3; interrupt table pointer. VUBYTE pad[0xa0]; fill bytes t_Mcc_Pram; /*-*/ APARAMETER /*-*/ /*-*/ Address Compression parameters table /*-*/ struct AddressCompressionPram VUWORD VptBase; VP-level addressing table base address VUWORD VctBase; VC-level addressing table base address VUWORD Vpt1Base; VP1-level addressing table base address VUWORD Vct1Base; VC1-level addressing table base address VUHWORD VpMask; mask address compression look-up
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Programming MSC8101 Periodic Interrupt Timer (PIT)
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msc8101.h source
/*-*/ External parameters table /*-*/ struct ExtCamPram VUWORD ExtCamBase; Base address external VUBYTE reserved00[4]; Reserved VUWORD ExtCam1Base; Base address external CAM1 VUBYTE reserved01[6]; Reserved /*-*/ Amode parameters table /*-*/ typedef struct AtmPram VUBYTE reserved0[64]; Reserved VUHWORD RxCellTmpBase; cell temporary base address VUHWORD TxCellTmpBase; cell temporary base address VUHWORD UdcTmpBase; temp base address mode only) VUHWORD IntRctBase; Internal base address VUHWORD IntTctBase; Internal base address VUHWORD IntTcteBase; Internal base address VUBYTE reserved1[4]; reserved four bytes VUWORD ExtRctBase; External base address VUWORD ExtTctBase; External base address VUWORD ExtTcteBase; External base address VUHWORD UeadOffset; offset half-wordunits UEAD entry extra header. Should even address. little-endian format used, UeadOffset little-endian format. VUBYTE reserved2[2]; Reserved VUHWORD PmtBase; Performance monitoring table base address VUHWORD ApcParamBase; Parameters table base address VUHWORD FbpParamBase; Free buffer pool parameters base address VUHWORD IntQParamBase; Interrupt queue parameters table base VUBYTE reserved3[2]; VUHWORD UniStatTableBase; statistics table base VUWORD BdBaseExt; ring base address extension union Structure packing supported. PROBLEM HERE!!! struct AddressCompressionPram AddrCompression; struct ExtCamPram ExtCam; AddrMapping; Address look-up mechanism VUHWORD VciFiltering; filtering enable bits. set, cell with VCI=i will sent cell queue. bits should zero. VUHWORD Gmode; Global mode VUHWORD CommInfo1; information field associated with last host command VUHWORD CommInfo2; information field associated with last host command VUHWORD CommInfo3; information field associated with last host command
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Programming MSC8101 Periodic Interrupt Timer (PIT)
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msc8101.h source
reserved201; Reserved reserved202; Reserved reserved203; Reserved reserved204; Reserved CRC32Preset; Preset CRC32 CRC32Mask; Constant mask CRC32 AAL1SnpTableBase; AAl1 protection look-up table base reserved5; Reserved SrtsBase; External SRTS logic base address. AAL1 only. Should bytes aligned VUHWORD IdleBase; Idle cell base address VUHWORD IdleSize; Idle cell size: VUWORD EmptyCellPayload; Empty cell payload (little-indian) specific only VUWORD Trm; Upper bound time between F-RM cells active source VUHWORD Nrm; Controls maximum data cells sent each F-RM cell. VUHWORD Mrm; Controls bandwidth between F-RM, B-RM user data cell VUHWORD Tcr; cell rate VUHWORD AbrRxTcte; reserved area address (2-UHWORD aligned)*/ VUBYTE reserved7[76]; Reserved t_Atm_Pram; /*-*/ SERIAL MANAGEMENT CHANNEL (SMC) /*-*/ typedef struct VUHWORD rbase; Base Address VUHWORD tbase; Base Address VUBYTE rfcr; function code VUBYTE tfcr; function code VUHWORD mrblr; buffer length VUWORD rstate; internal state VUWORD rptr; internal data pointer VUHWORD rbptr; Pointer VUHWORD rcount; internal byte count VUWORD rtemp; temp VUWORD tstate; internal state VUWORD tptr; internal data pointer VUHWORD tbptr; pointer VUHWORD tcount; byte count VUWORD ttemp; temp UART-specific PRAM VUHWORD max_idl; Maximum IDLE Characters VUHWORD idlc; Temporary IDLE Counter VUHWORD brkln; Last Break Length VUHWORD brkec; Break Condition Counter VUHWORD brkcr; Break Count Register (Tx) VUHWORD r_mask; Temporary mask t_Smc_Pram; VUBYTE VUBYTE VUBYTE VUBYTE VUWORD VUWORD VUHWORD VUHWORD VUWORD
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Programming MSC8101 Periodic Interrupt Timer (PIT)
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msc8101.h source
/*-*/ INTER-INTEGRATED CIRCUIT (I2C) /*-*/ typedef struct VUHWORD rbase; base address VUHWORD tbase; base address VUBYTE rfcr; function code VUBYTE tfcr; function code VUHWORD mrblr; buffer length VUWORD rstate; internal state VUWORD rptr; internal data pointer VUHWORD rbptr; Pointer VUHWORD rcount; internal byte count VUWORD rtemp; temp VUWORD tstate; internal state VUWORD tptr; internal data pointer VUHWORD tbptr; pointer VUHWORD tcount; byte count VUWORD ttemp; temp t_I2c_Pram; /*-*/ SERIAL PERIPHERAL INTERFACE (SPI) /*-*/ typedef struct VUHWORD rbase; Base Address VUHWORD tbase; Base Address VUBYTE rfcr; function code VUBYTE tfcr; function code VUHWORD mrblr; buffer length VUWORD rstate; internal state VUWORD rptr; internal data pointer VUHWORD rbptr; Pointer VUHWORD rcount; internal byte count VUWORD rtemp; temp VUWORD tstate; internal state VUWORD tptr; internal data pointer VUHWORD tbptr; pointer VUHWORD tcount; byte count VUWORD ttemp; temp VUBYTE reserved[8]; t_Spi_Pram; /*-*/ RISC TIMER PARAMETER /*-*/ typedef struct VUHWORD tm_base; VUHWORD tm_ptr; VUHWORD r_tmr; VUHWORD r_tmv; VUWORD tm_cmd; VUWORD tm_cnt; t_timer_pram; RISC RISC RISC RISC RISC RISC timer timer timer timer timer timer table base table pointer mode register valid register register internal
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Programming MSC8101 Periodic Interrupt Timer (PIT)
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msc8101.h source
/*-*/ MICROCODE PARAMETER AREA /*-*/ typedef struct VUHWORD rev_num; Ucode Revision Number VUHWORD d_ptr; MISC Dump area pointer t_ucode_pram; /*-*/ MAIN DEFINITION MSC8101 INTERNAL MEMORY /*-*/ typedef struct cpm_ram t_Mch_Pram VUBYTE
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mch_pram[256]; reserved0[0x4000];
logical channels parameter Reserved area
DPR_BASE+0x8000 /*-*/ note about pram union: pram area been broken three ways clean access into certain peripherals' spaces. This arrangement allows programmers flexibility usage terms being able change which peripheral being accessed simply changing array value. Given interweaving certain peripherals' pram areas, this would possible with only large pram structure. SERIALS accessing SCC, non-AFCC, pram accessing AFCC pram STANDARD accessing timers, revnum, d_ptr, RAND, pram base pointers SMCs, IDMAs, SPI, /*-*/ union access PRAM structs SCCs, FCCs, MCCs struct serials t_Scc_Pram scc_pram[4]; t_Fcc_Pram fcc_pram[3]; t_Mcc_Pram mcc_pram[2]; VUBYTE reserved1[0x700]; serials; access APRAM structs struct Notes: When packing data bytes within structure supported Enterprise compiler, uncomment entries this structure. Took "_Packed" from structures (t_ATM_Pram) because 8101 compiler does recognize this keyword, does support packing.
Programming MSC8101 Periodic Interrupt Timer (PIT)
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msc8101.h source
VUBYTE reserved2[0x400]; t_Atm_Pram atm_pram[2]; here!!! //VUBYTE reserved3[0xa00]; atm; access memory locations holding user-defined base addresses PRAM SMCs, IDMA, SPI, I2C. struct standard VUBYTE scc1[0x100]; VUBYTE scc2[0x100]; VUBYTE scc3[0x100]; VUBYTE scc4[0x100]; VUBYTE fcc1[0x100]; VUBYTE fcc2[0x100]; VUBYTE fcc3[0x100]; VUBYTE mcc1[0x80]; VUBYTE reserved_0[0x7c]; VUBYTE smc1[0x2]; VUBYTE idma1[0x2]; VUBYTE mcc2[0x80]; VUBYTE reserved_1[0x7c]; VUBYTE smc2[0x2]; VUBYTE idma2[0x2]; VUBYTE reserved_2[0xfc]; VUBYTE spi[0x2]; VUBYTE idma3[0x2]; VUBYTE reserved_3[0xe0]; VUBYTE timers[0x10]; VUBYTE Rev_num[0x2]; VUBYTE D_ptr[0x2]; VUBYTE reserved_4[0x4]; VUBYTE rand[0x4]; VUBYTE i2c[0x2]; VUBYTE idma4[0x2]; VUBYTE reserved_5[0x500]; standard; pram; VUBYTE VUBYTE VUBYTE reserved11[0x2000]; Reserved area cpm_ram_dpram_3[0x1000]; Internal reserved12[0x4000]; Reserved area <-The structure packing problem starts
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DPR_BASE+0x10000*/ VUWORD siu_siumcr; VUWORD siu_sypcr; VUBYTE reserved13[0x6]; VUHWORD siu_swsr; buses VUBYTE reserved14[0x14]; VUWORD bcr; VUBYTE ppc_acr; VUBYTE reserved15[0x3]; VUWORD ppc_alrh; VUWORD ppc_alrl; VUBYTE lcl_acr; VUBYTE reserved16[0x3];
Module Configuration Register System Protection Control Register Reserved area Software Service Register Reserved area Configuration Register Arbiter Configuration Register Reserved area Arbitration Level Reg. (First clients)*/ Arbitration Level Reg. (Next clients) Arbiter Configuration Register Reserved area
Programming MSC8101 Periodic Interrupt Timer (PIT)
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msc8101.h source
VUWORD lcl_alrh; Arbitration Level Reg. (First clients) VUWORD lcl_alrl; Arbitration Level Register (Next clients) VUWORD tescr1; transfer error status control reg. VUWORD tescr2; transfer error status control reg. VUWORD ltescr1; Local transfer error status control reg. VUWORD ltescr2; Local transfer error status control reg. VUWORD pdtea; Transfer Error Address VUBYTE pdtem; Transfer Error MSNUM VUBYTE reserved17[0x3]; Reserved area VUWORD ldtea; Transfer Error Address VUBYTE ldtem; Transfer Error MSNUM VUBYTE reserved18[0x3]; Reserved area VUWORD pdmtea; Transfer Error Address VUBYTE pdmter; Transfer Error RQNUM VUBYTE reserved95[0x3]; Reserved area VUWORD ldmtea; Local Transfer Error Address VUBYTE ldmter; Local Transfer Error RQNUM VUBYTE reserved96[0x93]; Reserved area memc struct memc_regs VUWORD Base Register VUWORD Option Register memc_regs[12]; VUBYTE reserved19[0x8]; Reserved area VUWORD memc_mar; Memory Address Register VUBYTE reserved20[0x4]; Reserved area VUWORD memc_mamr; Machine Mode Register VUWORD memc_mbmr; Machine Mode Register VUWORD memc_mcmr; Machine Mode Register VUBYTE reserved21[0x8]; Reserved area VUHWORD memc_mptpr; Memory Periodic Timer Prescaler VUBYTE reserved22[0x2]; Reserved area VUWORD memc_mdr; Memory Data Register VUBYTE reserved23[0x4]; Reserved area VUWORD memc_psdmr; PowerPC SDRAM machine Mode Register VUBYTE reserved97[0x4]; Reserved area VUBYTE memc_purt; PowerPC assigned VUPM Refresh Timer VUBYTE reserved24[0x3]; Reserved area VUBYTE memc_psrt; PowerPC assigned SDRAM Refresh Timer VUBYTE reserved25[0xb]; Reserved area VUWORD memc_immr; Internal Memory Register VUBYTE reserved98[0x74]; Reserved area si_timers VUHWORD si_timers_tmcntsc; Time Counter Status Control Register VUBYTE reserved30[0x2]; Reserved area VUWORD si_timers_tmcnt; Time Counter Register VUBYTE reserved99[0x4]; Reserved area VUWORD si_timers_tmcntal; Time Counter Alarm Register VUBYTE reserved31[0x10]; Reserved area VUHWORD si_timers_piscr; Periodic Interrupt Status Control Reg. VUBYTE reserved32[0x2]; Reserved area VUWORD si_timers_pitc; Periodic Interrupt Count Register VUWORD si_timers_pitr; Periodic Interrupt Timer Register VUBYTE reserved33[0x4b4]; Reserved area VUWORD dchcr[16]; Channel Configuration Register VUBYTE reserved100[0x40]; Reserved area VUWORD dma_dimr; Internal Mask Register VUHWORD dma_dstr; Status Register VUBYTE reserved101[0x2]; Reserved area
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Programming MSC8101 Periodic Interrupt Timer (PIT)
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msc8101.h source
VUBYTE dma_dtear; VUBYTE reserved102[0x3]; VUBYTE dma_dpcr; VUBYTE reserved103[0x3]; VUWORD dma_demr; VUBYTE reserved104[0x6c]; struct dma_dcpram VUWORD bd_addr; VUWORD bd_size; VUWORD bd_attr; VUWORD bd_bsize; dma_dcpram[16]; VUBYTE reserved105[0x300]; VUHWORD VUBYTE VUWORD VUWORD VUWORD VUWORD VUWORD VUWORD VUWORD VUWORD VUWORD VUBYTE VUHWORD VUBYTE VUWORD VUWORD VUWORD VUWORD VUWORD VUWORD VUWORD VUWORD VUWORD VUBYTE Status Register Reserved area Configuration Register Reserved area External Mask Register Reserved area Channel Parameter Buffer Buffer Buffer Buffer Descriptor Descriptor Descriptor Descriptor Address Transfer Size Attributes Base Size
Channel Parameter Reserved area
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ic_sicr; reserved36[0x2]; ic_sivec; ic_sipnr_h; ic_sipnr_l; ic_siprr; ic_scprr_h; ic_scprr_l; ic_simr_h; ic_simr_l; ic_siexr; reserved37[0x18]; ic_sicr_ext; reserved106[0x2]; ic_sivec_ext; ic_sipnr_h_ext; ic_sipnr_l_ext; ic_siprr_ext; ic_scprr_h_ext; ic_scprr_l_ext; ic_simr_h_ext; ic_simr_l_ext; ic_siexr_ext; reserved107[0x18];
Interrupt Configuration Register Reserved area Interrupt Vector Register Interrupt Pending Register (HIGH) Interrupt Pending Register (LOW) Interrupt Priority Register Interrupt Priority Register (HIGH) Interrupt Priority Register (LOW) Interrupt Mask Register (HIGH) Interrupt Mask Register (LOW) External Interrupt Control Register Reserved area Interrupt Configuration Register Reserved area Interrupt Vector Register Interrupt Pending Register (HIGH) Interrupt Pending Register (LOW) Interrupt Priority Register Interrupt Priority Register (HIGH) Interrupt Priority Register (LOW) Interrupt Mask Register (HIGH) Interrupt Mask Register (LOW) External Interrupt Control Register Reserved area
clocks VUWORD clocks_sccr; VUBYTE reserved38[0x4]; VUWORD clocks_scmr; VUBYTE reserved39[0x4]; VUWORD clocks_rsr; VUBYTE reserved40[0x6C]; io_ports struct io_regs VUWORD pdir; VUWORD ppar; VUWORD psor; VUWORD podr; VUWORD pdat; VUBYTE reserved41[0xc]; io_regs[4]; cpm_timers
System Clock Control Register Reserved area System Clock Mode Register Reserved area Reset Status Register Reserved area
Port Port Port Port Port Reserved
Data Direction Register Assignment Register Special Operation Register Open Drain Register Data Register area
Programming MSC8101 Periodic Interrupt Timer (PIT)
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msc8101.h source
VUBYTE cpm_timers_tgcr1; VUBYTE reserved42[0x3]; VUBYTE cpm_timers_tgcr2; VUBYTE reserved43[0xb]; VUHWORD cpm_timers_tmr1; VUHWORD cpm_timers_tmr2; VUHWORD cpm_timers_trr1; VUHWORD cpm_timers_trr2; VUHWORD cpm_timers_tcr1; VUHWORD cpm_timers_tcr2; VUHWORD cpm_timers_tcn1; VUHWORD cpm_timers_tcn2; VUHWORD cpm_timers_tmr3; VUHWORD cpm_timers_tmr4; VUHWORD cpm_timers_trr3; VUHWORD cpm_timers_trr4; VUHWORD cpm_timers_tcr3; VUHWORD cpm_timers_tcr4; VUHWORD cpm_timers_tcn3; VUHWORD cpm_timers_tcn4; VUHWORD cpm_timers_ter[4]; VUBYTE reserved44[0x260]; sdma general VUBYTE sdma_sdsr; VUBYTE reserved45[0x3]; VUBYTE sdma_sdmr; VUBYTE reserved46[0x3]; idma VUBYTE VUBYTE VUBYTE VUBYTE VUBYTE VUBYTE VUBYTE VUBYTE VUBYTE VUBYTE VUBYTE VUBYTE VUBYTE VUBYTE VUBYTE VUBYTE Timer Global Configuration Register Reserved area Timer Global Configuration Register Reserved area Timer Mode Register Timer Mode Register Timer Reference Register Timer Reference Register Timer Capture Register Timer Capture Register Timer Counter Timer Counter Timer Mode Register Timer Mode Register Timer Reference Register Timer Reference Register Timer Capture Register Timer Capture Register Timer Counter Timer Counter Timer Event Register Reserved area
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SDMA Status Register Reserved area SDMA Mask Register Reserved area
idma_idsr1; reserved47[0x3]; idma_idmr1; reserved48[0x3]; idma_idsr2; reserved49[0x3]; idma_idmr2; reserved50[0x3]; idma_idsr3; reserved51[0x3]; idma_idmr3; reserved52[0x3]; idma_idsr4; reserved53[0x3]; idma_idmr4; reserved54[0x2c3];
IDMA Status Register Reserved area IDMA Mask Register Reserved area IDMA Status Register Reserved area IDMA Mask Register Reserved area IDMA Status Register Reserved area IDMA Mask Register Reserved area IDMA Status Register Reserved area IDMA Mask Register Reserved area
struct fcc_regs VUWORD gfmr; VUWORD psmr; VUHWORD todr; VUBYTE reserved55[0x2];/* VUHWORD dsr; VUBYTE reserved56[0x2];/* VUWORD fcce; VUWORD fccm; VUBYTE fccs; VUBYTE reserved57[0x3];/* VUWORD ftirr;
General Mode Register Protocol Specific Mode Register Transmit Demand Register Reserved area Data Sync. Register Reserved area Event Register Mask Register Status Register Reserved area Transmit Partial Rate Register
Programming MSC8101 Periodic Interrupt Timer (PIT)
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msc8101.h source
fcc_regs[3]; VUBYTE reserved58[0x290]; brgs VUWORD VUWORD VUWORD VUWORD VUBYTE VUBYTE VUBYTE VUBYTE VUBYTE VUBYTE VUBYTE VUBYTE VUBYTE VUBYTE VUBYTE VUBYTE VUBYTE VUWORD VUWORD VUBYTE VUHWORD VUBYTE VUHWORD VUHWORD VUBYTE VUWORD VUBYTE brgs VUWORD VUWORD VUWORD VUWORD brgs_brgc5; brgs_brgc6; brgs_brgc7; brgs_brgc8; reserved59[0x260];
Reserved area
Configuration Configuration Configuration Configuration Reserved area
Register Register Register Register
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i2c_i2mod; reserved60[0x3]; i2c_i2add; reserved61[0x3]; i2c_i2brg; reserved62[0x3]; i2c_i2com; reserved63[0x3]; i2c_i2cer; reserved64[0x3]; i2c_i2cmr; reserved65[0x14b];
Mode Register Reserved area Address Register Reserved area Register Reserved area Command Register Reserved area Event Register Reserved area Mask Register Reserved area
cpm_cpcr; cpm_rccr; reserved66[0xe]; cpm_rter; reserved67[0x2]; cpm_rtmr; cpm_rtscr; reserved108[0x2]; cpm_rtsr; reserved68[0xc]; brgs_brgc1; brgs_brgc2; brgs_brgc3; brgs_brgc4;
Communication Processor Command Register RISC Configuration Register Reserved area RISC Timers Event Register Reserved area RISC Timers Mask Register RISC Time-Stamp Timer Control Register Reserved area RISC Time-Stamp Register Reserved area
Configuration Configuration Configuration Configuration
Register Register Register Register
struct scc_regs_8101 VUWORD gsmr_l; VUWORD gsmr_h; VUHWORD psmr; VUBYTE reserved69[0x2];/* VUHWORD todr; VUHWORD dsr; VUHWORD scce; VUBYTE reserved70[0x2];/* VUHWORD sccm; VUBYTE reserved71; VUBYTE sccs; VUBYTE reserved72[0x8];/* scc_regs[4]; struct smc_regs_8101
General Mode Register General Mode Register Protocol Specific Mode Register Reserved area Transmit-On-Demand Register Data Synchronization Register Event Register Reserved area Mask Register Reserved area Status Register Reserved area
Programming MSC8101 Periodic Interrupt Timer (PIT)
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msc8101.h source
VUBYTE reserved73[0x2];/* VUHWORD smcmr; VUBYTE reserved74[0x2];/* VUBYTE smce; VUBYTE reserved75[0x3];/* VUBYTE smcm; VUBYTE reserved76[0x5];/* smc_regs[2]; VUHWORD VUBYTE VUBYTE VUBYTE VUBYTE VUBYTE VUBYTE VUBYTE Reserved area Mode Register Reserved area Event Register Reserved area Mask Register Reserved area
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spi_spmode; reserved77[0x4]; spi_spie; reserved78[0x3]; spi_spim; reserved79[0x2]; spi_spcom; reserved80[0x52];
Mode Register Reserved area Event Register Reserved area Mask Register Reserved area Command Register Reserved area
cpm_mux VUBYTE cpm_mux_cmxsi1cr; VUBYTE reserved81; VUBYTE cpm_mux_cmxsi2cr; VUBYTE reserved82; VUWORD cpm_mux_cmxfcr; VUWORD cpm_mux_cmxscr; VUBYTE cpm_mux_cmxsmr; VUBYTE reserved83; VUHWORD cpm_mux_cmxuar; VUBYTE reserved84[0x10];
Clock Route Register Reserved area Clock Route Register Reserved area Clock Route Register Clock Route Register Clock Route Register Reserved area VUTOPIA Address Register Reserved area
struct si_regs VUHWORD sixmr[4]; VUBYTE sigmr; VUBYTE reserved85; VUBYTE sicmdr; VUBYTE reserved86; VUBYTE sistr; VUBYTE reserved87; VUHWORD sirsr; VUHWORD mcce; VUBYTE reserved88[0x2];/* VUHWORD mccm; VUBYTE reserved89[0x2];/* VUBYTE mccf; VUBYTE reserved90[0x7];/* si_regs[2]; VUBYTE reserved91[0x4a0]; si_ram struct si_ram VUHWORD tx_siram[0x100]; VUBYTE reserved92[0x200]; VUHWORD rx_siram[0x100]; VUBYTE reserved93[0x200]; si_ram[2]; VUBYTE reserved94[0x1000];
Mode Registers Global Mode Register Reserved area Command Register Reserved area Status Register Reserved area Shadow Address Register Event Register Reserved area Mask Register Reserved area Configuration Register Reserved area Reserved area
Transmit Routing Reserved area Receive Routing Reserved area
Reserved area
Programming MSC8101 Periodic Interrupt Timer (PIT)
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pit.c source
t_8101IMM;
/*-*/ MSC8101 CONSTANTS DEFINITIONS /*-*/ #define PORTA Index into Parallel Regs Array #define PORTB Index into Parallel Regs Array #define PORTC Index into Parallel Regs Array #define PORTD Index into Parallel Regs Array #define #define #define #define #define #define #define #define #endif PAGE1 PAGE2 PAGE3 PAGE4 SCC1 SCC2 SCC3 SCC4 Index Index Index Index SCC1 SCC2 SCC3 SCC4 into into into into PRAM PRAM PRAM PRAM Array Array Array Array PRAM PRAM PRAM PRAM Array Array Array Array
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Index Index Index Index
into into into into
pit.c source
/*-* FILENAME: PIT.c DESCRIPTION: Sets registers enabling Periodic Interrupt Timer, with interrupts enabled, using Baud Rate Generator timersclk source. *-*/ #include "msc8101.h" Interrupt codes used SIVEC branch table enum SIC_IRQ_CODE SIC_ERROR, SIC_I2C,SIC_SPI,SIC_RISC, SIC_FCC1,SIC_FCC2, SIC_FCC3,SIC_RESV09,
CPM_CPCR MASKS #define CPCR_RST
0x80000000
//CPM reset
Programming MSC8101 Periodic Interrupt Timer (PIT)
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pit.c source
#define CPCR_FLG 0x00010000 //CPM-busy flag /*-*/ Global Declarations /*-*/ #define QBUS_BASE 0x00F00000 //Default QBus Baseline //Value Vector Base Address Register (VBA) #define 0x00000000 //macro register #define SET_VBA asm("move.l #$00000000,vba") Internal Memory base pointer t_8101IMM *IMM; PIC's Edge/Level-Trig. Priority Reg. UHWORD *elire;
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PIC's Pending Register UHWORD *iprb; //This table contains interrupt function addresses. //64 entries, each bytes bytes memory UWORD SIC_BranchTable[64]; /*-*/ Function Prototypes /*-*/ void main(void); void SIC_IrqHandler(void); void SIC_InitInterrupt(void); void PIT_InitInterrupt(void); void PIT_Interrupt(void); Code Start void main(void) "di" disable interrupts
/*-*/ Establish pointer. When system came reset, default*/ Internal Memory base 0x0F000000 value programmed Hard Reset Configuration Word. startup.c, Register reprogrammed 0x14700000. This next line code simply loading pointer used this example, with base*/ address value that already established startup.c /*-*/ (t_8101IMM *)0x14700000; MSC8101 internal register Reset IMM->cpm_cpcr CPCR_RST CPCR_FLG; //set bits while (IMM->cpm_cpcr CPCR_FLG); //wait until reset finished
Programming MSC8101 Periodic Interrupt Timer (PIT)
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pit.c source
/*-*/ next lines required done 8101 command file before code downloaded. running from flash, uncomment next lines code. /*-*/ IMM->memc_regs[1].br 0x14501801; base register IMM->memc_regs[1].or 0xffff8010; option register Initialize GPCM IMM->memc_regs[11].br QBUS_BASE+0x21;// 64-bit port size IMM->memc_regs[11].or 0xffff0000; /*-*/ Setup SIU-CPM Interrupt Controller (SIC) /*-*/ SIC_InitInterrupt(); PIT_InitInterrupt();
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mask priorities 0,1,2; permit "bmclr #$00a0,sr.h" required; else interrupts never enabled "nop" "ei" enable interrupts
/*-*/ Program System Clock Control Register SCCR Bits 30-31 Division Factor clock divide /*-*/ results 6.25MHz with 25MHZ crystal IMM->clocks_sccr 0x00000001; /*-*/ Program Baud Rate Generator Configuration Register (BRGC1). Bits 0-13 reserved. (Reset BRG) Enable (Enable Count) Enable clocks EXTC (External Clock Source) input clock comes from CPMCLK (AutoBaud) Normal operation BRG. (Clock Divider) 0x0BE decimal (25mhz cstl) 0x17D decimal (16mhz cstl) DIV16 (Divide-by-16) divide /*-*/ With brgclk 6.25mhz; produces brg1 clock 32.768KHz 8.192KHz) IMM->brgs_brgc1 0x0001017c;// 25mhz crystal using mode IMM->brgs_brgc1 0x000102fa;// 16.384mhz crystal using mode Setup Parallel Port registers direct BRG1 PC[31] purpose IMM->io_regs[PORTC].ppar 0x00000001;
Programming MSC8101 Periodic Interrupt Timer (PIT)
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pit.c source
direct BRG1 PC[31] bit2 force PC[29] output. PC[29] used measure period. (Debug purpose only) IMM->io_regs[PORTC].pdir 0x00000005; IMM->io_regs[PORTC].psor 0x00000000; IMM->io_regs[PORTC].podr 0x00000000; /*-*/ Program Periodic Interrupt Timer Count Register (PITCR) 0-15 PITC $0051 ~10ms period /*-*/ IMM->si_timers_pitc 0x00510000; /*-*/ Program Periodic Interrupt Status Control Register (PISCR) Reserved Periodic Interrupt Status when PITR 9-12 Reserved Periodic Interrupt Enable enabled Periodic Interrupt Frequency 4MHz Periodic Timer Enable enabled /*-*/ IMM->si_timers_piscr 0x0007; while(1); asm( "debug" SIC_InitInterrupt Sets SIU-CPM Interrupt Controller void SIC_InitInterrupt(void) /*-*/ Note! Interrupt Vector Register (SIVEC) used moment. Therefore 'SIC_IrqHandler' must find what's reason every interrupt. Establish relevant pointers registers SIC-Irq usage /*-*/ SET_VBA; macro register iprb (UHWORD*) (QBUS_BASE 0x00001c38); elire (UHWORD*) (QBUS_BASE 0x00001c20); /*-*/ Configure Programmable Controller (PIC) enable Irqs: Make sure that Vector Base Address Reg. (VBA) correctly! SIC-Irq core jumps into routing table (base VBA) offset 0x0C00. Create routing table entry SIC-Irq, i.e. copy assembly code provided location Routing table. (Note! Here max. number bytes entry copied, although maybe less used. intention that number bytes doesn't need changed, when assembly code changes.) /*-*/ memcpy((void*)(VBA 0x0c00), &SIC_IrqHandler, 0x40); clear whole branch table memset(SIC_BranchTable, sizeof(SIC_BranchTable));
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Programming MSC8101 Periodic Interrupt Timer (PIT)
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pit.c source
/*-*/ clear previous interrupts register /*-*/ //clear previous interrupts SIC-reg. IMM->ic_sipnr_l 0xFFFFFFFF; //clear previous interrupts SIC-reg. IMM->ic_sipnr_h 0xFFFFFFFF; IMM->ic_simr_l 0x00000000; //disable interrupts
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clear previous interrupt Pending Register *iprb 0x0001; /*-*/ Configure Edge/Level-Triggered Priority Register enable IRQ16: Irq16 (SIC), level-triggered, priority level=3 /*-*/ *elire (*elire 0xFFF0) 0x0003; return; PIT_InitInterrupt Configure interrupt void PIT_InitInterrupt(void) create entry branch table SIC_BranchTable[SIC_PIT] (UWORD)&PIT_Interrupt; /*-*/ Configure SIU_CPM interrupt controller (SIC) When interrupt occurs, bit17 SIPNR_L will set. Furthermore corresponding interrupt code (SPI=2) 0x08000000 will visible SIVEC (dependent priority level). /*-*/ clear previous interrupt IMM->ic_sipnr_h 0x00000002; IMM->ic_simr_h 0x00000002; enable interrupt return; SIC_IrqHandler #pragma interrupt SIC_IrqHandler void SIC_IrqHandler(void) /*-*/ This function must copied location 'VBA+0x0C00' within routing table. Ensure that max. bytes (64-(6+6+2)) assembly code included into this function. Ensure that interrupt branch table been allocated (global) with 'UWORD SIC_BranchTable[64]'. Advice: Don't change this function, change only branch table entries. /*-*/
Programming MSC8101 Periodic Interrupt Timer (PIT)
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pit.c source
bytes JSR, created #pragma push registers onto stack asm("move.l _IMM,r0"); //IMM base address asm("move.l #$00010C04,r1"); //SIVEC offset asm("nop"); asm("adda r1,r0"); //SIVEC address asm("nop"); //get SIVEC figure source asm("moveu.b (r0),r1"); asm("move.l #_SIC_BranchTable,r0"); //get branch table base asm("nop"); asm("adda r0,r1"); //add sivec branch table base asm("nop"); //get address function from branch table asm("move.l (r1),r0"); asm("nop"); asm("jsr r0"); //call interrupt function bytes JSR, created #pragma registers from stack bytes, created #pragma return from interrupt PIT_IrqHandler void PIT_Interrupt(void) /*-*/ This function only called when SIC/PIT interrupt occurs. /*-*/ clear PISCR[PS] bit; PISCR[PS] when PISR count IMM->si_timers_piscr IMM->si_timers_piscr 0x0087; clear interrupt flag SIC-reg IMM->ic_sipnr_h 0x00000002; clear interrupt flag IPRB *iprb 0x0001; toggle PC[29] debug purpose only IMM->io_regs[PORTC].pdat IMM->io_regs[PORTC].pdat 0x0004; return; file
Freescale Semiconductor, Inc.
Programming MSC8101 Periodic Interrupt Timer (PIT)
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Freescale Semiconductor, Inc.
OnCE, DigitalDNA, DigitalDNA logo trademarks Motorola, Inc.
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USA/EUROPE Motorola Literature Distribution P.O. 5405 Denver, Colorado 80217 1-303-675-2140 1-800-441-2447 Technical Information Center 1-800-521-6274 JAPAN Motorola Japan Ltd. SPS, Technical Information Center 3-20-1, Minami-Azabu, Minato-ku Tokyo 106-8573 Japan 81-3-3440-3569 ASIA/PACIFIC Motorola Semiconductors H.K. Ltd. Silicon Harbour Centre King Street Industrial Estate N.T., Hong Kong 852-26668334 Home Page http://www.mot.com/SPS Helpline email: dsphelp@dsp.sps.mot.com
Order Number AN2144/D
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