Characterizing CMOS Core Current Low-Power Applications David DiC
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Characterizing CMOS Core Current Low-Power Applications
David DiCarlo
AN2013/D Rev. 10/2000
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Copyright Motorola, Inc., 2000
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Abstract Contents
With increasing digital signal processors battery-operated, portable applications, there increasing need conserve power minimize heat dissipation. This application note discusses simple, low-cost method characterizing CMOS current consumption application board while running actual application code. application code, code structure, operating frequency then optimized minimum power consumption. Although only measurement core supply current presented this application note, methods discussed also applied supply current, optimizing structure use.
Additionally, several Motorola DSP563xx evaluation boards modified enable core current measurements, eliminating need build prototype application board with that capability.
Introduction Power Consumption CMOS Devices DSP563xx Hardware Operating Modes. Application Code Measuring Current Demonstrating Low-Power Measurement Power Supply Prototype Test Code Current Measurement Results Analysis Summary Conclusion Current-Sensing Power Supply. Core Current
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Characterizing Core Current Low-Power Applications More Information This Product, www.freescale.com
Introduction
Manufacturers publish typical values current consumption various operational modes. CMOS digital signal processor (DSP) current strongly affected core clock frequency, application code, code structure. relationship these factors core current must understood successfully optimize battery-operated, portable design using CMOS DSP. This discussion Section "Power Consumption CMOS Devices."
simple, low-cost method characterizing core current actual application demonstrated Section "Demonstrating Low-Power Measurement." Section "Current Measurement Results Analysis," presents current data processors DSP563xx family while they execute several benchmarks different operating frequencies. This section also presents details modifying several DSP563xx evaluation boards. Section "Summary Conclusion," contains conclusions methods presented.
Power Consumption CMOS Devices
Current CMOS devices result current required charge discharge each node that switches from power supply rail other. Nodes that switch contribute current because additional charge required maintain state nonswitching nodes. amount charge required switch node from rail other expressed mathematically Qnode Cnode Vsupply where: Qnode amount charge coulombs required Cnode capacitance node farads Vsupply voltage difference between supply rails Alternately switching node from supply rail other produces current that directly proportional switching rate, frequency. Current expressed terms charge unit time, expressed mathematically Inode Qnode frequency Cnode Vsupply frequency where: Inode current required switch single node frequency rate hertz that node switched between rails summing current switching nodes, total device current expressed Idevice Cswitch Vsupply frequency Eqn. Eqn. Eqn.
Introduction More Information This Product, www.freescale.com
where: Idevice total device current Cswitch total capacitance nodes that switching CMOS-based DSP, because number nodes that switch changes application code executed data processed, total capacitance switching nodes changes well. Equation page better expressed where total device current switching capacitance functions time: Idevice(t) Cswitch(t) Vsupply frequency where: Idevice(t) total device current function time Cswitch(t) total capacitance switching nodes function time While impossible calculate actual number switching nodes function time given instruction data set, necessary understand application software code, on-chip resources, clock frequency affect current function time. Eqn.
DSP563xx Hardware
DSP563xx family CMOS-based digital signal processors based 24-bit, fixed point core surrounded differing amounts internal SRAM complement peripherals general-purpose (GPIO) pins. Internal processor speeds available some derivatives, because core execute instruction clock cycle, rate million instructions second (MIPS) possible. devices implemented high-density CMOS fabrication technologies that exhibit operating currents with supply voltages range down fully static design DSP563xx family devices allows low-power operating modes where core possibly peripherals halted when activity required. full state processor preserved execution resumed without losses data position code. clock provided internal phase-locked loop (PLL) clock generation circuit, allowing relatively frequency external crystals clock oscillators, eliminating challenge providing external full-speed clock signal. output frequency fully programmable disabled during low-power mode, through software control. internal clock also available on-chip peripherals use. DSP563xx core internal SRAM that operates with zero wait states organized three banks: bank Program memory banks data memory. size each bank memory depends particular derivative device. Three independent internal addresses data buses allow multiple data paths. On-chip memory capacity been increasing with each member family, further decreasing need external memory application code data storage. external memory interface, Port provided memory expansion outside device off-chip memory-mapped peripherals. Port requires least wait state therefore limited operation half internal frequency. Port also programmed mirror internal memory addresses debugging. Additionally, Port controller disabled power-sensitive applications where required. Each member DSP563xx family surrounded several on-chip peripherals that assist moving data out, around that provide event timing measurement support. Additionally, DSP56307 DSP56311 each have on-chip filter co-processor that perform filter operations hardware, therefore reducing MIPS load core. DSP5636x derivatives have peripherals that were specifically designed digital audio applications. most instances, pins unused peripherals
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Operating Modes
used general-purpose input output. Each peripheral derives power from device's supply. Low-power applications call judicious each peripheral because each will current seen that power supply.
Operating Modes
There three operating modes: Normal, Wait, Stop. Normal mode, clock generation circuitry, core, enabled peripherals active application code executed. Wait Stop low-power modes operation. Wait mode, clock generation circuitry enabled peripherals active, clock signal core internal memory gated processor halted. unmasked interrupt external hardware reset will cause processor wake process exception condition. advantage Wait mode that on-chip peripherals remain active. Data streams processed power conserved during idle periods streams.
Stop mode offers lowest power mode operation. clock signal gated internally core peripheral activities suspended. hardware reset external interrupt IRQA will bring Stop mode, processing will continue. Because Stop mode interrupt peripherals during data transfers, Stop mode should used only after careful consideration implications application. Additionally, clock circuitry fully disabled Stop mode, further reducing power, doing requires clock-stabilization delay wake-up.
Application Code
Application code plays role power consumed CMOS DSP, both microscopically linear parallel code macroscopically overall application code structured. three independent internal buses DSP563xx family devices allow additional data moves performed parallel with Data instructions, enabling data preloaded moved around processor more efficiently. MIPS capacity effectively increased because fewer actual instruction cycles required perform application task, resulting boosted performance. Linear code performing same task given operating frequency will take longer complete than equivalent, highly parallel code executing same frequency. Because parallel moves will number switching nodes, highly parallel code will consume more current than equivalent linear code same operating frequency. higher level, overall structure application code impact current consumption. natural tendency maximum operating frequency. many applications, MIPS capacity exceeds what required, processor idle during periods when processing required. While amount current wasted during idle periods reduced Wait Stop modes, also possible reduce clock frequency organize code that processor capacity matches demands application there little idle time.
Measuring Current
Although qualitative understanding factors that influence core current helpful, more useful able quantitatively measure actual device current while varying these factors. most interest designer low-power applications variation core current with clock frequency organization linearity application code utilization on-chip resources.
Power Consumption CMOS Devices More Information This Product, www.freescale.com
Current usually measured using ammeter, where voltage drop across known resistance used calculate current using ohm's law. Figure which shows typical schematic measuring current, comprise ammeter. Making low-current measurements challenge. small current requires larger resistance obtain useful measurement voltage. However, larger resistance reduces voltage across device. addition, current changes time, then voltage across device changes well, because voltage drop across measurement resistance changes. compromise between much device voltage lowered measurable voltage drop must made achieve desired accuracy current measurement.
Power Supply
Device Under Test
Figure Typical Schematic Current Measurement
CMOS DSPs, current measurements have typically been made with expensive current probes (very resistance with very sensitive volt meter) with ammeter with very series resistance using circuit boards designed specifically measuring current. disadvantage twofold: cost entry make measurements high both equipment cost custom hardware make measurement) measurements still suffer from perturbation caused making measurement first place.
Power Supply
Device Under Test
Sense
Figure Schematic Measuring Current Using Current-Sensing Resistor
Figure shows power supply with ability accurately measure current while avoiding disadvantages typical method. current supplied device calculated measuring voltage across current-sensing resistor, output held constant using external output voltage-sensing feature voltage regulator. current includes current required regulator sense control output voltage, appropriate selection voltage regulator voltage-sense circuitry make that current much smaller than device current. advantages using power supply make device current measurement that cost very that included application board very easily. addition, application board easily designed modified accommodate making these measurements with outboard current-sensing power supply.
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Freescale Semiconductor, Inc. Power Supply Prototype
Demonstrating Low-Power Measurement
This section presents power supply prototype test codes used demonstrate low-power measurements methods. Also presented results analysis current data. section concludes presenting details modifying several DSP563xx evaluation boards.
Power Supply Prototype
National Semiconductor LP2960 adjustable regulator selected prototyping current-sensing power supply. LP2960 selected ready availability following features: output easily programmed externally operation configured (required DPS56311) low-quiescent current
Figure shows prototype power supply schematic. Fine adjustment output voltage possible using 10-turn, trimpot, RTRIM. output voltage programmed replacing resistor ROUT. values each output voltage listed table within Figure Device supply current measured using voltage drop across resistor, where equivalent
Rout TRIM LP2960 ROUT VOUT RTRIM VOUT
Figure Schematic LP2960 Current-Sensing Power Supply
According LP2960 data sheet, least current required voltage programming network stability (ROUT, RTRIM, Figure values selected prototype circuit drew about meeting requirements stability minimizing contribution device current measured through Figure page shows supply current DSP56309 core executing benchmark (top trace) along with output voltage regulator (bottom trace). regulator output found able maintain fairly constant output voltage, even presence dynamic output current. Although there some fluctuation output voltage that would desirable actual application, fluctuation only noticed large swings supply current, such kernel. stability more than sufficient characterize core current during development periods relatively constant supply current.
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Figure Supply Current
initial core current values were measured using custom board with socket that allows most members DSP563xx family installed. board configured according schematic Figure Three separate power supplies were used supply independent power PLL, core, DSP's peripheral circuitry.
Power Supply Core Power Supply Power Supply
VccP VccQ
VccP PINIT/NMI MODA
VccQL
Vcc*
MODD MODB MODC Under Test
peripheral pins tied high through individual resistors
VccQ
XTAL EXTAL PCAP 0.01
JTAG/OnCEheader
VccP
NOTE: includes VccA, VccD, VccC, VccN, VccH, VccS, VccQH. Bypass capacitors shown.
Figure Test Circuit Schematic
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Test Code
prototype, current-sensing power supply used core supply. unused inputs were terminated with resistors tied power supply. crystal used clock input. core current five members DSP563xx family were measured, shown Table which details maskset information, fabrication process technology, core supply voltage.
Table Process Information Devices Measured
Device DSP56301 DSP56303 DSP56307 DSP56309 Maskset 2K30A 0K36A J22D 0J17D 2J23D Process Technology 0.32 CDR2 0.32 CDR2 0.32 CDR2 0.32 CDR2 0.23 HiP4DSP Core Supply Voltage
DSP56311
Test Code
application test code's effect core current demonstrated using battery algorithms, listed Table With exception Motorola-developed 6.10 speech encoder, test algorithms came from code that co-developed with Berkeley Design Technology, Inc. (BDTI) publication 2001 edition BDTI's Buyer's Guide Processors. routines were modified loop endlessly, where necessary, test data supplied with benchmark reset original values before each pass kernel. Table shows several routines that were modified toggle TIO0 signal during execution main kernel algorithm triggering oscilloscope.
Table Information Test Code Used Demonstrate Current-Sensing Power Supply
Benchmark BITUPK BLKFIR CONTROL CXFIR FFT99 (MOT) SSFIR VECMAX VECPROD VECSUM VITERBI Description unpacking Block-based real filter Control benchmark Block-based complex filter 256-point complex speech encoder Cascaded biquad filter adaptive filter Sample sample real filter Vector maximum Real vector product Real vector Viterbi decoder Benchmark modified provide oscilloscope trigger TIO0. Benchmark modified provide oscilloscope trigger TIO0. Benchmark modified provide oscilloscope trigger TIO0. Benchmark modified provide oscilloscope trigger TIO0. Comments
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code downloaded through JTAG/OnCEport using command converter. frequency manually with debugger three different frequencies each processor. frequencies measured MHz, MHz, MHz, except DSP56311, which also measured MHz. current allowed settle several minutes, after which current recorded.
Current Measurement Results Analysis
results current measurements each test algorithm detailed Table Each value shown average current algorithm kernel expressed algorithms fairly constant core currents throughout kernel except FFT99. FFT99 profile, shown Figure page typical DSPs measured, where only differences were magnitude width.
Table Average Core Current Each Test Algorithm (All Currents
DSP56301 FREQ (MHz) BITUPK BLKFIR CONTROL CXFIR FFT99 (MOT) SSFIR VECMAX VECPROD VECSUM VITERBI DSP56303 DSP56307 DSP56309 DSP56311
general, DSP56309 consumed most current DSPs measured while DSP56311 consumed least. DSP56309 likely consumed most current because contains largest internal memory space 0.32 CDR2 technology processors. DSP56311 lowest operating voltage Additionally, DSP56311 fabricated from smaller, 0.23 geometry newer, HiP4DSP process technology. None algorithms contained code that took advantage Enhanced Filter Co-Processor (EFCOP) DSP56307 DSP56311, possible assess implications EFCOP's core current.
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Test Code
might expected scanning column table will demonstrate, given frequency, core current varied depending test algorithm. CONTROL benchmark exhibited lowest core current, while FFT99 CXFIR benchmarks typically exhibited highest current given processor given frequency (that lowest highest values, respectively, particular column). understand difference observed core current between test algorithms, number cycles that used parallel instructions counted kernel each test, excluding modifications that were required enable continuous looping oscilloscope triggering. Table shows results CONTROL, CXFIR, FFT99 algorithms. "Cycles" column1 shows total number cycles required pass through kernel. "Parallel" column shows number cycles which parallel instructions occurred, Parallel" column shows percentage total cycles kernel where parallel instructions occurred. CONTROL code contains parallel instructions. Fifty percent cycles CXFIR code were parallel instructions, eighty-five percent cycles FFT99 code used parallel instructions. Although these algorithms perform equivalent tasks, given operating frequency extra current from non-linear code clearly demonstrated (more nodes switching).
Table Total Parallel Cycle Counts CONTROL, CXFIR, FFT99 Algorithms
Benchmark CONTROL CXFIR FFT99 Description Control benchmark Block complex 256-point Cycles 2866 8825 Parallel 1442 7524 Parallel
core current each processor every test algorithm plotted against operating frequency verify linear relationship between core current frequency. Figure page shows data plotted FFT99 algorithm representative data other algorithms, which were similarly linear. There linear relationship between core current operating frequency given algorithm. current valid operating frequency calculated from slope Y-intercept best-fit line data. calculated slope Y-intercept values each test algorithm tabulated Table page slope expressed units mA/MHz, also expressed mA/MIPS because DSP563xx core execute single instruction every clock cycle. Y-intercept non-zero cases, expressed units that typical value mA/MIPS that published manufacturers overestimates slope best-fit line because typical published value assumes Y-intercept zero. Instead, cases typical published value always higher than calculated slope.
Benchmark cycle counts used with permission, 2001 Berkley Design Technology, Inc. www.bdti.com
Current Measurement Results Analysis More Information This Product, www.freescale.com
Figure Linear Relationship Between Core Current Frequency Table Slope Y-Intercept Best-Fit Line Each Algorithm Processor
Slope (mA/MHz) 56301 BITUPK BLKFIR CONTROL CXFIR FFT99 (MOT) SSFIR VECMAX VECPROD VECSUM VITERBI 1.24 1.38 0.94 1.66 1.50 1.10 1.12 1.40 1.20 1.24 1.20 1.34 1.20 56303 1.16 1.34 0.96 1.54 1.60 1.16 1.12 1.36 1.20 1.32 1.22 1.34 1.30 56307 0.90 1.00 0.74 1.14 1.14 0.96 0.84 1.10 0.92 1.04 0.94 1.10 1.08 56309 1.38 1.32 0.96 1.70 1.70 1.28 1.26 1.50 1.30 1.48 1.30 1.50 1.42 56311 0.60 0.72 0.54 0.84 0.82 0.64 0.61 0.80 0.72 0.76 0.72 0.84 0.67 56301 16.3 16.8 20.2 20.8 19.8 20.0 19.3 20.0 26.0 20.0 20.5 25.3 56303 18.0 21.2 21.7 20.8 15.0 18.0 21.7 23.7 22.7 22.3 22.8 22.2 19.8 Y-Intercept (mA) 56307 17.8 19.7 18.2 22.8 21.5 12.3 22.0 19.5 21.7 20.7 18.5 19.8 16.3 56309 15.2 29.0 30.3 20.8 20.8 20.0 21.5 25.8 24.2 24.0 24.2 23.5 23.2 56311 22.9 22.0 17.4 17.6 28.0 20.3 22.6 20.0 16.3 19.6 21.7 18.9 33.4
should noted that slope best-fit line varies magnitude depending algorithm, with CONTROL having shallowest slope CXFIR FFT99 steepest, that other algorithms more less followed same ranking core current values. This, again, appears
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Freescale Semiconductor,Current-Sensing Power Supply Inc.
relate directly linearity application under execution, consistent with relationship expressed Equation page With more switching nodes, value Cswitch increases, which effectively increases slope current with respect frequency. average every column Y-intercept data, well every value Table page approximately with average values table being 20.9 This indicates Y-intercept constant across processors measured, meaning that current-versus-frequency lines pivot point MHz, with slope line being dependent degree non-linearity code under execution. measurements performed this application note revealed that several Motorola's evaluation boards could easily modified perform core current measurements. particular, DSP56303EVM (100 version only), DSP56307EVM, DSP56309EVM used current-sensing power supply output applied center jumper block J11. Please note that DSP56303EVM requires that trace bottom side board, because jumper present connection hard-wired. DSP56311EVM used removing jumper applying external power supply output side jumper block. cases, externally applied voltage must appropriate particular should follow application power board's power supply input. Better still, input current-sensing power supply should derived from output EVM's bridge rectifier that core power supplies come unison.
Summary Conclusion
This application note discussed simple, low-cost method characterizing CMOS current consumption application board while running actual application code. This discussion included methods optimize application code, code structure, operating frequency minimum power consumption. These methods satisfy increasing need conserve power minimize heat dissipation with increasing digital signal processors battery-operated, portable applications.
Current-Sensing Power Supply
current-sensing power supply successfully demonstrated measuring core current five members DSP563xx family. While there some fluctuation output voltage with core current, power supply suitable optimizing application sensitive, low-power applications. avoids expense series resistance current probes problems with using traditional ammeter. additional current from output voltage programming resistors only about which negligible compared core current. While attempt made optimize prototype power supply, there undoubtedly other power supply designs that would reduce amount noise very small currents that would better respond large quick changes current.
Core Current
When core current five members DSP563xx family measured using prototype current-sensing power supply with several different test algorithms, core current found vary magnitude relation non-linearity application code -that amount code that used parallel moves. core current also found vary linearly with frequency each combination processor test algorithm. slope best-fit line varied magnitude same current relation test algorithm given combination. These findings consistent with relationship between core current, frequency, switching node capacitance, voltage.
Summary Conclusion More Information This Product, www.freescale.com
Y-intercept best-fit lines core current versus frequency appeared constant across processors, frequencies, test algorithms used. This indicates that core-current-versus-frequency relationship application code intersects common point MHz.
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