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Revised MOSFET Model With Dynamic Temperature Compensation
Alain Laprade, Scott Pearson, Stan Benczkowski, Gary Dolny, Frank Wheatley
Abstract
empirical self-heating SPICE MOSFET model which accurately portrays vertical DMOS power MOSFET electrical thermal responses presented. This macromodel implementation culmination years evolution MOSFET modeling. This version brings together thermal electrical models VDMOS MOSFET. existing electrical model [2,3] highly accurate recognized industry. Simulation response self-heating MOSFET model track dynamic thermal response independent SPICE's global temperature definition. Existing models upgraded self-heating models with relative ease.
Introduction
Many power MOSFET models available today based ideal lateral MOSFET device. They offer poor correlation between simulated actual circuit performance several areas. They have high current inaccuracies that could mislead power circuit designers. This situation further complicated dynamic performance models. ideal power SPICE level-1 NMOS MOSFET model does account nonlinear capacitive characteristics Ciss, Coss, Crss power MOSFET. Higher level SPICE MOSFET models used implement non-linear capacitance with mixed results. inherent inaccuracies modeling power VDMOS with SPICE MOSFET model dictated need alternative approach; macro-model. macro-model such defined Wheatley Hepp address short comings ideal power SPICE MOSFET model. Highly accurate results possible surrounding ideal level-1 MOSFET model with resistive, capacitive, inductive other SPICE circuit elements. examples will illustrate approach: demonstrated that third parallel MOSFET required accurately model exponential relationship drain current gate-tosource voltage
©2003 Fairchild Semiconductor Corporation
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sub-threshold region. implementation network (figure using switches provided method precisely model non-linear capacitance. result accurate representation dynamic transition between blocking conduction. need this higher level modeling accuracy becomes apparent high frequency applications where gate charge losses proportion overall losses become significant. same situation exists space charge limiting effect high drain current. MOSFET model reference which this work based been explained reader encouraged refer these references full understanding MOSFET model parameters herein referenced standard SPICE MOSFET model. Recent works have demonstrated methods circumventing SPICE global temperature definition, providing means using device's junction temperature self-heating feedback mechanism. model developed limitations involving proprietary algorithms, rendering method limited interest. Model implementation convoluted, involving MOSFET analog behavioral model (ABM) implementation whose operating characteristics dependent SPICE level-3 NMOS MOSFET. result, both switching circuit load must duplicated model function. implementation does model drain-source avalanche property MOSFET. Neither attempt model temperature characteristics intrinsic body diode. Introduced self-heating modeling concepts non-proprietary adapted other MOSFET models.
Standard SPICE MOSFET Model
macro-model Figure that used numerous Fairchild MOSFET device models. evolution many years work improvements from numerous contributors [1-7]. significant advantage this model that extensive knowledge device physics process details required implementing parametric data within model. following data curves basis used generate macromodel model over temperature: transfer characteristic saturation characteristic
©2003 Fairchild Semiconductor Corporation
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rDS(ON) gate threshold voltage drain-to-source breakdown voltage intrinsic body diode voltage capacitance versus drain-to-source voltage gate charge waveform Parametric data five temperature points used model calibration resulting macro-model that provides representative simulation data rated operating junction temperature. limitation standard MOSFET model found when simulating high power pulsed dissipations, paralleled device operation. Reliance SPICE MOSFET primitive global analysis temperature variable (.TEMP SPICE instruction) results simulations having MOSFETs operating single predefined temperature. Device behaviour under high power dissipation transitory excursions paralleled operation cannot accurately modeled with globally assigned temperature. Threshold voltage rDS(ON) important temperature dependant device characteristics that vary sufficiently power dissipation render simulation inaccurate. Accurate modeling previously mentioned operating modes requires incorporating temperature device behaviour model level rather than global level.
LDRAIN DPLCAP DRAIN RLDRAIN
RSLC2
RSLC1
ESLC DBREAK DBODY RDRAIN EBREAK
GATE
LGATE RGATE RLGATE EVTEMP
Figure Standard MOSFET macro-model dependent global temperature definition
Self-Heating SPICE MOSFET Model
Improved implementation static dynamic behavior achieved with self©2003 Fairchild Semiconductor Corporation
EVTHRES
MMED
MSTRO LSOURCE RSOURCE RBREAK RLSOURCE SOURCE
RVTEMP VBAT RVTHRES
Rev.
heating SPICE MOSFET model (Figure evolution standard MOSFET model (Figure Temperature dependent model parameters respond closed loop form junction temperature information provided node Performance independent SPICE's global temperature definition .TEMP temperature option TNOM, circumventing level-1 NMOS model primitive temperature limitation. MOSFET operating losses inclusive current source G_Pdiss (scaling dissipation) representing instantaneous power dissipation into thermal model. Multiple MOSFETs simulated different variable junction temperatures. Each MOSFET connected heat sink model node Tcase. heat sink model device specific, heat sink optimization becomes possible. Current source G_Pdiss referenced simulation ground reference, permitting model bridge topologies.
LDRAIN DPLCAP RLDRAIN RSLC2 G_RSLC1 DRAIN RTHERM1 CTHERM1
ESLC
DBREAK
DBODY
RTHERM2 CTHERM2
GATE
RGATE RLGATE
EVTEMP
LGATE
Figure Self-heating MOSFET macro-model independent global temperature definition
example symbol representation self-heating MOSFET model shown Figure Symbol files OrCAD's circuit entry tools "PSpice Schematic" "OrCAD Capture"may downloaded from www.fairchildsemi.com. Recommended symbol implementation designate pinout attribute optional (ERC DON'T CARE). representation device junction temperature. used monitoring point, connected defined voltage source override self-heating feature. Tcase must connected heat sink model. Treatment connections model's gate, drain, source terminals different than those standard MOSFET model.
Figure Self-heating MOSFET SPICE symbol
©2003 Fairchild Semiconductor Corporation
G_RDRAIN EBREAK EVTHRES MMED G_RDBREAK MSTRO G_RSOURCE MWEAK
EDBODY
RTHERM4 CTHERM4 RDBODY RTHERM3 CTHERM3
G_RDBODY
LSOURCE RLSOURCE SOURCE
RTHERM5 CTHERM5
RTHERM6 CTHERM6 G_PDISS
Tcase
Rev.
Self-Heating Model Implementation
Ability describe value resistor temperature coefficients behavioral model referenced voltage node necessary express dependence junction temperature. PSPICE resistor ABMs permit voltage node references. Dynamic temperature dependence MOSFET's resistive element (expressed separate lumped elements) diode's resistive component cannot implemented without resistor ABM. This limitation overcome with voltage controlled current source expression (Figure using nodes current source voltage control, resistor behaviour expressed V/R(Tj). resistance R(Tj) becomes behavioral model expression dependent voltage node representation junction temperature. This voltage-controlled current source model used modify standard MOSFET model from Figure implementing voltage dependent expressions RDRAIN, RSOURCE, RSLC1. Behavioral expressions were implemented self-heating model eliminate RBREAK, RVTEMP, VBAT through modification expressions EVTEMP, EVTHRES, EBREAK.
I=V/R(Tj)
Figure Implementing voltage dependent resistor model
Temperature dependent resistive elements diodes DBODY DBREAK were separated from diode model, expressed voltagecontrolled current source models G_RDBODY G_RDBREAK. large value resistor RDBODY added improve convergence. EDBODY added series with DBODY incorporate temperature dependency intrinsic body diode forward conduction drop. Junction temperature information implemented inclusion MOSFET's thermal network current source G_PDISS. thermal network parameters supplied Fairchild data sheets. G_PDISS calculates MOSFET instantaneous operating loss, expresses result form current using scaling ratio This circuit form implementation junction temperature from expression
©2003 Fairchild Semiconductor Corporation
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Pdissipation Tcase
where junction temperature, Pdissipation instantaneous power loss, thermal impedance junction-to-case Tcase case temperature. Tcase scaling factor 1oC.
Simulation Results
unclamped inductive switching (UIS) test circuit Figure used compare performance FDP038AN06A0 (3.8 60V, TO-220) self-heating MOSFET model with that standard model measurement results. Incircuit measurements were performed with device case temperature interfaced large heatsink temperature 25oC.
Figure simulation circuit
simulation standard MOSFET model performed with PSPICE TNOM .TEMP variables 25oC (Figure lack temperature feedback model results drain-source breakdown voltage that only drain current dependent. does demonstrate device's breakdown voltage positive temperature coefficient. Source resistance (G_Rsource) added lower gain high currents. also contributing element device rDS(ON). Plotting square root versus results linear curve instead quadratic curve, thus improving visual resolution data higher current range.
©2003 Fairchild Semiconductor Corporation
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Volts Amps
Drain Current Drain Voltage Measured Drain Voltage Measured Drain Current Junction Temperature
Temperature
Time (ms)
Figure FDP038AN06A0 standard model simulation results
simulation measured results selfheating MOSFET model shown Figure Simulated drain-source breakdown voltage demonstrates model dependence drain current well junction temperature. Excellent agreement exits.
Volts Amps Time (ms) Temperature
Drain Current Drain Voltage Measured Drain Voltage Measured Drain Current Junction Temperature
Figure FDP038AN06A0 self-heating model simulation results
Accuracy self-heating model further verified comparing performance with that standard model, with characterization data from which standard model developed. Results shown Figures gate threshold, rDS(ON), conduction saturation voltage. Excellent agreement exists.
©2003 Fairchild Semiconductor Corporation
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FDP038AN08A0 Data Standard Model Self-Heating Model
VGS(TH)
Temperature
Figure FDP038AN06A0 threshold voltage Conditions: 250µA
small threshold voltage difference between models exists device junction temperature approaches 175oC, well within device yield parametric variation. This result different approaches used modeling intrinsic body diode. standard model intrinsic body diode sensitive PSPICE TNOM temperature option definition. temperature dependency TNOM eliminated self-heating model. result, self-heating model intrinsic body diode does exhibit leakage current's temperature dependence.
FDP038AN08A0 Data Standard Model Self-Heating Model
RDS(ON)
Temperature
Figure FDP038AN08A0 rDS(ON) Conditions: 80A,
©2003 Fairchild Semiconductor Corporation
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FDP038AN08A0 Data Standard Model Self-Heating Model
+25oC
+125oC
Figure FDB038AN08A0 saturation voltage Conditions:
Simulation Convergence
self-heating model tested under numerous circuit configurations. found numerically stable. Failure converge occur under some large signal simulations PSPICE's setup option ABSTOL setting less than 1µA. simulations were performed Dell Latitude having 500MHz Pentium processor with 256MB memory. Windows 2000 operating system used with virus scan software enabled. PSPICE Schematics version used. Simulation time results were: standard model 7.9s self-heating model 13.7s Simulation time expected longer with self-heating model dynamic interaction junction temperature feedback.
Future Model Developments
Minor inaccuracy introduced previously published Fairchild Semiconductor MOSFET models modified become self-heating models, within device parametric tolerance (this demonstrated this paper). inaccuracy eliminated including variable T_ABS=25 level-1 NMOS MOSFET during device specific model calibration, permitting full compatibility model with self-heating model. This term included standard MOSFET model calibration FDP038AN06A0. Temperature dependency self-heating model intrinsic body diode leakage current could introduced adding junction temperature dependent current source across body diode.
©2003 Fairchild Semiconductor Corporation
Rev.
Conclusion
self heating PSPICE power MOSFET macromodel provides next evolutionary step circuit simulation accuracy. inclusion thermal model coupled temperature sensitive MOSFET electrical parameters results selfheating PSPICE MOSFET macro-model which allows increased accuracy during time domain simulations. effect temperature change power dissipation during time domain simulations modeled. modeling modification concepts introduced non-proprietary adapted MOSFET SPICE models from manufacturer.
References
W.J. Hepp, Wheatley, PSPICE Subcircuit Power MOSFET Featuring Global Temperature Options", IEEE Transactions Power Electronics Specialist Conference Records, 1991 533-544. PSPICE Subcircuit Power MOSFET Featuring Global Temperature Options", Fairchild Semiconductor, Application Note AN-7510, October 1999. Benczkowski, Mancini, "Improved MOSFET Model", PCIM, September 1998, 64-69. G.M. Dolny, H.R. Ronan, Jr., C.F. Wheatley, Jr., SPICE Subcircuit Representation Power MOSFETs Using Empirical Methods," Review", Sept 1985. C.F. Wheatley, Jr., H.R. Ronan, Jr., G.M. Dolny, "Spicing- SPICE Software Power MOSFET Modeling," Fairchild Semiconductor, Application Note AN7506, February 1994. C.F. Wheatley, H.R. Ronan, Jr., "Switching Waveforms FET: 5Volt Gate Drive Power MOSFET," Power Electronics Specialist Conference Record, June 1984, 238. G.M. Dolny, C.F. Wheatley, Jr., H.R. Ronan, Jr., "Computer Aided Analysis Gate-Voltage Propagation Effects Power MOSFETs", Proc. HFPC, 1986, 146. Giovanni, Bazzano, Grimaldi, PSPICE Power MOSFET Subcircuit with Associated Thermal Model", PCIM 2002 Europe, 271-276. Nance, "Thermal Modeling Power-electronic Systems", Infineon Technologies, Application Note, mmpn_eng.pdf.
©2003 Fairchild Semiconductor Corporation
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Appendix Standard MOSFET SPICE Model
.SUBCKT FDP038AN06A0 *Nom Temp=25 February 2003 1.5e-9 1.5e-9 6.1e-9 Dbody DbodyMOD Dbreak DbreakMOD Dplcap DplcapMOD Ebreak 69.3 Evthres Evtemp Lgate 4.81e-9 Ldrain 1.0e-9 Lsource 4.63e-9 RLgate 48.1 RLdrain RLsource 46.3 Mmed MmedMOD Mstro MstroMOD Mweak MweakMOD Rbreak RbreakMOD Rdrain RdrainMOD 1.0e-4 Rgate 1.36 RSLC1 RSLCMOD 1e-6 RSLC2 Rsource RsourceMOD 2.8e-3 Rvthres RvthresMOD Rvtemp RvtempMOD S1AMOD S1BMOD S2AMOD S2BMOD Vbat ESLC +(1e-6*300),10))} .MODEL DbodyMOD (IS=2.4E-11 N=1.04 RS=1.65e-3 TRS1=2.7e-3 TRS2=2e-7 CJO=4.35e-9 M=5.4e-1 TT=1e-9 XTI=3.9) .MODEL DbreakMOD (RS=7.0e-2 TRS1=5e-4 TRS2=1.0e-7) .MODEL DplcapMOD (CJO=1.7e-9 IS=1e-30 N=10 M=0.47) .MODEL MmedMOD NMOS (VTO=3.3 KP=9 IS=1e-30 N=10 TOX=1
©2003 Fairchild Semiconductor Corporation
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L=1u W=1u RG=1.36 T_abs=25) .MODEL MstroMOD NMOS (VTO=4.00 KP=275 IS=1e-30 N=10 TOX=1 L=1u W=1u T_abs=25) .MODEL MweakMOD NMOS (VTO=2.72 KP=0.03 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=13.6 RS=.1 T_abs=25) .MODEL RbreakMOD (TC1=9e-4 TC2=1e-7) .MODEL RdrainMOD (TC1=5.5e-2 TC2=3.2e-4) .MODEL RSLCMOD (TC1=1e-3 TC2=1e-5) .MODEL RsourceMOD (TC1=5e-3 TC2=1e-6) .MODEL RvthresMOD (TC1=-6.7e-3 TC2=-1.5e-5) .MODEL RvtempMOD (TC1=-2.5e-3 TC2=1e-6) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-1.5) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=-4) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1 VOFF=.5) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=.5 VOFF=-1) .ENDS *Thermal Model Subcircuit .SUBCKT FDP038AN06A0_Thermal CTHERM1 6.45e-3 CTHERM2 3e-2 CTHERM3 1.4e-2 CTHERM4 1.65e-2 CTHERM5 4.85e-2 CTHERM6 1e-1 RTHERM1 3.24e-3 RTHERM2 8.08e-3 RTHERM3 2.28e-2 RTHERM4 1e-1 RTHERM5 1.1e-1 RTHERM6 1.4e-1 .ends
©2003 Fairchild Semiconductor Corporation
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Appendix Self-Heating MOSFET SPICE Model
.SUBCKT FDP038AN06A0_5NODE Tcase Spice model FDP038AN06A0 February 2003 1.5e-9 1.5e-9 6.1e-9 EDbody Dbody DbodyMOD Dbreak DbreakMOD Dplcap DplcapMOD RDBODY 1E15 G_Rdbody +2E-7*PWR((V(Tj,0)-25),2)))} G_Rdbreak +1e-7*PWR((V(Tj,0)-25),2)))} Ebreak +PWR((V(Tj,0)-25),2))} Evthres Evtemp Lgate 4.81e-9 Ldrain 1.0e-9 Lsource 4.63e-9 RLgate 48.1 RLdrain RLsource 46.3 Mmed MmedMOD Mstro MstroMOD Mweak MweakMOD G_Rdrain +3.2E-4*pwr((v(Tj,0)-25),2)))} Rgate 1.36 G_RSLC1 +1E-5*pwr((v(Tj,0)-25),2)))} RSLC2 G_Rsource +1e-6*pwr((V(Tj,0)-25),2)))} S1AMOD S1BMOD S2AMOD S2BMOD ESLC +(1e-6*300),10))} G_PDISS VALUE={I(ESLC)*V(5,7) I(EVTEMP)*V(9,7)
©2003 Fairchild Semiconductor Corporation
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I(EBREAK)*V(5,7) I(EDBODY)*V(7,5)}CTHERM1 6.45E-3 CTHERM2 3e-2 CTHERM3 1.4e-2 CTHERM4 1.65e-2 CTHERM5 4.85e-2 CTHERM6 Tcase 1e-1 RTHERM1 3.24e-3 RTHERM2 8.08e-3 RTHERM3 2.28e-2 RTHERM4 1e-1 RTHERM5 1.1e-1 RTHERM6 Tcase 1.4e-1 .MODEL DbodyMOD (T_ABS=25 IS=2.4E-11 N=1.04 CJO=4.35e-9 M=0.54 TT=1.0e-9 XTI=3.9) .MODEL DbreakMOD .MODEL DplcapMOD (CJO=1.7e-9 IS=1e-30 N=10 M=0.47) .MODEL MmedMOD NMOS (T_ABS=25 VTO=3.3 KP=9 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.36) .MODEL MstroMOD NMOS (T_ABS=25 VTO=4.0 KP=275 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MweakMOD NMOS (T_ABS=25 VTO=2.72 KP=0.03 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=13.6 RS=.1) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-1.5) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=-4) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1 VOFF=.5) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=.5 VOFF=-1) .ENDS
©2003 Fairchild Semiconductor Corporation
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