PSPICE Electro-Thermal Subcircuit Power MOSFETs Alain Laprade, Sc

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PSPICE Electro-Thermal Subcircuit Power MOSFETs Alain Laprade, Sc

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PSPICE Electro-Thermal Subcircuit Power MOSFETs
Alain Laprade, Scott Pearson, Stan Benczkowski, Gary Dolny, Frank Wheatley
Keywords
Device characterization, device modeling, high power discrete devices, modeling, device, power semiconductor devices, semiconductor devices, simulation, thermal design.
Abstract
empirical self-heating SPICE MOSFET model which accurately portrays vertical DMOS power MOSFET electrical thermal responses presented. This macro-model implementation culmination years evolution MOSFET modeling. This version brings together thermal electrical models VDMOS MOSFET. existing electrical model [2,3] highly accurate recognized industry. sequence model calibration procedure using parametric data described. Simulation response self-heating MOSFET model track dynamic thermal response independent SPICE's global temperature definition.
Introduction
Many power MOSFET models available today based ideal lateral MOSFET device. They offer poor correlation between simulated actual circuit performance several areas. They have high current inaccuracies that could mislead power circuit designers. This situation further complicated dynamic performance models. ideal power SPICE level-1 NMOS MOSFET model does account nonlinear capacitive characteristics Ciss, Coss, Crss power MOSFET. Higher level SPICE MOSFET models used implement non-linear capacitance with mixed results. need this higher level modeling accuracy becomes apparent high frequency applications where gate charge losses proportion overall losses become significant. inherent inaccuracies modeling power VDMOS with SPICE MOSFET model dictated need alternative approach; macro-model. macro-model such defined Wheatley Hepp address short comings ideal power SPICE MOSFET model. Highly accurate results
©2003 Fairchild Semiconductor Corporation
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possible surrounding temperature independent gain block (implemented using three level-1 MOSFET models) with resistive, capacitive, inductive other SPICE circuit elements. possible develop model from parametric measurements single iteration. model extraction procedure from parametric data must follow given sequence. Many changes model affect different behaviour. Failure follow this sequence will result repeated model calibration iterations. MOSFET model reference which this work based been explained 10]. reader encouraged refer these references full understanding MOSFET model parameters herein referenced. model, once extracted discussed here, reference [10] addresses use. Recent works have demonstrated methods circumventing SPICE global temperature definition, providing means using device's junction temperature self-heating feedback mechanism. model developed limitations involving proprietary algorithms, rendering method limited interest. Model implementation convoluted, involving MOSFET analog behavioral model (ABM) implementation whose operating characteristics dependent SPICE level-3 NMOS MOSFET. result, both switching circuit load must duplicated model function. implementation does model drain-source avalanche property MOSFET. Neither attempt model temperature characteristics intrinsic body diode. Introduced self-heating modeling concepts non-proprietary adapted other MOSFET models.
Self-Heating SPICE MOSFET Model
self-heating macro-model from Figure evolution years work improvements from numerous authors [1-7]. significant advantage this model that knowledge device physics process details necessary implement parametric data within model. Parametric data several temperature points used model calibration resulting macromodel which provides representative simulation data rated operating junction temperature. Temperature dependent model parameters respond closed loop form junction temperature information provided node Performance independent SPICE's global temperature definition listed .TEMP temperature option TNOM, circumventing level-1 NMOS model primitive temperature limitation. MOSFET operating losses inclusive current source G_Pdiss representing instanta©2003 Fairchild Semiconductor Corporation
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neous power dissipation into thermal model.
LDRAIN DPLCAP RLDRAIN RSLC2 G_RSLC1 DRAIN RTHERM1 CTHERM1
GATE
ESLC
DBREAK
DBODY
RTHERM2 CTHERM2
EDBODY
RGATE RLGATE
EVTEMP
LGATE
Figure Self-heating MOSFET macro-model independent global temperature definition
Figure Self-heating MOSFET macro-model independent global temperature definition
Multiple MOSFETs simulated different variable junction temperatures. Each MOSFET connected heat sink model node Tcase. heat sink model device specific, heat sink optimization becomes possible. Current source G_Pdiss referenced simulation ground reference, permitting model bridge topologies. example symbol representation self-heating MOSFET model shown Figure Symbol files OrCAD's circuit entry tools "PSPICE Schematic" "OrCAD Capture" downloaded from www.fairchildsemi.com. Recommended symbol implementation designate pinout attribute optional (ERC DON'T CARE, Float=UniqueNet). representation device junction temperature. used monitoring point, connected defined voltage source override self-heating feature. Tcase must connected heat sink model. Treatment connections model's gate, drain, source terminals different than those standard MOSFET model.
Figure Self-heating MOSFET symbol
Self-Heating SPICE MOSFET Model
Ability describe value resistor temperature coefficients behavioral model referenced voltage node necessary express dependence junction temperature. PSPICE resistor ABMs permit voltage node references.
©2003 Fairchild Semiconductor Corporation
G_RDRAIN EBREAK EVTHRES MMED G_RDBREAK MSTRO G_RSOURCE MWEAK
RTHERM4 CTHERM4 RDBODY RTHERM3 CTHERM3
G_RDBODY
LSOURCE RLSOURCE SOURCE
RTHERM5 CTHERM5
RTHERM6 CTHERM6 G_PDISS
Tcase
Rev.
Dynamic temperature dependence MOSFET's resistive element (expressed separate lumped elements) diode's resistive component cannot implemented without resistor ABM. This limitation overcome with voltage-controlled current source expression (Figure using nodes current source voltage control, resistor behaviour expressed V/R(Tj). resistance R(Tj) replaced behavioral model expression dependent voltage node representation junction temperature. This voltage-controlled current source model used implement voltage dependent expressions RDRAIN, RSOURCE, RSLC1.
I=V/R(Tj)
Figure Implementing voltage dependent resistor model
Temperature dependent resistive elements diodes DBODY DBREAK were separated from diode model, expressed voltage-controlled current source models G_RDBODY G_RDBREAK. very large value resistor RDBODY added improve convergence. EDBODY added series with DBODY incorporate temperature dependency intrinsic body diode forward conduction drop. Junction temperature information implemented inclusion MOSFET's thermal network current source G_PDISS. thermal network parameters supplied Fairchild Semiconductor data sheets. G_PDISS calculates MOSFET instantaneous operating loss, expresses result form current. This circuit form implementation junction temperature from expression
Pdissipation Tcase
where junction temperature, Pdissipation instantaneous power loss, thermal impedance junction- to-case Tcase case temperature. unit conversion electrical analogy thermal system listed Table
Electrical Farad Volt Thermal C/Watt Joules/oC Watt
Table Electrical/thermal analogy
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Parameter Extraction Methodology
sequence parameter extraction procedure very important since many changes library affect different behavior. instance, changing parameters transfer curve affect saturation curves. recommended methodology shown below. transfer curve saturation curve body diode forward conduction Breakdown voltage Capacitance (Crss, Coss, Ciss) Gate charge Temperature coefficients Thermal model Extraction achieved more rapidly data plotted log-log, semilog, versus etc. First extraction take days. becomes rapidly learned process with repeated usage.
Transfer Curve
Three level-1 MOSFET transistors used model gain block full current range from sub-threshold region through high current. three transistor models MweakMOD, MmedMOD MstroMOD. parameters each transistor used alignment model with measured data. .MODEL MmedMOD NMOS (VTO=3.3 KP=9 IS=1e-30 N=10 TOX=1 L=1u W=1u +RG=1.36 T_ABS=25) .MODEL MstroMOD NMOS (VTO=4.0 KP=275 IS=1e-30 N=10 TOX=1 L=1u W=1u +T_ABS=25) .MODEL MweakMOD NMOS (VTO=2.72 KP=0.03 IS=1e-30 N=10 TOX=1 L=1u +W=1u RG=13.6 RS=0.1 T_ABS=25) Source resistance (G_Rsource) added lower gain high currents. also contributing element device rDS(ON). Plotting square root versus results linear curve instead quadratic curve, thus improving visual resolution data higher current range. G_Rsource
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Saturation Curves
Several gate biases should used model saturation curves. instance, model standard gate device 10V, 3.5V. G_Rdrain used model linear region. Increasing G_Rdrain will decrease current saturation curves. Next, space charge limiting effect modeled using ESLC. multiplier ESLC (1e-6*X, exponent power statement) adjusted. Lowering will round curves high currents. saturation curves (for instance Vgs=10V Vgs=5V) match linear region, necessary readjust strong transistor MstroMOD. Modeling between transfer saturation curves will then need repeated until both curves data. G_Rdrain VALUE={V(50,16)/(1e-4* ESLC VALUE={(V(5,51)/ABS(V(5,51))) *(PWR(V(5,51)/(1e +6*300),10))}
Body Diode Forward Voltage
Match diode curve data currents adjusting parameters DbodyMOD. With forward voltage plotted scale, will adjust slope will shift curve left right. .MODEL DbodyMOD (IS=2.4e-11 N=1.04 CJO=4.35e-9 M=0.54 TT=1.0e-9 +XTI=3.9 T_ABS=25) high current region modeled linear scale. G_Rdbody used match diode curve data high currents adding series resistance, thus lowering curve. G_Rdbody VALUE={V(7,31)/(1.65e-3* used smooth transition region between currents high currents. After changing IKF, often necessary readjust G_Rdbody. .MODEL DbodyMOD (IS=2.4e-11 N=1.04 CJO=4.35e-9 M=0.54 TT=1.0e-9 +XTI=3.9 IKF=100 T_ABS=25)
Breakdown Voltage
current breakdown modeled with Ebreak. Ebreak VALUE={69.3*(1+9.5e-4* High current breakdown modeled with G_Rdbreak.
©2003 Fairchild Semiconductor Corporation
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G_Rdbreak VALUE={v(32,7)/(7.0e-2* (1+5e-4*(V(TH+)-25)+1e-7* +PWR((V(TH+)-25),2)))}
Intrinsic body diode reverse recovery modeled 100A/µS maximum rated current. Parameter body diode DbodyMOD used match modeled measured .MODEL DbodyMOD (IS=2.4e-11 N=1.04 CJO=4.35e-9 M=0.54 TT=1.0e-9 +XTI=3.9 T_ABS=25)
Capacitance
Capacitance modeled drain-to-source voltages 0.1V breakdown voltage. Crss modeled first, setting DplcapMOD. will adjust level capacitance curve while will adjust slope. Next, Coss modeled with DbodyMOD. This done similar manner Crss. Finally input capacitance Ciss adjusted setting model. .MODEL DplcapMOD (CJO=1.7e-9 IS=1e-30 N=10 M=0.47) .MODEL DbodyMOD (IS=2.4e-11 N=1.04 CJO=4.35e-9 M=0.54 TT=1.0e-9 +XTI=3.9 T_ABS=25) 6.1e-9
Gate Charge
Modeling gate charge curve four step process (Figure First, adjust slope through most negative gate voltages adjusting Next, adjust slope breakpoint adjusting switch voltages (VON VOFF) account discontinuity between slopes negative voltages. VOFF S1AMOD S1BMOD should reverse another (VON S1AMOD should VOFF S1BMOD, vice versa).
Figure Modeling gate charge
©2003 Fairchild Semiconductor Corporation
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1.5e-9 .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-1.5) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=-4) Third, switch voltages adjusted length plateau region. voltage level plateau will setup modeling done transfer curve adjusted this point. S2AMOD S2BMOD should reverse each other stated above S1AMOD S1BMOD. Fourth, adjust slope curve above plateau adjusting should nearly identical value. 1.5e-9 .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1 VOFF=0.5) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.5 VOFF=-1) values switches through should increasing positive direction. There should minimum 0.5V separating each value. Reduction separation below 0.5V result convergence errors.
Temperature Coefficients
Repeat steps through high temperature (ex. -25oC 125oC). step saturation curves, only gate bias will used temperature coefficient matching should gate voltage that used rating rDS(ON). Temperature coefficients factor transient analyses (capacitance, gate charge). Transfer Curve: high currents adjust temperature parameters Evtemp. currents adjust temperature parameters Evthres. temperature coefficients G_Rsource used curve high currents. first parameter highlighted each line below linear coefficient second square function coefficient. Evtemp VALUE={-2.5e-3*(V(TH+)-25) +1e-6*PWR((V(TH+)-25),2)} Evthres G_Rsource VALUE={V(8,7)/(2.5e-3* +,2)))} Saturation Curves: First adjust temperature parameters G_Rdrain. Then model temperature parameters G_RSLC1. This models space charge limiting effect over temperature. G_Rdrain VALUE={V(50,16)/(1e-4* G_RSLC1 VALUE={v(5,51)/(1e-6*
©2003 Fairchild Semiconductor Corporation
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Body Diode Forward Voltage: currents forward voltage modeled with temperature coefficients EDbody. last parameter EDbody used limit above 175oC. Thermal parameters G_Rdbody used model high current region. EDbody VALUE={IF(V(TH+)<175, -1.5e-3*V(TH+)+.03,0.2325)} G_Rdbody VALUE={V(7,31)/(1.65e-3* (1+2.7e-3*(V(TH+)-25)+2e-7* +PWR((V(TH+)-25),2)))} Breakdown voltage: current breakdown modeled with thermal parameters Ebreak. Thermal parameters G_Rdbreak used model high current. G_Rdbreak VALUE={v(32,7)/(7.0e-2* Ebreak VALUE={69.3*(1+9.5e-4*
Thermal Model
thermal model modeled independently electrical model. Components CTHERM1 through CTHERM6 RTHERM1 through RTHERM6 used simulated thermal impedance curve measured data. ensure good thermal model, thermal capacitors should increasing value from CTHERM1 through CTHERM6. Thermal resistors should also increasing value from RTHERM1 through RTHERM6. CTHERM1 6.45E-3 CTHERM2 3e-2 CTHERM3 1.4e-2 CTHERM4 1.65e-2 CTHERM5 4.85e-2 CTHERM6 Tcase 1e-1 RTHERM1 3.24e-3 RTHERM2 8.08e-3 RTHERM3 2.28e-2 RTHERM4 1e-1 RTHERM5 1.1e-1 RTHERM6 Tcase 1.4e-1
Simulation Results
Simulation results parametric data from MOSFET FDP038AN06A0 plotted Figures gate charge, gate threshold, rDS(ON), conduction saturation voltage. Excellent agreement exists.
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FDP038AN06A0 Data Standard Model Self-Heating Model
VGS(TH)
Temperature
Figure FDP038AN06A0 threshold voltage Conditions: 250µA
FDP038AN06A0 Data Standard Model Self-Heating Model
RDS(ON)
Temperature (oC)
Figure FDP038AN06A0 rDS(ON) Conditions: 80A,
FDP038AN06A0 Data Standard Model Self-Heating Model
+125
Figure FDP038AN06A0 saturation voltage Conditions:
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Simulation Convergence
self-heating model tested under numerous circuit configurations. found numerically stable. Failure converge occur under some large signal simulations PSPICE's setup option ABSTOL setting less than 1µA. simulations [10] were performed Dell Latitude having 500MHz Pentium processor with 256MB RAM. Windows 2000 operating system used with virus scan software enabled. PSPICE Schematics version used. Simulation time results were: standard model 7.9s self-heating model 13.7s Simulation time will longer with self-heating model when significant rapid junction temperature variation occurs. This result dynamic interaction from junction temperature feedback MOSFET temperature dependent parameters.
Future Model Developments
Minor inaccuracy introduced previously published Fairchild Semiconductor MOSFET models modified become self-heating models, well within device parametric tolerance (not demonstrated this paper). inaccuracy eliminated including variable T_ABS=25 level-1 NMOS MOSFET during device specific model calibration, permitting full compatibility model with self-heating model. This term included standard MOSFET model calibration FDP038AN06A0. Temperature dependency self-heating model intrinsic body diode leakage current could introduced adding junction temperature dependent current source across body diode.
Conclusion
self heating PSPICE power MOSFET macro-model provides next evolutionary step circuit simulation accuracy. inclusion thermal model coupled temperature sensitive MOSFET electrical parameters results self-heating PSPICE MOSFET macro-model which allows increased accuracy during time domain simulations. effect temperature change power dissipation during time domain simulations modeled. modeling modification concepts introduced non-proprietary adapted MOSFET SPICE models from manufacturer. methodology calibrating MOSFET model using parametric data described. Adherence calibration sequence yields highly accurate model.
©2003 Fairchild Semiconductor Corporation
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References
[1]. W.J. Hepp, Wheatley, PSPICE Subcircuit Power MOSFET Featuring Global Temperature Options", IEEE Transactions Power Electronics Specialist Conference Records, 1991 533-544. [2]. PSPICE Subcircuit Power MOSFET Featuring Global Temperature Options", Fairchild Semiconductor, Application Note AN-7510, October 1999. [3]. Benczkowski, Mancini, "Improved MOSFET Model", PCIM, September 1998, 64-69. [4]. G.M. Dolny, H.R. Ronan, Jr., C.F. Wheatley, Jr., SPICE Subcircuit Representation Power MOSFETs Using Empirical Methods," Review", Sept 1985. [5]. C.F. Wheatley, Jr., H.R. Ronan, Jr., G.M. Dolny, "Spicing-up SPICE Software Power MOSFET Modeling," Fairchild Semiconductor, Application Note AN7506, February 1994. [6]. C.F. Wheatley, H.R. Ronan, Jr., "Switching Waveforms FET: 5Volt Gate Drive Power MOSFET," Power Electronics Specialist Conference Record, June 1984, 238. [7]. G.M. Dolny, C.F. Wheatley, Jr., H.R. Ronan, Jr., "Computer Aided Analysis Gate-Voltage Propagation Effects Power MOSFETs", Proc. HFPC, 1986, 146. [8]. Giovanni, Bazzano, Grimaldi, PSPICE Power MOSFET Subcircuit with Associated Thermal Waveforms FET: 5Volt Gate Drive Power MOSFET," Power Electronics Specialist Conference Model", PCIM 2002 Europe, 271-276. [9]. Nance, "Thermal Modeling Power-electronic Systems", Infineon Technologies, Application Note, mmpn_eng.pdf. [10]. A.Laprade, Pearson, Benczkowski, Dolny, Wheatley; Revised MOSFET Model With Dynamic Temperature Compensation"; PCIM Shanghai 2003, p.177.
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Appendix Self-Heating MOSFET SPICE Model Listing
.SUBCKT FDP038AN06A0_5NODE Tcase 1.5e-9 1.5e-9 6.1e-9 EDbody Dbody DbodyMOD Dbreak DbreakMOD Dplcap DplcapMOD RDBODY 1E15 G_Rdbody G_Rdbreak Ebreak Evthres Evtemp Lgate 4.81e-9 Ldrain 1.0e-9 Lsource 4.63e-9 RLgate 48.1 RLdrain RLsource 46.3 Mmed MmedMOD Mstro MstroMOD Mweak MweakMOD G_Rdrain Rgate 1.36 G_RSLC1 RSLC2 G_Rsource S1AMOD S1BMOD S2AMOD S2BMOD ESLC G_PDISS VALUE={I(ESLC)*V(5,7) +I(EDBODY)*V(7,5)}
©2003 Fairchild Semiconductor Corporation
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CTHERM1 6.45E-3 CTHERM2 3e-2 CTHERM3 1.4e-2 CTHERM4 1.65e-2 CTHERM5 4.85e-2 CTHERM6 Tcase 1e-1 RTHERM1 3.24e-3 RTHERM2 8.08e-3 RTHERM3 2.28e-2 RTHERM4 1e-1 RTHERM5 1.1e-1 RTHERM6 Tcase 1.4e-1 .MODEL DbodyMOD (T_ABS=25 IS=2.4E-11 N=1.04 CJO=4.35e-9 M=0.54 +TT=1.0e-9 XTI=3.9) .MODEL DbreakMOD .MODEL DplcapMOD (CJO=1.7e-9 IS=1e-30 N=10 M=0.47) .MODEL MmedMOD NMOS (T_ABS=25 VTO=3.3 KP=9 IS=1e-30 N=10 TOX=1 +L=1u W=1u RG=1.36) .MODEL MstroMOD NMOS (T_ABS=25 VTO=4.0 KP=275 IS=1e-30 N=10 TOX=1 +L=1u W=1u) .MODEL MweakMOD NMOS (T_ABS=25 VTO=2.72 KP=0.03 IS=1e-30 N=10 TOX=1 +L=1u W=1u +RG=13.6 RS=.1) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-1.5) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=-4) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1 VOFF=.5) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=.5 VOFF=-1) .END
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PSPICE Electro-Thermal Subcircuit Power MOSFETs Alain Laprade, Sc

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