AN-5026 Fairchild Semiconductor Application Note January 2001 Rev

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AN-5026 Fairchild Semiconductor Application Note January 2001 Rev

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AN-5026 Using Packages
AN-5026
Fairchild Semiconductor Application Note January 2001 Revised September 2001
Using Packages
Introduction
Demanding space weight requirements personal computing portable electronic equipment many innovations packaging. Combining right interface logic products with package technology have significant impact capabilities formfactor product. Leaded surface mount devices constantly pushing manufacturing capabilities leading board manufacturers finer finer lead pitch geometry's increase density reduce board space. This requirement lead significant interest JEDEC (Joint Electron Device Engineering Council) registered Fine-Pitch Ball Grid Array (FBGA) package. These packages ideally suited cost, high volume applications, where package size performance major importance. Typical applications include: Notebook computers Personal Digital Assistants (PDA's) Mobile telephone handsets High density disk drives Camcorders Digital cameras advantages compared fine pitch TSSOP packages: BGAs usually smaller. BGAs have larger pitch. BGAs have fragile leads, that causes yield rework problems. Board assembly yields significantly improved. Board inspection reduced. BGAs have better thermal electrical properties. many applications, results significant system level cost savings. TABLE Space Savings Compared Surface Mount Packages Number Bits TSSOP TVSOP QVSOP BQSOP
65.50%
FIGURE Ball Surface Mount
Surface Mount
0.5mm pitch, race finer surface mount lead pitches several technical economic walls. Manufacturing anything smaller will significantly impact yield push board costs above acceptable levels highly competitive cost conscious electronics industry. Avoiding problems such bent leads solder bridging become significant manufacturing challenges. Additionally, electrical problems such crosstalk become major issue length close pitch leads surface mount packages. Alternatively, packaging uses relatively wide "pad pad" pitch rules when coupled with existing manufacturing processes result high yields. "array" approach improves density reduces board space consumed device. Table Figure show examples space savings over surface mount packages.
2001 Fairchild Semiconductor Corporation
AN500543
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AN-5026
Routing
Fairchild Semiconductor products designed around JEDEC standard 0.8mm ball pitch large 0.5mm ball size. This allows economical 0.15mm mil) line space manufacturing processes well optimized reliability. Figure shows 0.15mm mil) line routing techniques.
FIGURE Routing Figure through Figure illustrate basic routing techniques different bit-count devices.
FIGURE 54-Ball 18-Bit Routing (74LCX16500)
FIGURE 54-Ball 24-Bit Routing (FST16211)
FIGURE 96-Ball 32-Bit Routing (74VCX32374) Note: Various techniques routing internal control pins.
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AN-5026
Routing
(Continued)
FIGURE 114-Ball 36-Bit Routing (74VCX32500)
FIGURE 114-Ball 40-Bit Routing (FST32211) Note: FST32211 also routed 43-bit switch without vias.
Routing Power Ground: Power ground balls have been routed illustrations above because designers multiple routing choices. There generally methods: Supplying power ground connecting vias VCC/GND planes traces under package. Figure placement. Pros: Better noise performance lower power inductance (shorter VCC/GND trace length). Cons: size under package restricted 0.56mm (22.0 mil) vias. Supplying power ground connecting vias VCC/GND plains traces outside package. Figure Pros: Allows larger vias outside package. Cons: Compromised noise performance through trace length added VCC/GND trace length.
FIGURE Powered with Vias Under Package
FIGURE Powered with Vias Outside Package Land Area
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AN-5026
Design Layout Options
When using vias high bit-count devices such 48-bit FST32211 (see Figure 10), density placement become critical issues layout designer. through-board vias allows access signal bits device; this helps contribute maximum space integration. Additionally, board backside vias used connect components such termination decoupling devices needed.
FIGURE 114-Ball 48-Bit with Vias (FST32211) Note: free 48-bit switch solution FST16211 used with minimal loss space savings. (see Figure Figure shows ball pads spacing with 0.8mm pitch 0.56mm via, which give 0.11mm ball spacing. Figure shows board cross-section with non-solder mask defined pads-to-via spacing dimensions. Manufacturing technology expense deciding factors size. Larger vias allow more relaxed manufacturing rules lower costs. Smaller vias more costly high manufacturing equipment higher drill breakage.
FIGURE Ball Spacing Diagram
FIGURE Board with Non-Solder Mask Defined Pads Spacing
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AN-5026
Design Layout Options
Through-board vias most economical type from board manufacturing perspective. However, trade-offs highly space-constrained designs required. Through-board vias create matrix vias board backside, limiting traces components. These vias also disrupt smooth layout runs internal board layers limit their placement. With ever increasing demand more compact systems higher density layouts, three more advanced methods connections being used, blind via, buried via, micro via. Figure shows example these types used conjunction with BGA. Blind vias connect side board some inner layers, completely through other side. Buried vias connect internal board layers extend exterior board.
(Continued) Micro vias very small vias (4µm typical) used layouts. This significantly reduce density, increase routing options board, conserve space. Laser technology often used drill micro vias. Lasers drill micro vias through millimeter thick dielectric layer, allowing connection first internal layer board. millimeter layers drilled with laser, allowing connection from surface second board layer. These three types more costly than through-board vias from manufacturing standpoint. However, there significant advantages over through-board vias; elimination backside vias frees that layer component placement, some internal layers backside freed traces uninterrupted runs.
FIGURE Multi Layer Board with Connections Micro Vias, Buried Vias Blind Vias
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AN-5026
Board Design
achieve maximum reliability, design which mounted should considered. particular, diameter package lands board lands very important. actual sizes these dimensions factors, their ratio also critical importance. Figure shows Board Layout with optimum ratio package land land. This optimized ratio equalizes stresses, reducing chances stress cracked solder ball, which will lead premature system failure. Ratios other than will lead unequal distribution stress loads. example, solder lands that larger than package lands will place greater amount stress ball package land ball interface. This cause cracking premature failure package land ball interface.
Mounting Process
Replacing leaded packages with BGA's offers several board assembly advantages: Improved device planarity chance bend leads Greater spacing With chance bend deform leads, products offer manufacturers significant yield improvement over similar lead count fine-pitch surface mount devices. Another important feature products their ability self-align over solder lands. This feature caused surface tension solder balls pulling over pads. solder paste recommended mounting devices, although possible omit paste, only flux. advantages using paste are: Paste acts flux, aids wetting solder ball land. Paste, being sticky, helps hold component place during reflow. Paste helps overcome minor variations planarity solder balls.
FIGURE Board Layout Land diameter package Land diameter printed circuit board Ratio best case reliability practice optimum land diameters follows: Solder Mask defined pads: 0.375mm
Paste contributes final volume solder joint, thus allows this volume varied give optimum joint. No-clean type pastes recommended, difficulty cleaning under mounted component. order produce optimum solder joint, important understand amount collapse solder balls, overall shape joint. These function diameter solder ball vias. volume type solder paste screened onto PCB. diameter land. board assembly re-flow conditions. weight package. shown Figure original ball height package 0.40mm. ball height typically drops 0.35mm after package mounted.
Non-Solder Mask defined pads: 0.350mm Experience shown that solder lands either solder mask defined, non-solder mask defined. However, non-solder mask defined designs provide additional ball-to-land contact area, making them favored option. additional contact area created from solder ball side connection made during soldering process. shown Figure this creates improved mechanical connection.
FIGURE Cross-section Comparison Solder Mask Defined (left) Non-Solder Mask Defined (right) with Solder Ball Connections
FIGURE Solder Ball Collapse
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AN-5026
Testing
During prototype engineering debug phase necessary access signals testing purposes. Several options exist depending specific needs system being developed. Prototype socket fanout solder mask defined lands With form factor boards large arrays remove board real estate advantage gained with packaging. Limited access still gained using test points like those shown Figure
Minimum Size Defined Pattern Prototype Testing ARRAY 0.8mm pitch with package dimensions 16.0mm 5.5mm Overall dimensions (including TestVia's) 20.1mm 8.8mm 22mil vias, 15mil holes; 6mil line space rules
Each methods offers advantages disadvantages. prototype socket gives designer ability test multiple devices socketed connection. fan-out method, shown Figure incorporates mounted routed through array vias signal accessibility.
FIGURE Fan-out Prototype Testing
Solder Mask Defined Land Pattern In-System Testing
FIGURE In-System Testing
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AN-5026 Using Packages
Notebook Docking Application
Routing into hole pattern created typical 0.8mm docking connector achieved single signal layer. limiting signal routing single layer, vias needed BGA. Eliminating datapath vias allows greater levels backside usability backside component placement.
FIGURE Docking Application
Conclusion
FBGA's offer dramatic levels layout design possibilities. BGA's offer space savings more TSSOP greater than over comparable TVSOP QVSOP packaging. understanding effectively these packages, system designers create electronic systems with greater component density, miniaturization functionality. additional benefit system manufacturing with less re-work more reliability. Continued innovations cost reductions manufacturing technology will usher advances design further usability cost effectiveness BGA's. With packages already with leaded packages cost large-scale designs, continued drive toward system size reduction, FBGA's types wave future will soon everywhere.
Fairchild does assume responsibility circuitry described, circuit patent licenses implied Fairchild reserves right time without notice change said circuitry specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL PRESIDENT FAIRCHILD SEMICONDUCTOR CORPORATION. used herein: Life support devices systems devices systems which, intended surgical implant into body, support sustain life, whose failure perform when properly used accordance with instructions provided labeling, reasonably expected result significant injury user. www.fairchildsemi.com critical component component life support device system whose failure perform reasonably expected cause failure life support device system, affect safety effectiveness. www.fairchildsemi.com

AN-5026 Fairchild Semiconductor Application Note January 2001 Rev

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