Electrical Characteristics MM74HC High-Speed CMOS Logic input out

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Electrical Characteristics MM74HC High-Speed CMOS Logic input out

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Electrical Characteristics MM74HC High-Speed CMOS Logic
Electrical Characteristics MM74HC High-Speed CMOS Logic
input output characteristics MM74HC high-speed CMOS logic family were conceived meet several basic goals. These goals provide input current voltage requirements, noise immunity quiescent power dissipation similar CD4000 MM74C metal-gate CMOS logic output current drives similar power Schottky TTL. addition, enable merging HC-CMOS designs, MM74HCT family differs only their input voltage requirements, which same TTL, ease interfacing between logic families. order familiarize user with MM74HC logic family, input output characteristics discussed this application note, well these characteristics affected various parameters such power supply voltage temperature. Also, those users have been designing with metal-gate CMOS logic, notable differences features high-speed CMOS compared those logic families. Buffered CMOS Logic Family MM74HC "buffered" logic family like CD4000B series CMOS. Buffering CMOS logic merely denotes designing that output taken from inverting buffer stage. example, internal circuit implementation NAND gate would simple NAND followed inverting stages. unbuffered gate would implemented single stage. Both shown Figure Most logic devices inherently buffered because they inherently multi-stage circuits. Gates similar small circuits yield greatest improvement performance buffering.
Fairchild Semiconductor Application Note Larry Wakeman April 1998
There several advantages buffering this high-speed CMOS family. using standardized buffer, output characteristics devices more easily made identical. Multi-stage gates will have better noise immunity higher gain caused having several stages from input output. Also, output impedance unbuffered gate change with input logic level voltage input logic combination, whereas buffered outputs unaffected input conditions. Finally, single stage gates implemented MM74HC CMOS would require large transistors large output drive requirements. These large devices would have large input capacitance associated with them. This would affect speed circuits driving into unbuffered gate, especially when driving large fanouts. Buffered gates have small input transistors correspondingly small input capacitance. think that major disadvantage buffered circuits would speed loss. would seem that three stage gate would three times slower than buffered one. However, internal stages much faster than output stage speed lost buffering relatively small. exception buffering MM74HCU04 inverter which unbuffered enable various linear crystal oscillator applications.
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FIGURE Schematic Diagrams Unbuffered Buffered NAND Gate CMOS Input Voltage Characteristics mentioned before, MM74HC standard input levels similar metal-gate CMOS. This enables high-speed logic family enjoy same wide noise margin CD4000 MM74C logic. With these input levels 3.5V minimum logic (VIH) 1.0V logic (VIL). output levels when operated worst case input levels, specified VCC-0.1 0.1V. output levels will actually within millivolts either ground.
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When operated over entire supply voltage range, input logic levels are: 0.7VCC 0.2VCC. Figure illustrates input voltage levels noise margin these circuits over power supply range. shaded area indicates noise margin which difference between input output logic levels. logic noise margin logic noise margin VCC. Also shown comparison 74LS input levels noise margins over their supply range.
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1998 Fairchild Semiconductor Corporation
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These input levels specified individual data sheets 2.0V, 4.5V, 6.0V. 2.0V input levels quite 0.7(VCC) 0.2(VCC) voltages transistor turn thresholds become significant. This shown Figure
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FIGURE Worst Case Input Output Voltages Over Operating Supply Range "HC" "LS" Logic input output logic voltages their behavior with temperature variation determined input output transfer function logic circuit. Figure shows transfer function MM74HC00 NAND gate. seen, NAND gate ground output levels very sharp transition about 2.25V. Thus, good noise immunity achieved, since input noise volt will appear output. transition point also very stable with temperature, drifting typically millivolts over entire temperature range. comparison, transfer function 74LS00 plotted Figure LSTTL output transitions about 1.1V transition region varies several hundred millivolts over temperature range. Also, since transition region closer logic level, less ground noise tolerated input. typical systems, noise capacitively coupled signal lines. amount voltage coupled capacitively induced currents dependent impedance output driving signal line. Thus, lower output impedance lower induced voltage. High-speed CMOS offers improved noise immunity over CD4000 this respect because output impedance tenth that CD4000 about times less susceptible capacitively induced current noise.
FIGURE Input/Output Transfer Characteristics LS00 Nand Gate MM74HCT sub-family MM74HC logic provides compatible input logic voltage levels. This will enable outputs guaranteed correctly drive CMOS inputs. incompatibility results because outputs only guaranteed pull 2.7V logic high level, which high enough guarantee valid CMOS logic high input. design entire family compatible would compromise speed, input noise immunity circuit size. This sub-family used interface sub-systems implemented using logic CMOS sub-systems. input level specifications MM74HCT circuits same LSTTL. Minimum input high level 2.0V maximum level 0.8V using supply. fairly simple alternative interfacing from LSTTL pull-up resistor from output VCC, usually 4-10 This resistor will ensure that will pull VCC. (See Interfacing MM74HC High-Speed CMOS Logic application note.) High-Speed CMOS Input Current Capacitance Both standard "HC" compatible "HCT" circuits maintain ultra input currents inherent CMOS circuits when CMOS levels applied. This current typically less than nanoamp reverse leakages input protection diodes. Input currents small that they usually neglected. Since CMOS inputs present essentially load, their fanout nearly infinite. Each CMOS input some capacitance associated with inputs. This capacitance typically MM74HC, package, input protection diode, transistor gate capacitances. Capacitance information given data sheets measured with pins grounded except test pin. This method used because yields fairly conservative result avoids capacitance meter power supply ground loops decoupling problems. Figure plots typical input capacitance versus input voltage HC-CMOS logic with device powered small peaking 2.2V internal Miller feedback capacitance effects.
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FIGURE Input/Output Transfer Characteristics HC00
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When comparing MM74HC input currents logic, 74LS does need significantly more input current. LSTTL requires current when logic applied high state which significantly more than worst case leakage that MM74HC has.
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FIGURE Typical Quiescent Supply Current Variation with Temperature
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FIGURE Input Capacitance Input Voltage Typical Device MM74HC Power Supply Voltage Quiescent Current Figure compares operating power supply range high-speed CMOS metal-gate CMOS. seen, MM74HC operate power supply voltages from 2-6V. This range narrower than 3-15V range CD4000 MM74C CMOS. narrower range silicon-gate CMOS process employed which been optimized attain high operating frequencies 2-6V range however much wider than 4.5V 5.5V range specified circuits, guaranteeing operation down useful when operating CMOS batteries portable battery backup applications. quiescent power supply current high-speed CMOS family very similar CD4000 MM74C CMOS. When CMOS circuits switching there current path between ground, except leakage currents which typically much less than These diode transistor leakages.
Figure illustrates this leakage increases with temperature plotting typical leakage current versus temperature device. result this temperature dependence, there standardized specifications which specify higher current elevated temperatures. summary these specifications shown Table
TABLE Standardized Specifications MM74HC Logic 25°C, 85°C 125°C 6.0V Temperature 25°C 85°C 125°C Gates Flip-Flops
Output Characteristics prime advantages MM74HC over metal-gate CMOS (besides speed) output drive current, which about times CD4000 MM74C logic. larger output current enables high-speed CMOS directly drive large fanouts 74LS devices, also enables HC-CMOS more easily drive large capacitive loads. This improvement output drive variety enhancements provided silicon-gate process used. basic current equation MOSFET Where transistor gate voltage, transistor threshold voltage, transistor drain voltage which equivalent circuit output voltage. This CMOS process, when compared metal-gate CMOS, increased transistor gains, Beta, lower threshold voltages, Also, improved photolithography reduced transistor lengths, wider transistors also possible because tighter geometries.
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FIGURE Comparison Supply Range "HC", "LS" Metal-Gate
Figure compares output high current specifications MM74HC, 74LS metal-gate CMOS standard device outputs. High-speed CMOS worst case output current which similar power Schottky circuits, offers symmetrical logic high currents well. addition, CMOS circuits whose functions
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make them ideal driving large capacitive loads have larger output current example, these driver outputs used octal flip-flops, latches, buffers, bidirectional circuits.
using 85°C data sheet number would about VOUT 0.26V, this what specified device data sheets.
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FIGURE Typical Output Source
FIGURE Comparison 74HC, 74LS CD4000/ Output Drive Currents,
Table summarizes various output current specifications MM74HC CMOS along with their equivalent LSTTL fanouts. Table shows, output currents MM74HC devices derated from MM74HC devices. derating caused decrease current drive output transistors temperature increased. show this, Figures plots typical output source sink currents against temperature both standard driver circuits. This variation similar that found metal-gate CMOS, same -0.3% derating that used approximate temperature derating CD4000 MM74C applied 74HC. example, approximate worst case 25°C current drive would expect
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FIGURE Typical Output Sink Current Temperature Standard Outputs TABLE Data Sheet Output Current Specifications MM74HC Logic Device 4.5V Standard 74HC 74HC Output High Current (VOUT 3.94) (VOUT 3.94) Output Current (VOUT 0.33V) (VOUT 0.33V) LSTTL Fanout
data sheet specifications output current measured only output voltage either source sink current each three temperature ranges, room, commercial, military. outputs supply much larger currents larger output voltages allowed. This shown Figures which plot output current versus output voltage both N-channel sink current P-channel source current. Both standard driver outputs shown. example, standard output would typically sink with typically capable short circuit current
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largest power supply voltage that should applied device larger voltages applied, transistors will breakdown, "punch through". smallest voltage that should applied MM74HC circuit -0.5V. more negative voltages applied, substrate diode would become forward biased. both cases large currents could flow, damaging device.
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FIGURE Typical P-Channel Output Source Current Output Voltage Standard Outputs
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FIGURE Typical N-Channel Output Sink Current Output Voltage Standard Outputs
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FIGURE Typical P-Channel Output Source Current Output Voltage Outputs output current voltage characteristics logic circuit determine well that circuit will switch output when driving capacitive loads transmission lines. more current available, faster load switched. order HC-CMOS achieve LSTTL performance, outputs should have characteristics similar LSTTL. This similarity illustrated Figure plotted typical LSTTL HC-CMOS output characteristics together. supply voltage decreased, output currents will decrease. Figure plots output sink current versus power supply voltage with 0.4V output voltage, Figure plots output source current against power supply with output voltage VCC-0.8V. interesting note that MM74HC powered typically, will still drive LSTTL inputs 25°C). Absolute Maximum Ratings Absolute maximum ratings guidelines that define limits operation MM74HC logic devices. exceed these ratings could cause device malfunction permanently damage itself. These limits tabulated Table III, their reasons existing discussed below.
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FIGURE Typical N-Channel Output Sink Current Output Voltage Outputs
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FIGURE Comparison Standard LSTTL HC-CMOS Output Source Currents
FIGURE Output Source Current Variation with Power Supply High-speed CMOS inputs should have voltages applied them that exceed below ground more than 1.5V. would forward bias input protection diodes excessive currents which damage them. actuality diodes specified withstand current. Thus input voltage exceed 1.5V designer limits input current less than output voltages should restricted less than -0.5V greater than VCC+0.5V, current must limited same limitations input diodes apply outputs well. This includes both standard 3-STATE outputs. These current restrictions. normal high speed systems, line ringing power supply spiking unavoidably cause inputs outputs glitch above these limits. This will damage these diodes internal circuitry. diodes have been specifically designed withstand momentary transient currents that would normally occur high speed systems. Additionally, there maximum rating output supply currents shown Table This restriction dictated current capability integrated circuit metal traces. Again this specification expected that during switching transients output supply currents could exceed these specifications several times these numbers. most CD4000 MM74C CMOS operating designer does need worry about excessive output currents, since output transistors usually cannot source sink enough current stress metal dissipate excessive amounts power. high-speed CMOS devices have much improved output characteristics, care should exercised ensure that they draw excessive currents long durations, i.e., greater than seconds. also important ensure that internal dissipation circuit does exceed package power dissipation. This will usually only occur when driving large currents into small resistive loads.
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FIGURE Comparison Standard LSTTL HC-CMOS Output Sink Currents
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FIGURE Output Sink Current Variation with Power Supply
TABLE Absolute Maximum Ratings MM74HC CMOS Logic Symbol VOUT IOUT Input Voltage Output Voltage Standard Current, Output Driver Parameter Supply Voltage Value -0.5 -1.5 VCC+1.5 -0.5 VCC+0.5 Unit
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TABLE Absolute Maximum Ratings MM74HC CMOS Logic (Continued) Symbol IIK, Parameter Standard Ground Current Input Output Diode Current Driver Value Unit
MM74HC Input Protection with circuits designed with transistors "HC" logic must protected against damage excessive electrostatic discharges, which sometimes occur during handling assembly procedures. protection were provided, large static voltages appearing across pins could cause damage. However, input protection which takes full advantage "HC" silicon-gate process been carefully designed reduce susceptibility these high-speed CMOS circuits oxide rupture large static voltages. conjunction with input protection, output parasitic diodes also protect circuit from large static voltages occuring between input, output, supply pin.
prevent large voltages from appearing across transistor. These diodes larger than those used metal-gate CMOS enable greater current shunting make them less susceptible damage. input network ringed ground diffusions, which prevent substrate currents caused these transients from affecting other circuitry. parasitic output diodes (Figure that isolate output transistor drains from substrate also important preventing damage. They clamp large voltages that appear across output pins. These diodes also ringed ground diffusions again shunt substrate currents, preventing damage other parts circuit. Summary MM74HC, because many process enhancements, does provide combination features from 74LS metal-gate CMOS logic families. High-speed CMOS gives designer increased flexibility power supply range over LSTTL, much larger output drive than CMOS previously had, wider noise immunity than 74LS, CMOS power consumption.
Figure shows schematic input protection network employed. network consists three elements: poly-silicon resistor, diode connected VCC, distributed diode-resistor connected ground. This high-speed process utilizes poly resistor more effectively isolate input diodes than diode-resistor used metal-gate CMOS. This resistor will slow down incoming transients dissipate some their energy. Connected resistor diodes which clamp input spike
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FIGURE Schematic Diagram Input Output Protection Structures
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Electrical Characteristics MM74HC High-Speed CMOS Logic
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Electrical Characteristics MM74HC High-Speed CMOS Logic input out

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