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DC Electrical Characteristics of MM74HC High-Speed CMOS Logic

Fairchild Semiconductor Application Note 313 Larry Wakeman April 1998

DC Electrical Characteristics of MM74HC High-Speed CMOS Logic
The input and output characteristics of the MM74HC high-speed CMOS logic family were conceived to meet several basic goals. These goals are to provide input current and voltage requirements, noise immunity and quiescent power dissipation similar to CD4000 and MM74C metal-gate CMOS logic and output current drives similar to low power Schottky TTL. In addition, to enable merging of TTL and HC-CMOS designs, the MM74HCT sub family differs only in their input voltage requirements, which are the same as TTL, to ease interfacing between logic families. In order to familiarize the user with the MM74HC logic family, its input and output characteristics are discussed in this application note, as well as how these characteristics are affected by various parameters such as power supply voltage and temperature. Also, for those users who have been designing with metal-gate CMOS and TTL logic, notable differences and features of high-speed CMOS are compared to those logic families. A Buffered CMOS Logic Family The MM74HC is a "buffered" logic family like the CD4000B series CMOS. Buffering CMOS logic merely denotes designing the IC so that the output is taken from an inverting buffer stage. For example, the internal circuit implementation of a NAND gate would be a simple NAND followed by two inverting stages. An unbuffered gate would be implemented as a single stage. Both are shown in Figure 1. Most MSI logic devices are inherently buffered because they are inherently multi-stage circuits. Gates and similar small circuits yield the greatest improvement in performance by buffering.
Fairchild Semiconductor Application Note 313 Larry Wakeman April 1998
There are several advantages to buffering this high-speed CMOS family. By using a standardized buffer, the output characteristics for all devices are more easily made identical. Multi-stage gates will have better noise immunity due to the higher gain caused by having several stages from input to output. Also, the output impedance of an unbuffered gate may change with input logic level voltage and input logic combination, whereas buffered outputs are unaffected by input conditions. Finally, single stage gates implemented in MM74HC CMOS would require large transistors due to the large output drive requirements. These large devices would have a large input capacitance associated with them. This would affect the speed of circuits driving into an unbuffered gate, especially when driving large fanouts. Buffered gates have small input transistors and correspondingly small input capacitance. One may think that a major disadvantage of buffered circuits would be speed loss. It would seem that a two or three stage gate would be two to three times slower than a buffered one. However, internal stages are much faster than the output stage and the speed lost by buffering is relatively small. The one exception to buffering is the MM74HCU04 hex inverter which is unbuffered to enable its use in various linear and crystal oscillator applications.
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FIGURE 2. Worst Case Input and Output Voltages Over Operating Supply Range for "HC" and "LS" Logic The input and output logic voltages and their behavior with temperature variation is determined by the input to output transfer function of the logic circuit. Figure 3 shows the transfer function of the MM74HC00 NAND gate. As can be seen, the NAND gate has VCC and ground output levels and a very sharp transition at about 2.25V. Thus, good noise immunity is achieved, since input noise of a volt or two will not appear on the output. The transition point is also very stable with temperature, drifting typically 50 or so millivolts over the entire temperature range. As a comparison, the transfer function for a 74LS00 is plotted in Figure 4. LSTTL output transitions at about 1.1V and the transition region varies several hundred millivolts over the temperature range. Also, since the transition region is closer to the low logic level, less ground noise can be tolerated on the input. In typical systems, noise can be capacitively coupled to the signal lines. The amount of voltage coupled by capacitively induced currents is dependent on the impedance of the output driving the signal line. Thus, the lower the output impedance the lower the induced voltage. High-speed CMOS offers improved noise immunity over CD4000 in this respect because its output impedance is one tenth that of CD4000 and so it is about 7 times less susceptible to capacitively induced current noise.
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(a) FIGURE 3. Input / Output Transfer Characteristics for (a) HC00
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When comparing MM74HC input currents to TTL logic, 74LS does need significantly more input current. LSTTL requires 400 µA of current when a logic low is applied and 40 µA in the high state which is significantly more than the worst case 1 µA leakage that MM74HC has.
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FIGURE 7. Typical Quiescent Supply Current Variation with Temperature
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Figure 7 illustrates how this leakage increases with temperature by plotting typical leakage current versus temperature for an MSI and SSI device. As a result of this temperature dependence, there is a set of standardized ICC specifications which specify higher current at elevated temperatures. A summary of these specifications are shown in Table 1.
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FIGURE 6. Comparison of Supply Range for "HC", "LS" and Metal-Gate
Figure 8 compares the output high and low current specifications of MM74HC, 74LS and metal-gate CMOS for standard device outputs. High-speed CMOS has worst case output low current of 4 mA which is similar to low power Schottky TTL circuits, and offers symmetrical logic high and low currents as well. In addition, CMOS circuits whose functions
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make them ideal for use driving large capacitive loads have a larger output current of 6 mA. For example, these bus driver outputs are used on the octal flip-flops, latches, buffers, and bidirectional circuits.
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(a) FIGURE 9. Typical Output (a) Source
FIGURE 8. Comparison of 74HC, 74LS and CD4000 / 74C Output Drive Currents, IOH and IOL
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The largest power supply voltage that should be applied to a device is 7V. If larger voltages are applied, the transistors will breakdown, or "punch through". The smallest voltage that should be applied to a MM74HC circuit is -0.5V. If more negative voltages are applied, a substrate diode would become forward biased. In both cases large currents could flow, damaging the device.
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(a) FIGURE 11. Typical P-Channel Output Source Current vs. Output Voltage for (a) Standard Outputs
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(a) FIGURE 13. Typical N-Channel Output Sink Current vs. Output Voltage for (a) Standard Outputs
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(b) FIGURE 14. Typical N-Channel Output Sink Current vs. Output Voltage for (b) Bus Outputs
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(a) FIGURE 15. Comparison of Standard LSTTL and HC-CMOS Output (a) Source Currents
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(b) FIGURE 16. Comparison of Standard LSTTL and HC-CMOS Output Sink Currents
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(a) FIGURE 17. Output (a) Sink Current Variation with Power Supply
TABLE 3. Absolute Maximum Ratings for MM74HC CMOS Logic Symbol VCC VIN VOUT IOUT DC Input Voltage DC Output Voltage Standard DC Current, Per Output Pin Bus Driver Parameter DC Supply Voltage Value -0.5 to 7.0 -1.5 to VCC+1.5 -0.5 to VCC+0.5 Unit V V V mA mA
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TABLE 3. Absolute Maximum Ratings for MM74HC CMOS Logic (Continued) Symbol ICC IIK, IOK Parameter Standard DC VCC or Ground Current Input or Output Diode Current Bus Driver Value Unit mA mA mA
MM74HC Input Protection As with any circuits designed with MOS transistors "HC" logic must be protected against damage due to excessive electrostatic discharges, which can sometimes occur during handling and assembly procedures. If no protection were provided, large static voltages appearing across any two pins of a MOS IC could cause damage. However, the new input protection which takes full advantage of the "HC" silicon-gate process has been carefully designed to reduce the susceptibility of these high-speed CMOS circuits to oxide rupture due to large static voltages. In conjunction with the input protection, the output parasitic diodes also protect the circuit from large static voltages occuring between any input, output, or supply pin.
prevent large voltages from appearing across the transistor. These diodes are larger than those used in metal-gate CMOS to enable greater current shunting and make them less susceptible to damage. The input network is ringed by VCC and ground diffusions, which prevent substrate currents caused by these transients from affecting other circuitry. The parasitic output diodes (Figure 19) that isolate the output transistor drains from the substrate are also important in preventing damage. They clamp large voltages that appear across the output pins. These diodes are also ringed by VCC and ground diffusions to again shunt substrate currents, preventing damage to other parts of the circuit. Summary The MM74HC, because of many process enhancements, does provide a combination of features from 74LS and metal-gate CMOS logic families. High-speed CMOS gives the designer increased flexibility in power supply range over LSTTL, much larger output drive than CMOS has previously had, wider noise immunity than 74LS, and low CMOS power consumption.
Figure 19 shows a schematic of the input protection network employed. The network consists of three elements: a poly-silicon resistor, a diode connected to VCC, and a distributed diode-resistor connected to ground. This high-speed process utilizes the poly resistor to more effectively isolate the input diodes than the diode-resistor used in metal-gate CMOS. This resistor will slow down incoming transients and dissipate some of their energy. Connected to the resistor are the two diodes which clamp the input spike and
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FIGURE 19. Schematic Diagram of Input and Output Protection Structures
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DC Electrical Characteristics of MM74HC High-Speed CMOS Logic
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.