Buffered 4Mx72 DRAM MODULE based 4Mx4 DRAM, with ECC, 4K-Refresh

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Buffered 4Mx72 DRAM MODULE based 4Mx4 DRAM, with ECC, 4K-Refresh

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HYM572A404C N-Series
Buffered 4Mx72 DRAM MODULE based 4Mx4 DRAM, with ECC, 4K-Refresh
HYM572A404C N-Series 4Mx72-bit Extended Data mode CMOS DRAM module consisting eighteen HY5116404C 24/26 TSOP-II 16-bit BiCMOS line driver TSSOP glass-epoxy printed circuit board. 0.1µF 0.01µF decoupling capacitors mounted each DRAM. HYM572A404CNG/CTNG Gold plated socket type Dual In-line Memory Module suitable easy interchange addition byte memory.
FEATURES
168-Pin Buffered DIMM Extended Data Operation /CAS-before-/RAS, /RAS-only, Hidden Self refresh capability 4096 refresh cycles 256ms (SL-part) 4096 refresh cycles 64ms Fast access time cycle time
Speed tRAC 50ns 60ns 70ns tCAC 13ns 15ns 18ns tHPC 20ns 25ns 30ns
Single power supply 5.0V power dissipation Max. self-refresh 51.7mW (SL-part) Max. battery back-up 71.5mW (SL-part) Max. CMOS standby 51.7mW (SL-part) 121mW Max. standby 220mW Max. operating
Speed Power 11.2W 9.26W 8.27W
compatible inputs outputs JEDEC standard pinout Buffered inputs (except /RAS Byte interleave enabled, Dual address inputs (A0,B0)
ORDERING INFORMATION
PART NUMBER HYM572A404CNG HYM572A404CTNG SPEED 50/60/70 50/60/70 FEATURES EDO, EDO, TSOP PACKAGE DIMM DIMM PLATING Gold Gold
This document general product description subject change without notice. Hyundai Electronics does assume responsibility circuits described. patent licenses implied. Rev.01 Dec.97 ©1997 Hyundai Semiconductor
HYM572A404C N-Series
CONNECTION
DISCRIPTION
/RAS0, /RAS2 /CAS0, /CAS4 /WE0, /WE2 /OE0, /OE2 A0-A11, DQ0~DQ71 PD1~PD8 /PDE ID0, Address Strobe Column Address Strobe Write Enable Output Enable Address Input Data Input Output Presence Detect Presence Detect Enable Power (+5V) Ground
Rev.01 Dec.97
HYM572A404C N-Series
ASSIGNMENTS
NAME DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 /WE0 /CAS0 /RAS0 /OE0 NAME /OE2 /RAS2 /CAS4 /WE2 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 NAME DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 NAME /PDE DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQ64 DQ65 DQ66 DQ67 DQ68 DQ69 DQ70 DQ71
Rev.01 Dec.97
HYM572A404C N-Series
PRESENCE DETECT PINS
Speed NOTE either open driven on-board buffer circuits. connected directly without buffer. will either open Self-Refresh driven Normal.
Rev.01 Dec.97
HYM572A404C N-Series
BLOCK DIAGRAM
NOTE resistors
Rev.01 Dec.97
HYM572A404C N-Series
ABSOLUTE MAXIMUM RATINGS
SYMBOL TSTG VIN, VOUT PARAMETER Ambient Temperature Storage Temperature Voltage relative Voltage relative Short Circuit Output Current Power Dissipation RATING -1.0 -1.0 19.7 UNIT
NOTE Operation above Absolute Maximum Ratings adversely affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(TA=0°C 70°C) SYMBOL PARAMETER Power Supply Voltage Input High Voltage Input Voltage MIN. -1.0 TYP. MAX. VCC+1.0 UNIT
NOTE voltages referenced VSS.
Rev.01 Dec.97
HYM572A404C N-Series
CHARACTERISTICS
(TA=0°C 70°C, VCC=5.0V VSS=0V, unless otherwise noted.) Speed/ Power Max. Current 2040 1680 1500 2040 1680 1500 1680 1500 1320 2040 1680 1500
Symbol
ICC1
Parameter
Operating Current Standby Current /RAS-only Refresh Current Mode Current CMOS Standby Current /CAS-before/RAS Refresh Current Battery Back-up Current (SL-part)
Test Condition
/RAS /CAS cycling tRC=tRC (min.)
UNIT
ICC2 ICC3
/RAS /CAS other inputs /CAS VIH, /RAS cycling (min.) /RAS VIL, /CAS, Address cycling tHPC tHPC (min.) /RAS /CAS VCC-0.2V
ICC4
SL-part
ICC5 ICC6
/RAS /CAS cycling tRC=tRC (min.)
tRAS 300ns tRAS
ICC7
ICC8
Self Refresh Current (SL-part) Parameter
62.5µs /CAS cycling 0.2V 0.2V Address VCC-0.2V 0.2V VCC-0.2V, 0.2V open /RAS /CAS 0.2V Other pins same ICC7 Test condition other pins under test VOUT /RAS /CAS 4.2mA -5.0mA
Symbol
Min. /RAS /RAS
Max.
UNIT
Input Leakage current (Any Input) Output Leakage current (Any Input) Output Voltage Output High Voltage
NOTE
ICC1, ICC3, ICC4 ICC6 depend output loading cycle rates(tRC tHPC). Specified values obtained with outputs unloaded. specified average current. ICC1, ICC3, ICC6, address changed only once while /RAS=VIL. ICC4, address changed maximum once while /CAS=VIH within mode cycle time tHPC. Only /RAS(max.) applied refresh battery backup tRAS(max.) 10µs applied normal functional operation. ICC5(max.) 9.4mA, ICC7 ICC8 applied SL-part only.
Rev.01 Dec.97
HYM572A404C N-Series
CHARACTERISTICS
(TA=0°C 70°C, VCC=5.0V VSS=0V, unless otherwise noted.) HYM572A404C N-Series SYMBOL PARAMETER MIN. tRWC tHPC tHPRWC tRAC tCAC tCPA tCLZ tCEZ tRAS tRASP tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tRWL tCWL Random Read Write Cycle Time Read-Modify-Write Cycle Time Mode Cycle Time Mode Read-Modify-Write Cycle Time Access Time from /RAS Access Time from /CAS Access Time from Column Address Access Time from Column Precharge /CAS Output Impedance Buffer Turn-Off Delay Time from /CAS Transition Time (Rise Fall) /RAS Precharge Time /RAS Pulse Width /RAS Pulse Width (EDO Mode) /RAS Hold Time /CAS Hold Time /CAS Pulse Width /RAS /CAS Delay Time /RAS Column Address Delay Time /CAS /RAS Precharge Time /CAS Precharge Time Address Set-up Time Address Hold Time Column Address Set-up Time Column Address Hold Time Column Address /RAS Lead Time Read Command Set-up Time Read Command Hold Time Referenced /CAS Read Command Hold Time Referenced /RAS Write Command Hold Time Write Command Pulse Width Write Command /RAS Lead Time Write Command /CAS Lead Time UNIT NOTE MAX. MIN. MAX. MIN. MAX. 200K 200K 200K 9,13 6,13 7,13 11,13 2,13 5,6,7 5,6,13 5,7,13 5,13 5,13 8,13
Rev.01 Dec.97
HYM572A404C N-Series
CHARACTERISTICS
(Continued) HYM572A404C N-Series SYMBOL PARAMETER UNIT NOTE MIN. MAX. MIN. MAX. MIN. MAX. tREF tWCS tCWD tRWD tAWD tCSR tCHR tRPC tCPT tROH tOEA tOED tOEZ tOEH tCPWD tRHCP tWRP tWRH tRASS tRPS tCHS tDOH tREZ tWEZ tWED tOEP tWPE tOCH tCHO Data-In Set-up Time Data-In Hold Time Refresh Period (4096 cycles) Refresh Period (SL-part) Write Command Set-up Time /CAS Delay Time /RAS Delay Time Column Address Delay Time /CAS Set-up Time (CBR Cycle) /CAS Hold Time (CBR Cycle) /RAS /CAS Precharge Time /CAS Precharge Time (CBR Counter Test) /RAS Hold Time Reference Access Time Data Delay Time Output Buffer Turn Delay Time from Command Hold Time Delay Time from /CAS Precharge /RAS Hold Time from /CAS Precharge /RAS Precharge Time(CBR cycle) /RAS Hold Time (CBR cycle) /RAS Pulse Width (Self Refresh) /RAS Precharge Time (Self Refresh) /CAS Hold Time (Self Refresh) Output Data Hold Time Output Buffer Turn Delay from /RAS Output Buffer Turn Delay from Data Delay Time Precharge Time Pulse Width (EDO cycle) /CAS Hold Time /CAS Hold Time 8,13 11,13 10,13 10,13
Rev.01 Dec.97
HYM572A404C N-Series
NOTE initial pause 200µs required after power-up followed /RAS only refresh cycles before proper device operation achieved. case using internal refresh counter, minimum refresh cycles instead /RAS only refresh cycles required. tASC tCP(min.), assume tT=2ns VIH(min.) VIL(max.) reference levels measuring timing input signals. Transition times measured between VIH(min.) VIL(max.) minimum specifications used only indicate cycle time which proper operation over full temperature range 70°C) assured. Measured VOH=2.0V VOL=0.8V with load equivalent loads 100pF. Operation within tRCD(max.) limit insures that tRAC(max.) met. tRCD(max.) specified reference point only. tRCD greater than specified tRCD(max.) limit, then access time controlled tCAC Operation within tRCD(max.) limit insures that tRAC(max.) met. tRAD(max.) specified reference point only. tRAD greater than specified tRAD(max.) limit, then access time controlled tCEZ(max.), tOEZ(max.), tREZ(max.) tWEZ(max.) define time which output achieves open circuit condition referred output voltage levels. Either tRCH tRRH must satisfied read cycle. These parameters referred /CAS leading edge early write cycles leading edge Read-ModifyWrite cycles. tWCS, tRWD, tCWD, tAWD tCPWD restrictive operating parameters. They included data sheet electrical characteristics only. tWCS tWCS(min.), cycle early write cycle data will remain open circuit (high impedance) through entire cycle. tCWD tCWD(min.), tRWD tRWD(min.) tCPWD tCPWD(min.), then cycle Read-Modify-Write cycle data will contain data read from selected cell. neither above conditions satisfied, condition data indeterminate. /RAS goes high before /CAS high going, open circuit condition output achieved /CAS high going. /CAS goes high before /RAS high going, open circuit condition output achieved /RAS high going. timing skew from DRAM DIMM resulted from addition buffers.
CAPACITANCE
(TA=25°C, VCC=5.0V 10%, VSS=0V 1MHz, unless otherwise noted.) SYMBOL CIN1 CIN2 CIN3 PARAMETER Input Capacitance (A0~A11, Input Capacitance (/RAS0, /RAS2) Input Capacitance (/CAS0, /CAS4, /WE0, /WE2, /OE0, /OE2) Data Input /Output Capacitance (DQ0~DQ71) TYP. MAX. UNIT
Rev.01 Dec.97
HYM572A404C N-Series
PACKAGE INFORMATION
Buffered Dual In-line Memory Module (SOJ/TSOP-II Mounted)
Rev.01 Dec.97

Buffered 4Mx72 DRAM MODULE based 4Mx4 DRAM, with ECC, 4K-Refresh

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