AN-1023 Fairchild Semiconductor Application Note November 1995 Re

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AN-1023 Fairchild Semiconductor Application Note November 1995 Re

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AN-1023 Structural System Test IEEE Std. 1149.1 with Hierarchical Multidrop Addressable JTAG Port, SCANPSC110F
AN-1023
Fairchild Semiconductor Application Note November 1995 Revised 2001
Structural System Test IEEE Std. 1149.1 with Hierarchical Multidrop Addressable JTAG Port, SCANPSC110F
Introduction
IEEE Std. 1149.1 (JTAG) defines standard Test Access Port (TAP) protocol commands built test both chip board level. board designed with boundary scan components typically consists scan chain which daisy-chain Test Data Output (TDO) Test Data Input (TDI) components board. While single scan chain solution might adequate testing board production single-board system, adequate when multi-board system requires interconnects between boards tested after system integration. number methods available accessing system level boundary scan nets. Traditional methods included using multi-channel tester physically access each board, using single tester connection with each board's traces daisy chained together multiplexing Test Mode Select (TMS) pins running each board. alternative approach implement addressable test access controller such SCANPSC110F. SCANPSC110F eliminates shortcomings traditional methods while also providing capability partition single board level scan chain into smaller chains. While possible separate cables each board during production test, becomes unwieldy quickly number boards increase. Furthermore, multiple port solution practical with embedded test. Even though daisy chaining multiple boards together simple, several drawbacks exist. example, Automatic Test Program Generation (ATPG) software multipleboard system views system were board. system scales upward, number NETS become large will number length serial test vectors required. When board missing empty backplane, fault occurs boundary scan infrastructure boards, entire system becomes untestable. multiplexed scheme works well partitioning system giving board test access through single test port. But, does scale well backplane, there provision backplane interconnect testing. Backplane interconnect testing required ability park board Pause-DR/IR states (See Figure Applications Note AN-890) while accessing another board. also requires means performing system wide updates scan commands data. SCANPSC110F solution provides simple means tying independent scan chains from multi-board systems together selectively accessing them. six-bit addressing scheme allows bridges single backplane. Test vectors generated testing individual boards used testing boards after system integration well embedded test field. partitioning achieved using SCANPSC110F will automatically isolate faults down board level with diagnostics. multiple local scan ports (LSP) allow additional partitioning scan chains within board. Backplane interconnect testing enabled through PARKPAUSE command broadcast addressing feature. ATPG software easily implemented available through multiple venders.
FIGURE Single Board Boundary Scan Implementation
2001 Fairchild Semiconductor Corporation
AN012144
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Introduction
(Continued)
FIGURE SCANPSC110F Multidrop Configuration
SCANPSC110F Application Example
more information this application example, refer AN-1037 "Embedded IEEE 1149.1 Test Application Example." Consider system with multidrop backplane. general there slots. Some slots populated with cards, others empty. There many different card types that used with this backplane, there multiple cards same type used within this backplane given configuration. backplane architecture this example simple. Each slots receive same multidrop backplane signals. There active components backplane. However, there passive pull-up resistors hold backplane signals high when 3-stated. system test bus, (TDOBP, TDIBP, TMSBP, TCKBP, TRSTBP* (Asynchronous active input)), also connected each slot multidrop configuration. Each card SCANPSC110F connected system test bus, boundary scan interface (IEEE 1149.1 compliant drivers, latches, transceivers such SCAN18540T, SCAN18373T, SCAN182245T) connected system backplane.
Verification Determination Backplane Configuration
This test sweeps entire address range SCANPSC110F reads captured value from instruction register selected SCANPSC110F. SCANPSC110F instruction register will capture value "XXXXXX01", where "XXXXXX" represents assigned address slot inputs. value scanned back matches outgoing address, SCANPSC110F been selected. scanned back value "11111111" would indicate that there SCANPSC110F outgoing address, such case empty slot. These results used ways: exact system configuration known test time, which often case production, results address range sweep compared known configuration. SCANPSC110F found address where there should have been one, SCANPSC110F found address where there should have been one, tester will report failure. system configuration unknown test time, results from address range sweep compared database containing possible boards determine what board types present current configuration system. Later when interconnect testing cards backplane performed, this predetermined configuration used select proper tests specific configuration.
System Wide Infrastructure Test
Infrastructure testing always first test that must performed. system level, infrastructure test consists verification determination backplane configuration then testing connectivity, identity functionality components that make output scan chains which interface with SCANPSC110F LSP's.
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AN-1023
Local SCAN Port Instruction Test
After system configuration verified determined, test circuitry each card must tested. This done addressing each SCANPSC110F unparking each LSP's, scanning back value captured Instruction Registers each component local chains. captured value "01" least significant bits represents functioning boundary scan component. some cases remaining bits Instruction Register capture used encode pseudo code (e.g., components like Fairchild's SCAN18XXXT, SCAN18XXXA), used test correct component placement. Optionally, device identification register checked each boundary scan component cards check correct component placement. 18-bit SCAN Test Access Logic SCAN18XXXA family includes optional register, some earlier boundary scan components were equipped with register.
used testing board without SCANPSC110F with exception: data SCANPSC110F Instruction Register, Bypass data register, bits, must added serial vectors. remaining steps board test are: Scan SAMPLE/PRELOAD command into target devices BYPASS command SCANPSC110F. Scan first test vector into boundary registers target devices. Scan EXTEST command into target devices BYPASS command SCANPSC110F. Scan next vector into target devices; captured results from previous vector shifted this vector shifted This step repeated until test vectors this board have been exercised. Scan GOTOWAIT command into SCANPSC110F instruction registers return SCANPSC110F Wait-For-Address state where next card addressed.
Board Level Interconnect Testing SCANPSC110F
individual boards cards have already been tested during production. Re-testing after system integration optional, makes good check. case embedded test that will used power self test periodic field testing, running go/no-go board level tests will enable built-in diagnostics down board level. SCANPSC110F Selection Configuration Select SCANPSC110F scanning address into SCANPSC110F Instruction Register. Configure Mode Register appropriate local serial port network configuration board test. board only scan chain connected LSP1, default configuration will appropriate. there multiple chains connected multiple LSPs board with interconnects running between components different chains, appropriate unpark multiple LSPs form what looks like larger chain. network configuration performed Scanning MODESEL command into selected SCANPSC110F's Instruction Register. Scanning appropriate value into Mode register selected SCANPSC110F. Unpark scanning UNPARK command into instruction register selected SCANPSC110F. Once SCANPSC110F selected LSPs unparked, connection made between tester target scan chains. remainder board test consists same commands test data that would
Backplane Interconnect Testing
Testing backplane similar testing NETS within board with exception. nodes backplane NETS terminate components that connected different SCANPSC110F. (See Figure example order test lines multidrop backplane, say, with cards, each card connected test SCANPSC110F. SCANPSC110F provides address information. SCANPSC110F's LSPs (local scan ports) connected backplane driver, such Fairchild's SCAN Test Access Logic, SCAN182245A. These drivers, turn, connected backplane itself, thereby provide scan test operations backplane interconnect testing. Boundary scan ATPG software generates patterns with assumption that output cells components connected will updated simultaneously. This assumption allows node drive during pattern another node drive same during pattern update happen simultaneously nodes, there could significant periods contention between multiple outputs NET. Therefore, Update-IR EXTEST command Update-DRs between patterns vectors (while EXTEST active command) must performed simultaneously boards using broadcast address order select SCANPSC110Fs backplane. general, shifting operations must done addressing SCANPSC110F time.
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AN-1023
Backplane Interconnect Testing
(Continued)
FIGURE Backplane Interconnect Test Flow
SCANPSC110F local scan ports. port connected backplane drivers. other partition resident board.
FIGURE Testing Backplane Interconnects
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AN-1023
detailed description flow backplane interconnect test follows. Reset SCANPSC110F: This performed forcing TRST clocking TCKBP five times while holding TMSBP high. Configure/Preload: Preload boundary scan registers components connected backplane signals each card with first test pattern, shift EXTEST command into Instruction Registers components that interface with backplane signals. Select SCANPSC110F scanning address into SCANPSC110F Instruction Register. Configure Mode Register unpark that interfaces backplane logic. This necessary LSP1 used (default configuration). Unpark scanning UNPARK command into Instruction Register selected SCANPSC110F. Scan SAMPLE/PRELOAD command into target devices PARKPAUSE command SCANPSC110F. Scan first test vector into boundary registers target devices. state sequence should from Shift-DR Exit1-DR through Pause-DR state, after shifting test vector, avoid parking Pause-DR state (see PARKPAUSE command SCANPSC110F data sheet). Shift EXTEST command into target devices GOTOWAIT command SCANPSC110F. state sequence should from Shift-IR Exit1-IR Update-IR, after shifting commands, that active will parked Pause-IR state. Repeat each board involved with backplane test. Execute EXTEST Command: EXTEST command updated backplane components simultaneously avoid significant periods contention that would result from executing EXTEST command board time. Select SCANPSC110F scanning broadcast address into SCANPSC110F Instruction Registers. Scan UNPARK command into Instruction Register selected SCANPSC110F. will actually unparked until backplane sequenced back into Pause-IR state, while UNPARK command active. Scan PARKPAUSE command into SCANPSC110F instruction register. state sequence should from Shift-IR Exit1-IR through Pause-IR state, after shifting PARKPAUSE command. will unpark upon entering Pause-IR state. EXTEST command previously been shifted into Instruction Registers target devices will become active instruction once unparked sequenced through Update-IR state. Capture logic values inputs target devices park Pause-DR state sequencing backplane TAP's through CaptureDR Exit1-DR Update-DR.
Scan GOTOWAIT command SCANPSC110F Instruction Registers.
into
Shift Test Data: Test results from previous pattern shifted while next pattern shifted into boundary registers components each board system. After data shifted, parked Pause-DR state that boundary register contains data, updated value output cell. Select SCANPSC110F scanning address into SCANPSC110F Instruction Register. Scan PARKPAUSE command into Instruction Register selected SCANPSC110F. (The PARKPAUSE command used unpark well park LSP). Sequence backplane TAPs into Pause-DR state order unpark LSP. From Pause-DR state, transition Exit2-DR Shift-IR, where next test vector shifted into target devices, then Exit1-DR Update-DR. will reparked PAUSE-DR state when transitioning from Exit1-DR Update-DR, because PARKPAUSE command still active. Scan GOTOWAIT command SCANPSC110F Instruction Registers. into
Repeat each board involved backplane test. Drive/Capture: SCANPSC110F selected their LSPs that interface backplane components unparked sequenced through Update-DR Capture-DR states. Select SCANPSC110F scanning broadcast address into SCANPSC110F Instruction Registers. Scan PARKPAUSE command into Instruction Register selected SCANPSC110F. Sequence backplane TAPs Pause-DR state order unpark LSP. Sequence from Pause-DR state through Update-DR through Capture-DR Exit1-DR Update-DR. This will execute next vector repark Pause-DR state. Scan GOTOWAIT command SCANPSC110F Instruction Registers. into
Shift Test Results from Last Vector: test results from last vector shifted while shifting safe dummy vector, that 3-states bus. Select SCANPSC110F scanning address into SCANPSC110F Instruction Register. Scan PARKPAUSE command into Instruction Register selected SCANPSC110F. (The PARKPAUSE command used unpark well park LSP). Sequence backplane TAPs Pause-DR state order unpark LSP. From Pause-DR state, transition Exit2-DR Shift-IR, where results last test vector shifted out, Exit1-DR Update-DR. will reparked Pause-DR state when transitioning from Exit1-DR Update-DR, because PARKPAUSE command still active. Scan GOTOWAIT command SCANPSC110F Instruction Registers. into
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AN-1023 Structural System Test IEEE Std. 1149.1 with Hierarchical Multidrop Addressable JTAG Port, SCANPSC110F
Reset Test Logic: This performed clocking TCKBP eight times while holding TMSBP high. takes three clocks reset SCANPSC110F from Run-Test/Idle state five more reset target components from Pause-DR state. general, takes five TCK's each level test hierarchy.
Fairchild does assume responsibility circuitry described, circuit patent licenses implied Fairchild reserves right time without notice change said circuitry specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL PRESIDENT FAIRCHILD SEMICONDUCTOR CORPORATION. used herein: Life support devices systems devices systems which, intended surgical implant into body, support sustain life, whose failure perform when properly used accordance with instructions provided labeling, reasonably expected result significant injury user. www.fairchildsemi.com critical component component life support device system whose failure perform reasonably expected cause failure life support device system, affect safety effectiveness. www.fairchildsemi.com

AN-1023 Fairchild Semiconductor Application Note November 1995 Re

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