This Application Note describes configuration required connect Atmel A

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This Application Note describes configuration required connect Atmel A

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Connecting Atmel ARM-based Serial Synchronous Controller (SSC) I2S-compatible Serial
This Application Note describes configuration required connect Atmel ARMbased Synchronous Serial Controller (SSC) device with I2S-compatible serial bus, such stereo audio digital-to-analog converter (DAC) stereo audio Codec. digital interface these audio devices generally compliant with standard. I2S-standard compliant device word length bits, does peripheral embedded AT91RM9200 series microcontrollers. (Inter-IC Sound) serial designed digital audio devices technologies, such compact disc (CD) players, digital sound processors, digital (DTV) sound. characteristics protocol separate handling audio data clock signals. Separating data clock signals eliminates need anti-jitter devices removing time-related errors. Application Note includes dedicated software package AT91RM9200, applicable Atmel ARM-based products that embed Synchronous Serial Controller (SSC). This application note takes into account warnings described AT91RM9200 Errata Sheet, literature number 6015.
AT91 ARM® Thumb® Microcontrollers Application Note
Warranty
delivered sources free charge copied modified without authorization. software delivered without warranty condition kind, either express, implied statutory. This includes without limitation warranty condition with respect merchantability fitness particular purpose, against infringements intellectual property rights others.
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Audio
(Inter-IC Sound) standard based three-wire architecture. This standard defines serial link dedicated data transfer between integrated circuits digital audio systems. This three-wire link provides additional information audio data, such subcoding control, transferred separately. three lines defined protocol are: Serial Data (SD) line containing time-division multiplexed channels left/right channel Word Select (WS) continuous Serial Clock (SCK)
link used primarily send audio data from processor(master) Audio (slave). three lines driven master transmitter Serial Data Out) time-division multiplexed channels (from master slave) left/right channel Word Select (WS) continuous Serial Clock (SCK); master (transmitter) slave (receiver) share same clock signal data transmission
additional line used connect slave input signal (such audio Codec): Serial Data time-division multiplexed channels (from slave master)
Figure Block Diagram Example
TRANSMITTER MASTER Clock Word Select TRANSMITTER Data Data RECEIVER
Clock Word Select Data
Data
Left Channel
Right Channel
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Word Length Considerations
standard defines several possible data (word) lengths from bits. most audio applications, data length bits, corresponding dynamic range
Note: dynamic range given following formula: Dynamic Range Range where range 2bit
Table Range versus Dynamic Range
Range
Dynamic Range
Only 16-bit words managed maximum value field FSLEN Frame Mode Register.
Clock Considerations sampling frequency audio devices vary from 16-bit data.
generate data with correct rate, peripheral divides internal peripheral clock (MCK) integer factor. Table indicates error audio clock signal frequency (related peripheral main clock) compared ideal value. this uncertainty, peripheral clock value thus crystal frequency must chosen carefully with respect limitations components. rate determines data flow clock signal frequency: Rate Number Bits Channel Number Channels Sampling Frequency 16-bit audio, left/right, rate calculated follows: Rate Sampling Frequency divider factor value SSC_CMR register equals half peripheral clock frequency (MCK) divided required rate. this factor integer, real rate (generated SSC) different from theoretical one. Table gives error between theoretical real values audio sample frequency. important note that difference between frequency levels result distortion audio output signal. Table Using Clock
Theoretical Audio Sample Frequency (Hz) Theoretical Rate Theoretical Divider Factor 39.06250 42.51701 85.03401 117.18750 234.37500 SSC_CMR (Real Divider Factor) (40) (42) (86) (118) (234) Audio Sample Frequency (Hz)
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Connection Stereo Audio
following implementation using illustrates connection audio output ARM-based microcontroller embedding peripherals. used connected processor, sending 16-bit words, wordselect signal serial clock. standard audio DAC, only used audio output, connected slave. Figure Audio Connection
Audio Clock Word Select Data Stereo Audio 3550A Audio
Command TWCK
Atmel ARM-based Microcontroller
Table gives hardware connections between microcontroller Micronas 3550A: Table Hardware Connections
Microcontroller (TFx) (TKx) (TDx) (TWCK) (TWD) 3550A Name (I2S) (I2S) (I2S)
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Configuring
following example illustrates peripherals embedded AT91RM92000, SSC1. related lines Parallel Input/Output Controller (PIO) configured peripheral mode. When using DAC, only three lines emitter used because used master only emission. software configured according following general characteristics: Sample audio frequency (FILE_SAMPLING_FREQ): 44.1 Number slots frame (SLOT_BY_FRAME): Number bits slot (BITS_BY_SLOT): peripheral clock (MCK): (left right channels) (data length bits)
Note:
parameters functions compliant with ARM-based Software Packages Application Note, lit. 6016.
Standard Initialization
following configuration steps common serial peripherals: Configure corresponding Parallel Input/Output Controller work peripheral mode, i.e., three lines related SSC1 multiplexed with PIOB must management mode.
*AT91C_PIOB_PDR= ((unsigned int) AT91C_PB7_TK1 ((unsigned int) AT91C_PB8_TD1 ((unsigned int) AT91C_PB6_TF1
Configure Power Management Controller enable current peripheral enabling SSC1 clock.
AT91F_SSC1_CfgPMC();
Reset SSC1:
pSSC->SSC_CR AT91C_SSC_SWRST
Clear Transmit Receive Counters:
AT91F_PDC_Close((AT91PS_PDC) &(pSSC->SSC_RPR));
Configuring Clock Mode Register (SSC_CMR)
definition Clock Mode Register done characteristics described above (sample audio frequency, number slots frame, data length peripheral clock frequency). This setting managed standard software package.
function AT91F_SSC_SetBaudrate: rate= 2*16*44100 1.4112 AT91F_SSC_SetBaudrate( pSSC,MCK,
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Configuring Transmit Frame Mode Register (SSC_TFMR)
Transmit Frame Mode register used manage both (corresponding Word Select line) (corresponding data line) signals. Table Transmit Frame Mode Register (SSC_TFMR) Settings
Field Name DATLEN DATDEF Value BITS_BY_SLOT-1 Comments Programs Data Length Default value data. compatibility with protocol, bits zero when sending data. Most Significant First. sent first. Data Number frame. Programs number data contained frame. Frame Sync LENgth. Programs duration active level number serial clock cycles. Word Select signal must long data word. Frame Sync Output Selection Frame Sync Data ENable. Sync Data (SSC_TSHR) emit. Frame Sync Edge Detection used this case.
MSBF DATNB FSLEN
SLOT_BY_FRAME BITS_BY_SLOT
FSOS FSDEN FSEDGE
Negative Pulse Disabled Positive Edge Detection
*AT91C_SSC1_TFMR (AT91C_SSC_FSOS_NEGATIVE (((BITS_BY_SLOT-1)<<16) AT91C_SSC_FSLEN) (((SLOT_BY_FRAME-1)<<8) AT91C_SSC_DATNB) AT91C_SSC_MSBF (BITS_BY_SLOT-1)
Configuring Interrupt Mode
this application, Peripheral Data Controller (PDC) interrupt sources handled loop sending wave file DAC. Configure Advanced Interrupt Controller (AIC) handle interrupts:
AT91F_AIC_ConfigureIt AT91C_BASE_AIC, AT91C_ID_SSC1, IRQ_LEVEL_I2S, AT91F_ASM_I2S_Handler base address System peripheral priority
Level sensitive
Enable interrupt AIC:
AT91C_ID_SSC1);
Enable Transmit interrupt Interrupt Enable Register:
AT91F_SSC_EnableIt (pSSC, AT91C_SSC_ENDTX);
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Configuring Configure PDC:
AT91F_PDC_SetTx ((AT91PS_PDC) &(pSSC->SSC_RPR), (char *)wav_file, AT91C_WAV_FILE_SIZE/2); AT91F_PDC_SetNextTx ((AT91PS_PDC) &(pSSC->SSC_RPR), (char *)wav_file, AT91C_WAV_FILE_SIZE/2);
Enable feature:
AT91F_PDC_EnableTx ((AT91PS_PDC) &(pSSC->SSC_RPR));
Enabling Peripheral Starting Transmission
Transmit Clock Mode Register must configured before enabling starting transmission. Then, when transmission enabled, starts automatically. Table Transmit Clock Mode Register (SSC_TFMR) Settings
Field Name Value Divided Clock Comments Transmit Clock Selection. Internally generated divided clock (from peripheral clock MCK) selected. Clock Output Mode Transmit Clock Inversion. data frame sync signals shifted transmit clock falling edge. Transmit Start Selection. first word transferred left channel. Transmit Start Delay. First after falling edge signal last right channel. Transmit Period Divider Selection. Frame Length, including left right channel
Continuous Transmit Clock Shifting serial clock falling edge Falling edge signal
START STTDLY
PERIOD
((SLOT_BY_FRAME *BITS_BY_SLOT)/2)
*AT91C_SSC1_TCMR
<<24)
((1<<16) AT91C_SSC_STTDLY) AT91C_SSC_START_FALL_RF AT91C_SSC_CKO_CONTINOUS AT91C_SSC_CKS_DIV);
Enable transmitter:
AT91F_SSC_EnableTx (pSSC);
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Connection Stereo Audio Codec
following examples illustrate peripherals AT91RM9200 connecting stereo audio Codec. peripheral AT91RM9200 able manage channels output mode channel input mode. This sufficient most applications using Codec generally only channel required input mode. Hardware software configurations related this type application described "Configuration Stereo Output Mono Input" page When channels managed input mode (i.e., received frame bits), AT91RM9200 requires channels. Hardware software implementation related this type application described "Configuration Stereo Input Output" page
Configuration Stereo Output Mono Input
connect Codec stereo output mono channel input (only left channel), following implementation using with 16-bit data format used. standard audio Codec used both output input modes. SSC, used master mode, manages transmit signals. Figure Stereo Audio Codec with Input Channel
Atmel ARM-based Microcontroller Stereo Audio CODEC e.g. TSC2301 Audio Clock Word Select Audio Audio
Configuring
following configuration example using AT91RM9200 peripherals (SSC1). Parallel Input/Output Controller (PIO) configured peripheral mode corresponding lines.
Configuring Receive Frame Mode Register
Receive Frame Mode Register (SSC_RFMR) configured manage data reception. Table Receive Frame Mode Register (SSC_RFMR) Settings
Field Name DATLEN LOOP Value BITS_BY_SLOT LOOP Comments Programs Data Length Loop Mode. compatibility with protocol, bits zero when sending data. Most Significant First. received first.
MSBF
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Table Receive Frame Mode Register (SSC_RFMR) Settings (Continued)
Field Name DATNB FSLEN FSOS FSDEN FSEDGE Value slot frame) (Default value because used) used Disabled Positive Edge Detection (Default value Comments Data Number frame. Programs number data contained frame. Frame Sync LENgth. Frame Sync Output Selection Frame Sync Data ENable. Sync Data (SSC_RSHR) receive. Frame Sync Edge Detection used this case.
*AT91C_SSC1_RFMR AT91C_SSC_MSBF (BITS_BY_SLOT-1)
Configuring Receive Clock Mode Register Table SSC1 Receive Clock Mode Register (SSC1_RCMR) Settings
Field Name START STTDLY Value Clock Signal (Default value) Sampling rising edge serial clock Transmit Start Comments Receive Clock Selection Clock Output Mode Selection. Used. Receive Clock Inversion Receive Start Selection Receive Start Delay. First after falling edge last right channel. Receive Period Divider Selection. used
PERIOD
*AT91C_SSC1_RCMR AT91C_SSC_CKS_TK AT91C_SSC_START_TX ((1<<16) AT91C_SSC_STTDLY) AT91C_SSC_CKI
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Configuration Stereo Input Output
connect Codec stereo input output (both channels received), following implementation using with 16-bit data format used. standard audio Codec used input output modes. first peripheral, used master mode, manages transmit signals left-channel input. second peripheral manages right-channel input only synchronized with first peripheral. Figure Stereo Audio Codec with Input Channels
Audio Clock Word Select Stereo Audio CODEC e.g. TSC2301 Audio Audio
Atmel ARM-based Microcontroller
Configuring SSC1
configuration settings SSC1 same those described "Configuration Stereo Output Mono Input" page
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Configuring SSC0 SSC0 must configured receive second stereo input channel. Configure enabling SSC0 clock:
*AT91C_PMC_PCER AT91C_ID_SSC0; peripheral clock*/ enable SSC0
Reset SSC0 Peripheral:
*AT91C_SSC0_CR AT91C_SSC_SWRST
Configure SSC0 Receive Frame Mode Register. Receive Frame Mode Register (RFMR) configured manage data reception. Table SSC0 Receive Frame Mode Register (SSC0_RFMR) Settings
Field Name DATLEN LOOP Value BITS_BY_SLOT LOOP Comments Programs Data Length Loop Mode. compatibility with protocol, bits zero when sending data. Most Significant First. received first. Data Number frame. Programs number data contained frame. Frame Sync LENgth. Frame Sync Output Selection Frame Sync Data ENable. Sync Data (SSC_RSHR) receive. Frame Sync Edge Detection used this case.
MSBF DATNB FSLEN FSOS FSDEN FSEDGE
slot frame) (Default value because used) used Disabled Positive Edge Detection (Default value
Settings identical those SSC1. *AT91C_SSC0_RFMR AT91C_SSC_FSOS_NONE AT91C_SSC_MSBF (16-
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Table SSC0 Receive Clock Mode Register (SSC0_RCMR) Settings
Field Name START Value Clock Signal (Default value) Sampling rising edge serial clock rising edge Comments Receive Clock Selection Clock Output Mode Selection. Used. Receive Clock Inversion Receive Start Selection. Receiver SSC0 must right channel while SSC1 receiving left channel. Start edge condition inverted with respect SSC1. Receive Start Delay. First after falling edge last right channel. Receive Period Divider Selection. used
STTDLY
PERIOD
*AT91C_SSC0_RCMR AT91C_SSC_CKS_RK AT91C_SSC_CKO_NONE AT91C_SSC_CKI AT91C_SSC_START_RISE_RF ((1<<16) AT91C_SSC_STTDLY)
Enable SSC0 receiver
*AT91C_SSC0_CR AT91C_SSC_RXEN; Enable
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6020A-ATARM-11/03

This Application Note describes configuration required connect Atmel A

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