this application note help user test bench using Atmel's TS8388B 8-bit

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this application note help user test bench using Atmel's TS8388B 8-bit

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Getting Started with TS8388B 8-bit Gsps TS81102G0 1:4/8 DMUX
this application note help user test bench using Atmel's TS8388B 8-bit Gsps TS81102G0 1:4/8 DMUX evaluation boards. first gives description test bench used Atmel's laboratory, provides recommendations connect components together finally describes detail test procedure that should followed rapidly evaluate Atmel broadband data conversion devices.
TS8388B TS81102G0
Evaluation Boards Application Note
Rev. 5350A-BDC-10/03
Figure Test bench
TS8388B TS81102G0 Evaluation Boards
5350A-BDC-10/03
E4426B TSEV8388BG TSEV83102G0 Evaluation Board TSEV81102G0 Evaluation Board
Input Signal Generator Filter Synchronization Exit
DEMUX
HP16500C Clock Signal Generator
Digital Acquisition System
E4426B Histogram Reconstructed Signal ENOB, SFDR, INL,
LabView
Scientific Computer
TS8388B TS81102G0 Evaluation Boards
Interfacing DMUX Evaluation Boards
Settings
TSEV8388BF/FZA2 Evaluation Boards (ADC CQFP Package) Figure Evaluation Boards (ADC CQFP Package)
Clkin Clkinb
Figures there offset between output connector DMUX input connector.
Evaluation Board Component Side
DMUX Evaluation Board Component Side
Evaluation Board Component Side
DMUX Evaluation Board Component Side
Note:
this configuration, DMUX Ensure boards connected illustrated above, otherwise
DMUX damaged forcing signal ground, example.
5350A-BDC-10/03
TSEV8388BGL/GLZA2 Evaluation Boards (ADC CBGA Package) Figure Evaluation Boards (ADC CBGA Package)
Clkin Clkinb
Evaluation Board Component Side
DMUX Evaluation Board Component Side
Note:
Ensure boards connected illustrated above, otherwise damage DMUX occur forcing signal ground, example.
TS8388B TS81102G0 Evaluation Boards
5350A-BDC-10/03
TS8388B TS81102G0 Evaluation Boards
TSEV8388BGL/F Evaluation Boards without Digital Output Buffers Since both data outputs on-board differentially terminated DMUX input buffers on-chip differentially terminated, necessary remove extra termination when board plugged DMUX board.
Figure Boards without Digital Output Buffers
Differential terminations removed
5350A-BDC-10/03
TSEV8388BGLZA2/FZA2 Evaluation Boards with Digital Output Buffers TSEV81102G0TPZR3 DMUX Evaluation Board
DMUX boards connected directly another with hardware modification required.
necessary extra decoupling capacitors DMUX output between ground: capacitors recommended with capacitor Figure DMUX Evaluation Board
Capacitor between Capacitor between Capacitor between
Access
Access
Access
Access
Capacitor between
TS8388B TS81102G0 Evaluation Boards
5350A-BDC-10/03
TS8388B TS81102G0 Evaluation Boards
Other Settings
DMUX jumpers(1) BIST: jumper (BIST inactive) NBBIT: jumper (8-bit) CLKINTYPE: jumper (DR/2 mode) RATIOSEL: jumper (for ratio)
Power supplies DVEE connected supply connected supply VPLUSD connected ground connected supply(2) VEET connected supply(2)
DMUX connected supply connected supply connected mode
grounds have connected together.
Notes: BIST jumper BIST active NBBIT jumper 10-bit CLKINTYPE jumper mode RATIOSEL jumper ratio VEET power supplies have connected sources respectively only board "ZA2" suffix ("with buffer" option).
Connecting Logic Analyzer
Once DMUX boards connected ready operation, last step before power connect logic analyzer probes DMUX outputs. recommended have least DMUX ports fully connected logic analyzer addition Data Ready signal from DMUX, thus providing synchronization clock logic analyzer.
Quick Start
Power Sequence
Apply DVEE power supplies both DMUX) Turn power supply both DMUX) applicable ("with buffer" board), supply VEET Supply grounds have connected well VPLUSD directly ground) Apply clock sinusoidal differential clock) analog input dBFS input level) Perform asynchronous reset DMUX
5350A-BDC-10/03
devices should operate properly. next section describes test procedure followed that whole system works correctly optimum results obtained.
Test Procedure
DMUX Output Levels Setting
Static Adjustment Configuration DMUX logic analyzer clock analog input signals active input (the frequency both signals importance could choose Gsps close Fs/2 optimum settings). Perform asynchronous reset DMUX then release make system operational re-activate asynchronous reset freeze outputs their level reset.
Note: Always choose that Fs/Fin N/M, where number samples (2n) number cycles (must number).
This first step mandatory match logic analyzer threshold DMUX output levels both dynamic conditions.
While asynchronous reset DMUX active (held high), with voltmeter measure levels output bits DMUX Vref level ports. Vref should close (VOL VOH)/2. typical case, Vref lower than (VOL VOH)/2. logic analyzer threshold value obtained with (VOL+VOH)/2.
Notes: logic analyzer threshold very important parameter single-ended data acquisition. This case when dealing with differential data acquisition (both Data DataB taken into account).
necessary calibrate logic analyzer with probes connected prior first acquisition. Setting threshold logic analyzer between -1.4 -1.6 should satisfy conditions detection DMUX output data. Dynamic Check make sure previous value logic analyzer threshold correct both dynamic domains, dynamic test performed. From last configuration, de-activate asynchronous reset DMUX (the data should then DMUX output). With Gsps close Fs/2 Nyquist conditions), measure with oscilloscope (eye diagram). Vref value also checked with voltmeter. obtained VOL, Vref values should close ones found during previous test. not, recommend re-check connection between DMUX boards: data from properly sent DMUX? Perform another asynchronous reset DMUX what happens. Tune DMUX swing adjust.
TS8388B TS81102G0 Evaluation Boards
5350A-BDC-10/03
TS8388B TS81102G0 Evaluation Boards
still cannot identify source your problem: Check entire system again. Take down your test conditions.
Finally, contact hotline hotline-bdc@gfo.atmel.com support. output swing (VOH VOL) logic analyzer detect DMUX outputs, then DMUX swing adjust should used. tuning swing adjust, should able obtain satisfying values VOL, Vref.
Note: nominal setting swing adjust (SWIADJ DMUX should suitable standard logic analyzer.
DMUX Delay Adjust
Once sure that logic analyzer effectively detects DMUX outputs, next adjustment delay adjust DMUX (DMUXDelAdj). Using same configuration previously described Gsps close Fs/2), find right DMUX delay perform optimum synchronization between DMUX. this setting, special care taken with sampling input frequencies. fact, adjustment DMUX delay adjust depends sampling frequency. dependent input frequency, optimum setting given sampling frequency achieved when Nyquist condition met, where Fs/2. find right adjustment between DMUX ADC, recommended cover entire DMUX delay adjust range check reconstructed signal obtained each delay. optimum delay which corresponds clean reconstructed signal with glitch possible that whole range delays satisfactory). addition, illustrated Figure should choose delay close adjustment where gives poor results.
Figure DMUX Delay Adjust
Poor results Minimum delay
Clean reconstructed signal
Poor results Maximum delay
recommended setting
Optimum setting
recommended setting
5350A-BDC-10/03
Logic Analyzer Delay Adjust
results still satisfactory (glitches reconstructed signal), last adjustment make logic analyzer delay. means oscilloscope, diagram with data Data Ready signal should observed. theory, Data Ready signal should right middle data small amount skew have made shift right left. Fine tuning logic analyzer delay then necessary prop Data Ready signal middle data. Figure Logic Analyzer Delay Adjust
Data Ready
delay adjust steps
delay adjust steps
Data
then recommend proceed follows: First, steps, change logic analyzer delay approximately find "good" "bad" zones (this where reconstructed signal shows many glitches) Second, steps, fine-tune logic analyzer delay until reconstructed signal glitch until test gives satisfying dynamic results. Typical results should obtain are: Gsps dBFS input level) SFDR ENOB bits still obtain expected results ADC, please contact hotline specific technical support hotline-bdc@gfo.atmel.com
TS8388B TS81102G0 Evaluation Boards
5350A-BDC-10/03
Atmel Corporation
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Literature Requests
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5350A-BDC-10/03

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