This application note describes generate Pulse Width Modulation (PWM)

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This application note describes generate Pulse Width Modulation (PWM)

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Pulse Width Modulation Generation Using AT91 Timer/Counter
This application note describes generate Pulse Width Modulation (PWM) signal, tunable frequency duty cycles, using AT91 Timer/Counter (TC).
Timer/Counter Overview
AT91 series microcontrollers feature Timer Counter block which includes three identical 16-bit timer counter channels. Each channel independently programmed, through operating modes, perform wide range functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing, pulse width modulation interrupt generation. Each Timer Counter channel external clock inputs, internal clock inputs, multi purpose input/output signals, which configured user. Each channel drives internal interrupt signal, which programmed generate processor interrupts Advanced Interrupt Controller (AIC). three Timer Counter channels independent identical operation. Each Timer Counter channel organized around 16-bit counter. value counter incremented each positive edge selected clock. When counter reached value 0xFFFF passes 0x0000, overflow occurs COVFS TCx_SR (Status Register) set. current value counter accessible real-time reading TCx_CV. trigger reset counter. this case, counter value passes 0x0000 next valid edge selected clock.
AT91 ARM® Thumb® Microcontrollers Application Note
2682B-ATARM-03-Oct-03
Timer/Counter Operating Each Timer Counter channel operate independently different modes: Modes Capture Mode provides measurement signals.
Waveform Mode provides wave generation. Timer Counter Operating Mode programmed with WAVE Channel Mode Register (TCx_CMR). Capture Mode, TIOA TIOB configured inputs. Waveform Mode, TIOA always configured output TIOB output selected external trigger.
Trigger
Common Triggers
trigger resets counter starts counter clock. Three types triggers common both modes, fourth external trigger available each mode. following triggers common both operating modes: Software Trigger: Each channel software trigger, available setting SWTRG TCx_CCR. SYNC: Each channel synchronization signal SYNC. When asserted, this signal same effect software trigger. SYNC signals channels asserted simultaneously writing TC_BCR (Block Control) with SYNC set. Compare Trigger: implemented each channel provide trigger when counter value matches value CPCTRG TCx_CMR.
External Trigger
Timer Counter channel also configured have external trigger. Capture Mode, external trigger signal selected between TIOA TIOB. Waveform Mode, external event programmed following signals: TIOB, XC0, XC2. This external event then programmed perform trigger setting ENETRG TCx_CMR. external trigger used, duration pulses must longer than system clock (MCK) period order detected.
Generation Using AT91 Timer/Counter
2682B-ATARM-03-Oct-03
Generation Using AT91 Timer/Counter
Timer/Counter Block Diagram
Figure Timer/Counter Block Diagram
MCK/2 MCK/8 MCK/32 MCK/128 MCK/1024
Parallel Controller TCLK0 TIOA1 TIOA2 TCLK1 TCLK2 TC0XC0S
SYNC
TCLK0 TCLK1 TCLK2 TIOA0 TIOB0
Timer/Counter Channel
TIOA
TIOA0
TIOB
TIOB0
TCLK0 TCLK1 TIOA0 TIOA2 TCLK2 TC1XC1S
SYNC
Timer/Counter Channel
TIOA
TIOA1
TIOB
TIOB1
TIOA1 TIOB1
TCLK0 TCLK1 TCLK2 TIOA0 TIOA1
Timer/Counter Channel
TIOA
TIOA2
TIOB
TIOB2
SYNC
TIOA2 TIOB2
TC2XC2S
Timer Counter Block Advanced Interrupt Controller
2682B-ATARM-03-Oct-03
Clock Source
Each channel independently select internal external clock source counter: Internal clock signals: MCK/2, MCK/8, MCK/32, MCK/128, MCK/1024 External clock signals: XC0,
three-bit TCCLKS field mode register TCx_CMR determines whether counter clocked five internal clock sources (MCK/x) three external clock sources (TCLKx). selected clock inverted with CLKI TCx_CMR (Channel Mode Register). This enables counting opposite edges clock. burst function allows clock validated when external signal high. BURST parameter Mode Register defines this signal (none, XC0, XC1, XC2). Note: cases, external clock used, duration each levels must longer than system clock (MCK) period. external clock frequency must least times lower than system clock (MCK). Figure Timer/Counter Clock Source
CLKS
TCx_CMR[2:0]
MCK/2 MCK/8 MCK/32 MCK/128 MCK/1024
Burst
TCx_CMR[5:4]
CLKI
TCx_CMR[3]
Clock Counter
BURSTCLK
maximal counter duration when internal clock used determined internal clock prescaler number:
maximal counter duration (seconds) counter resolution
where
Table Maximum Counter Duration
MCK/2 MCK/8 MCK/16 MCK/128 MCK/1024 26.21ms 104.8ms 419.4ms 1.68s 13.42s
13.10ms 52.4ms 209.7ms 838.8ms 6.71s
6.55ms 26.22ms 104.86ms 420.4ms 3.36ms
3.97ms 14.89ms 63.86ms 254.2ms 2.03s
1.98ms 7.45ms 31.98ms 127.1ms 1.02s
Generation Using AT91 Timer/Counter
2682B-ATARM-03-Oct-03
Generation Using AT91 Timer/Counter
Pulse Width Modulation Generation
waveform mode entered setting WAVE (bit Mode Register) forces TIOA output pin. TIOB used either output (dual waveform mode) input (single waveform mode). Waveform Operating Mode allows Channel generate signals with same frequency independently programmable duty cycles, generate different types one-shot repetitive pulses. Waveform Operating Mode, used compare registers. compare registers generate counter reset (RC) waveform modification (RA, when counter reaches value programmed them. Compare used control TIOA output. Compare used control TIOB configured output). Compare programmed control TIOA and/or TIOB outputs. Compare also generate trigger CPCTRG trigger resets counter that control period waveforms. Each these events programmed set, clear toggle output defined corresponding parameter TCx_CMR.
Application Example
AT91 Timer/Counter generation frequency with duty cycle TIOA duty cycle TIOB. This application example based AT91EB40A Evaluation Board applicable AT91 products. compare generate trigger CPCTRG Mode Register trigger resets counter signal period controlled Compare register. duty cycle TIOA TIOB controlled Compare registers respectively. trigger event sets TIOA TIOB then TIOA toggled TIOB shown below Figure Figure Dual Pulse Width Modulation Generation
Counter
Timer configuration
TIOA
TIOB
Trigger
Master Clock AT91EB40A Evaluation Board MHz. value needed compare register assure timer period (1kHz fre5
2682B-ATARM-03-Oct-03
quency) must established. frequency controlled compare register minimal prescaler value required select timer clock must first determined. maximal counter value 0xFFFF (65535): 66000000 0.001 1.007 65535 65535 value 1.007 Therefore, timer clock must least MCK/2 (33000000Hz) have compare period 1ms. application, required compare register values must calculated using following equation:
Compare Value
Where desired timer compare period (second) timer clock frequency(Hertz) Compare register 33000000 1000 33000 80E8 Fpwm 1000 duty cycle TIOA, compare register 33000 9900 26AC duty cycle TIOB, compare register 33000 16500 4074
Generation Using AT91 Timer/Counter
2682B-ATARM-03-Oct-03
Generation Using AT91 Timer/Counter
Software Code
following software code example generates dual 1kHz with duty cycle TIOA duty cycle TIOB using Timer/Counter waveform mode AT91EB40A Evaluation Board applicable entire AT91 series.
//*-//*The software delivered without warranty condition kind, either express, implied statutory. This includes //*without limitation warranty condition with respect merchantability fitness particular purpose, against //*infringements intellectual property rights others. //*-//* File Name Object Author wave_pwm.c AT91EB40A Timer Counter Dual generation AT91 Application Group
//*-//* Configure channel Timer Counter(TC) AT91EB40A dual waveform generation frequency 1kHz clock selected Register compare toggle TIOA1 when reached Register compare toggle TIOB1 when reached Register compare toggle TIOA1 TIOB1 when reached //*-
#define #define #define #define #define
TC1_CCR TC1_CMR TC1_RA TC1_RB TC1_RC
((volatile unsigned 0xFFFE0040) ((volatile unsigned 0xFFFE0044) ((volatile unsigned 0xFFFE0054) ((volatile unsigned 0xFFFE0058) ((volatile unsigned 0xFFFE005C)
#define
PIO_PDR
((volatile unsigned 0xFFFF0004)
TC_CMR: Timer Counter Channel Mode Register Bits Definition #define #define #define #define #define #define #define #define #define #define TC_CLKS_MCK20x0 TC_EEVT_XC0 TC_CPCTRG TC_WAVE TC_ACPA_TOGGLE_OUTPUT TC_ACPC_TOGGLE_OUTPUT TC_ASWTRG_SET_OUTPUT TC_BCPB_TOGGLE_OUTPUT TC_BCPC_TOGGLE_OUTPUT TC_BSWTRG_SET_OUTPUT 0x400 0x4000 0x8000 0x30000 0xC0000 0x400000 0x3000000 0xC000000 0x40000000
TC_CCR: Timer Counter Control Register Bits Definition #define #define #define TC_CLKEN TC_CLKDIS TC_SWTRG
Controller
2682B-ATARM-03-Oct-03
#define #define
PIOTIOA1 PIOTIOB1
Timer Signal Timer Signal
//*-//* Function Name main Object: Timer Counter configuration generate Dual generation //*-int main void Begin *TC1_CCR TC_CLKDIS *PIO_PDR (1<<PIOTIOA1) (1<<PIOTIOB1) Disable Clock Counter Define TIOA1 TIOB1 peripheral
Timer/Counter mode configuration *TC1_CMR TC_BSWTRG_SET_OUTPUT TC_BCPC_TOGGLE_OUTPUT TC_BCPB_TOGGLE_OUTPUT TC_ASWTRG_SET_OUTPUT TC_ACPC_TOGGLE_OUTPUT TC_ACPA_TOGGLE_OUTPUT TC_WAVE TC_CPCTRG TC_EEVT_XC0 TC_CLKS_MCK2 Compare registers initialization *TC1_RC 0x80E8 *TC1_RB 0x4074 *TC1_RA 0x26AC 1kHz generation duty cycle TIOB1 duty cycle TIOA1 BSWTRG BCPC BCPB ASWTRG ACPC ACPA software trigger TIOB
Register compare toggle TIOB Register compare toggle TIOB software trigger TIOA
Register compare toggle TIOA Register compare toggle TIOA Waveform mode Register compare trigger enable external event (TIOB=output)
WAVE CPCTRG EEVT
TCCLKS
*TC1_CCR TC_CLKEN *TC1_CCR TC_SWTRG
Enable Clock counter Trig timer
(;;) }//* return(0) }//*End
Generation Using AT91 Timer/Counter
2682B-ATARM-03-Oct-03
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2682B-ATARM-03-Oct-03

This application note describes generate Pulse Width Modulation (PWM)

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