Pulse Width Modulation (PWM) technique provide logic logic controlled

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Pulse Width Modulation (PWM) technique provide logic logic controlled

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Pulse Width Modulation
Pulse Width Modulation (PWM) technique provide logic logic controlled period time. Pulse Width Modulation used many applications such controlling speed motor. This application note describes implementation simple using Atmel's FPGAs. basic principle register store value which loaded Up/Down Counter whenever counter reaches terminal count. terminal counter used generate pulse width modulation.
Functional Description
data register used store value counter, this value determines pulse width. Up/Down Counter loaded with value from data register when counter reaches terminal count; Toggle Flip-flop generates output. When data value first loaded, counter begins count down from data value During this phase operation terminal count signals Low. When counter transitions through terminal count generated triggers Toggle Flip-flop drive signal High. data value re-loaded counting proceeds maximum value. Again terminal count will generated when counter reaches maximum value, driving signal toggle from High Low. data value re-loaded cycle repeats. direction counter controlled signal: counter count down when Low, count when High. terminal count controls data value that loads counter from data register. Data loaded when terminal count High. duty cycle signal controlled data value loaded up/down counter. duty cycle output varied specifying various data values, higher data value, higher duty cycle (see Table Table Data Values Different Duty Cycles
Data Value 11100110 11000000 10000000 01000000 00011001 Duty Cycle
Programmable AT40K AT40KAL AT94K Application Note
Rev. 2324A-10/01
Block Diagram
Data Data
Data Register
Clock Up/down
Up/down Counter
Toggle Flip-Flop
Clock
Load Reset
Figure Sample Output Waveform(1)
Mark Period(2) Data Value Tclock
Frame Period Tclock
Notes:
Duty Cycle calculated taking ratio Mark Period Frame Period: Duty Cycle Mark Period/Frame Period Data Value/2n. Mark Period Data Value Tclock. Frame Period Tclock where binary counter width.
Design Implementation
8-bit counter implemented using VHDL. design uses 8-bit data register, 8-bit up/down counter comparator logic. designer easily modify design different resolution changing data register counter width. VHDL source files, testbench files user packages downloaded from Atmel's site. Table provides list software requirements design implementation.
Table Software Requirements
Tool VHDL Synthesizer Requirement Exemplar's LeonardoSpectrumor Synthesis tool which supports Atmel AT40K architecture Atmel's above System DesignerModelSim® simulator simulator tool which supports VITAL VHDL
Place Route Simulator
Pulse Width Modulation
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Pulse Width Modulation
Sample Design Using LeonardoSpectrum, Figaro ModelSim Simulator
Copy source file pwm_fpga.vhd your project design directory. This file downloaded from Atmel's site, Start LeonardoSpectrum. Select AT40K under Technology window click open files select pwm_fpga.vhd from your project directory. Click Leonardo read design file, Atmel architecture synthesize. successful compilation will generate pwm_fpga.edf. Import pwm_fpga Figaro placement routing. Generate bistream this bistream configure FPSLICTM. resulting signal shown Figure Figure ModelSim Simulator Result Duty Cycle Wave
2324A-10/01
Source Files
pwm_fpga.vhd
Library IEEE; ieee.std_logic_1164.all; ieee.std_logic_arith.all
work.user_pkg.all;
ENTITY pwm_fpga PORT clock,reset: STD_LOGIC; std_logic_vector(7 downto
Data_value pwm_fpga;
STD_LOGIC
ARCHITECTURE arch_pwm
pwm_fpga
SIGNAL reg_out std_logic_vector(7 downto SIGNAL cnt_out_int: std_logic_vector(7 downto SIGNAL pwm_int, rco_int: std_logic;
BEGIN 8-bit data register store data values .The data values -will determine duty cycle output
PROCESS (clock,reg_out,reset)
BEGIN (reset ='1') THEN reg_out <="00000000"; ELSIF (rising_edge(clock)) THEN reg_out data_value; PROCESS; -8-bit up/down counter. Counts down based -and generates terminal count -maximum value pwm_int signal
whenever counter reaches through zero. Terminal
when transists
-count uesd automatically load data value generate -different with different duty cycle -INC functions which used -down counting. they defined sepearate user_pakge library
PROCESS
BEGIN
(rco_int '1') THEN cnt_out_int reg_out;
Pulse Width Modulation
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Pulse Width Modulation
ELSIF rising_edge(clock) THEN (rco_int pwm_int ='1' cnt_out_int <"11111111") THEN cnt_out_int INC(cnt_out_int); ELSE (rco_int ='0' pwm_int ='0' cnt_out_int "00000000") THEN cnt_out_int DEC(cnt_out_int); PROCESS;
PROCESS(cnt_out_int, rco_int, clock,reset) BEGIN
(reset ='1') THEN rco_int <='1'; ELSIF rising_edge(clock) THEN ((cnt_out_int "11111111") (cnt_out_int ="00000000")) THEN rco_int '1'; ELSE rco_int <='0'; PROCESS;
Logic Generate ouput.
PROCESS (clock,rco_int,reset) BEGIN (reset '1') THEN pwm_int <='0'; ELSIF rising_edge(rco_int) THEN pwm_int NOT(pwm_int); ELSE pwm_int pwm_int; PROCESS; pwm_int;
arch_pwm;
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User_pkg_inc_dec.vhd
LIBRARY IEEE; IEEE.STD_LOGIC_1164.ALL;
PACKAGE user_pkg function INC(X: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; function DEC(X: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; user_pkg
PACKAGE BODY user_pkg function INC(X: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR variable STD_LOGIC_VECTOR(X'LENGTH downto begin XV'HIGH LOOP XV(I) then XV(I) '1'; exit; else XV(I) '0'; loop;
return INC;
function DEC(X: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR variable STD_LOGIC_VECTOR(X'LENGTH downto begin XV'HIGH LOOP XV(I) then XV(I) '0'; exit; else XV(I) '1'; loop;
return DEC;
user_pkg;
Pulse Width Modulation
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Pulse Width Modulation
Post-layout Testbench
pwm_posttb.vhd Post-layout Testbench File
Design: pwm_fpga Program: Figaro Version: Atmel (patch level applied) Vendor: Atmel Created: 2001 11:45:56
library IEEE; IEEE.STD_LOGIC_1164.all;
IEEE.VITAL_timing.all; library AT40K; AT40K.VCOMPONENTS.all; entity post_test_bench post_test_bench; architecture arch_test_bench post_test_bench
component pwm_fpga port clock STD_LOGIC '0'; reset STD_LOGIC '0'; Data_value STD_LOGIC_VECTOR(7 downto "00000000"; STD_LOGIC component;
signal sig_pwm: STD_LOGIC; signal sig_reset: STD_LOGIC; signal sig_Data_value: STD_LOGIC_VECTOR(7 downto signal sig_clock: STD_LOGIC; signal STD_LOGIC '1'; signal zero STD_LOGIC '0'; shared variable ENDSIM: boolean:=false; constant clk_period:TIME:=200
BEGIN
clk_gen: process begin ENDSIM FALSE THEN sig_clock '1'; wait clk_period/2; sig_clock '0';
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wait clk_period/2; else wait; process; inst_pwm_fpga:pwm_fpga port clock sig_clock, reset sig_reset, Data_value sig_Data_value, sig_pwm
stimulus_process: PROCESS
BEGIN sig_reset '1'; wait sig_reset '0'; sig_data_value "11000000"; wait sig_data_value "10000000"; wait sig_data_value "01000000"; wait sig_data_value "10000000";
wait;
PROCESS stimulus_process; arch_test_bench;
Pulse Width Modulation
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Atmel Corporation 2001. Atmel Corporation makes warranty products, other than those expressly contained Company's standard warranty which detailed Atmel's Terms Conditions located Company's site. Company assumes responsibility errors which appear this document, reserves right change devices specifications detailed herein time without notice, does make commitment update information contained herein. licenses patents other intellectual property Atmel granted Company connection with sale Atmel products, expressly implication. Atmel's products authorized critical components life support devices systems. Atmel registered trademark Atmel. System Designerand FPSLICare trademarks Atmel. Leonardo ModelSim registered trademarks Mentor Graphics Corporation. LeonardoSpectrum trademark Mentor Graphics Corporation. Other terms product names trademarks others.
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Pulse Width Modulation (PWM) technique provide logic logic controlled

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