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CMOS ASIC
Converting FPGAs PLDs Atmel Gate Arrays
Atmel only companies that designs manufactures field programmable gate arrays (FPGAs), programmable logic devices (PLDs) high performance gate arrays. Atmel offers seamless, direct conversion path designs implemented most PLDs FPGAs gate array families. potential benefits system designer such capability fourfold: Component cost savings. Atmel's conversion process will convert single FPGA into lower cost gate array that pin-for-pin compatible replacement. Board space savings. Atmel converts true gate array, hardwired FPGA/PLD. Multiple FPGAs PLDs converted consolidated into single gate array, reducing system component count providing even more cost savings. Enhanced performance. Conversion gate array grants designer access macrocells functions contained cell library. Included higher order logic functions, inclusion SRAM, other buffers testability improvement circuitry that cannot realized FPGA PLD. Gate array routing schemes allow greater degree flexibility optimize timing performance logic area. Reduction design cycle time. ASIC design prototyped using programmable logic migrated gate array production without time cost re-design. cases, Atmel uses existing FPGA design database that little additional engineering effort required from customer. This application note discusses some factors consider when deciding convert, describes conversion process, details required information selected FPGA products.
FPGA/PLD Gate Array Conversion Application Note
Converting FPGAs PLDs Atmel Gate Arrays
0145D
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ATL50 Array Organization 0.5µm CMOS
Device Number
ATL50/4 ATL50/15 ATL50/25 ATL50/40 ATL50/60 ATL50/85 ATL50/110 ATL50/150 ATL50/200 ATL50/235 ATL50/300 ATL50/435 ATL50/550 ATL50/700 ATL60/870 ATL60/1100
Gates
4,000 15,000 25,000 38,000 58,000 86,000 110,000 149,000 195,000 232,000 301,000 430,000 545,000 693,000 870,000 1,119,000
Routable Gates
3,000 10,000 16,900 25,400 34,600 51,900 65,900 89,300 116,900 139,500 181,000 260,000 288,000 363,000 456,000 590,000
Count
Pins
Gate Speed
Notes: Nominal 2-input NAND gate with volts.
ATL60 Array Organization 0.6µm CMOS
Device Number
ATL60/4 ATL60/15 ATL60/25 ATL60/40 ATL60/60 ATL60/85 ATL60/110 ATL60/150 ATL60/200 ATL60/235 ATL60/300 ATL60/435 ATL60/550 ATL60/700 ATL60/870 ATL60/1100
Gates
4,000 15,000 25,000 38,000 58,000 86,000 110,000 149,000 195,000 232,000 301,000 430,000 545,000 693,000 870,000 1,119,000
Routable Gates
3,000 10,000 16,900 25,400 34,600 51,900 65,900 89,300 116,900 139,500 181,000 260,000 288,000 363,000 456,000 590,000
Count
Pins
Gate(1) Speed
Notes: Nominal input NAND gate with volts.
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ATLS60 Array Organization
Device Number ATLS60/80 ATLS60/100 ATLS60/120 ATLS60/144 ATLS60/160 ATLS60/208 ATLS60/225 ATLS60/256
Note:
Gates 12,500 20,400 30,200 44,600 55,300 96,500 113,500 148,200
Routable Gates 8,000 13,000 17,500 26,000 32,500 57,000 67,500 88,000
Count
Pins
Gate(1) Speed
Nominal input NAND Gate with
Programmable Logic Gate Array
Programmable logic devices have enjoyed tremendous popularity growth over last several years, primarily because user saves both time money. Designers work with multiple design tools that inexpensive platforms. Designs implemented hours modified easily, allowing system performance evaluation same week. This instant feedback allows designers validate system operation rectify errors without additional expense. Programmable logic devices provide ideal solution moderate production volumes fast prototyping more complex logic designs. volumes increase, however, programmable devices become prohibitively expensive. Gate arrays provide efficient implementation design. They offer superior performance, higher density, lower cost-per-gate production volumes when compared programmable logic devices. Design tools that support gate arrays typically more comprehensive expensive than FPGA/PLD design tools. However, many ASIC design platforms support FPGA design. ability simulate both programmable device gate array same design environment allows designer compare verify conversion. However, while gate array prototypes delivered days weeks, that still much longer period than verification cycle programmable logic device. Gate array designs typically require nonrecurring expense design implementation, design revisions require additional time expense.
Convert?
There four instances when converting from programmable logic device gate array offers user direct benefit. Save Money High Volumes. cost year's supply programmable devices approximates cost nonrecurring expense plus initial year's supply gate array device, serious consideration should given conversion. After nonrecurring expense amortized, cost savings become even more dramatic. Time Market Versus Cost Reduction. Using programmable device logic verification prototyping then converting gate array gives designer best both worlds fast, accurate design cycle cost component production. Higher Performance. Gate arrays have lower standby operating current, plus offer greater speed than FPGA/PLD. designer also greater selection buffer types, drive currents, wide selection higher order logic memory (SRAM) functions. Integration. Converting several FPGAs PLDs consolidating logic into single gate array uses less printed circuit board space, reduces component count, consumes less power, improves reliability system.
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Converting FPGAs/PLDs
Atmel's conversion process designed minimize amount engineering support required from system designers, provided requisite design database Figure FPGA/PLD Gate Array Conversion received. inputs required vary depending original manufacturer FPGA/PLD. Figure outlines conversion process flow.
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first step toward meeting Data Acceptance (DA) submission design database Atmel. required elements present, design database quickly accepted. Frequently issues arise with format vectors another element) with missing items which require some work done meet Because Atmel never certain what type database will received from customers, schedules design starting point. other words, clock starts once been met. Once Atmel database acceptance been met, original design converted into equivalent netlist using Atmel cell library Synopsys. Synopsys tools read variety formats, including preferred formats EDIF Verilog. Figure outlines process which synopsys converts FPGA netlist into Verilog-XLformat. database input proprietary Atmel mapping file translation into Atmel cells. When design mapped entirety, Verilog netlist Atmel cells produced. equivalent netlist ensures that both functionality timing design match original. Using this technique, almost FPGA/PLD design converted gate array.
Figure FPGA Conversion
FPGA Netlist (EDIF) Synopsys
Verilog Netlist
Mapping File
Hierarchical Verilog Netlist
Synopsys Flattened Verilog Netlist
Verilog Netlist Atmel Cells
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original test vectors also converted used verify gate array design. Good functional vectors must provided developed. This important because functional test vectors verification vehicle gate array design. final approval vectors used falls upon original designer; better served produce verify test vectors prior database submission than attempt reconstruct them after fact. vectors must same five groups (Input, Output, Tri-state, Bi-directional, Enable) have stated purpose. Outputs sampled once clock cycle cycle point. Test vectors must include wafer probe speed" final test. speed" with certain critical paths identified testing speed". Test vectors must pass Atmel's Test Vector Checker (tvc), tool provided with libraries verify format vector set. Design data base formats, simulation/test vector formats, specifications, documentation requirements listed below.
Documentation
Full hierarchical schematics Clock tree reset diagram Timing diagrams showing relationship clocks data applied valid outputs After design been converted verified functional performance, optimization process begins. design optimized match timing performance original FPGA/PLD design meet performance goals. Additional logic functions memory added gate array well. Before physical design chip begins, joint Preliminary Design Review held with Atmel customer approve results converted design. From this point design process identical that traditionally designed gate array. design physically placed routed gate array verified electrical design rules. Atmel uses Cadence's Verilog-XL golden simulator. Atmel guarantees performance equal better than that predicted Verilog-XL post route simulation. Back annotation data extracted from actual layout incorporated into post-route functional timing simulation. Minor layout modifications required meet timing specification. Final Design Review held approve post-route simulation data. After customer approval, design released mask generation prototyping. Prototypes delivered little three weeks production units short weeks after customer approval prototypes. Atmel guarantees gate array will pin-for-pin compatible replacement FPGA/PLD. Tables list recommended Atmel gate arrays conversion from various Actel, Altera, Xilinx, Cypress, Latticeprogrammable devices.
Required Database
Design Database Format EDIF 2.0.0 Synopsys files Verilog structural netlist Xilinx .xnf files source cell library Actel FPGA Altera FPGA/PLD Atmel FPGA Xilinx FPGA Other
Simulation/Test Vector Format
ALTERA Format ASCII Tabular Format COMPASS Tabular Trace Format ORCAD Format Quicksim Logfile Format Quicksim List Format Verilog Format VIEWlogic Tabular Format VLAIF Tabular Format
Gate Array Implementation
After database acceptance, design database converted into equivalent netlist primitive cells from Atmel's gate array library. vectors from original FPGA design also converted used functional simulation vectors validate gate array netlist. these vectors used perform timing simulation form core gate array tester program, vitally important that accurate complete vector provided. After FPGA databases have been converted validated, additional circuitry, such memory blocks, testability improvement elements, higher order logic functions, incorporated into netlist. optimization that necessary match timing improve performance performed this point
Specifications
Operating conditions voltage temperature System loading requirements Operating clock speed number clocks definition including enable Tri-stateand bi-directional buffers Identification critical paths Definition asynchronous behavior
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well. this point, boundary internal scan added ATPG vectors generated. Preliminary Design Review then held with customer review approve results design conversion. Preliminary Design Review (PDR) following items reviewed PDR: Confirm Netlist Checker (v3) Test Vector Checker (tvc) files correct buffer listing bonding diagram Preliminary testability compiler report Route clock tree analysis worst case best case delay Verilog simulation at-speed -nominal, worst case, best case (with timing violations) Review critical path information (tSU, tHOLD, tPD) -Verilog Veritime estimates electrical specifications Electromigration calculation Final Design Review (FDR) Beyond this point, design process follows that traditionally designed gate array. cells placed routed, post-route simulation performed, checks performed verify conformance with electrical design rules, confirm Logic Versus Schematic (LVS) correct. held with customer review approve post route data, authorize mask making prototype fabrication. last joint review between Atmel customer before committing prototypes. Prior this meeting, both Atmel customer will have reviewed post-route Verilog-XL simulation incorporating back annotation data. customer receive back annotation data complete post-route simulation their systems. Atmel guarantees silicon performance equal better than that predicted post-route Verilog-XL simulations. items reviewed follows: Updates cell mapping timing any) Post-route netlist check (v3) -post-route netlist changes Post-route timing simulation specification -review clock timing speed -clock skew required) -listing timing warnings with explanation Static path analysis specified) Electromigration calculation
Bonding diagrams list -bond plot LVS/DRC/ERC Prototype Delivery Atmel will deliver prototypes ceramic TQFP packages customer. units verify functionality electrical performance gate array. Synthesis from Hardware Description Language (HDL) There been increase HDLs design FPGAs PLDs more design platforms offer this capability. most popular languages VHDL Verilog-HDL. Using logic synthesis technique, behavioral level description FPGA mapped into functionally equivalent gate array netlist. Both hardware description languages supported Synopsys Design Compiler. This FPGA/PLD gate array conversion methodology requires least amount data conversion allows flexibility incorporate such features memory, testability, higher order logic functions into gate array. This technique also effective when need consolidate several FPGA designs into gate array exists. Synthesis from offers most efficient utilization gate array, expense timing matching. Should user require them, VHDL descriptions converted FPGAs PLDs, well gate array implementation, provided exporting netlists through Synopsys. Testability Improvement Automatic Test Pattern Generation incorporation testability improvement circuitry into ASIC design becomes more important density design increases. same said conversion consolidation large numbers dense FPGAs PLDs into gate array. insertion scan paths within ASIC testing ATPG provide easy means screening manufacturing-related defects during testing, with relatively small silicon usage penalty. Using ATPG only supplement functional test vectors, replacement. process consists replacing existing flip-flops with scan flip-flops connecting them form scan chains. input output must identified each scan chain. general, scan chains should exceed flip-flops length. Thus, design with flip-flops, input pins their corresponding output pins must identified. Existing pins multiplexed this design limited. Additional pins required Test Enable (TE) signal Test Mode (TM) signal. used control flip-flops, placing them either normal mode scan mode.
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required bypass violations testability guidelines, example which would gated clocks. During testing, flip-flops scan chains must toggle same clock. gated clocks exist design, logic must designed that bypasses this gating when Test Mode active. Since Test Mode active only during ATPG test, basic function design unaffected. Synopsys Test Compiler Guidelines table outlines other testability rules suggested workarounds utilizing Test Mode signal. When test guidelines
followed, testability insertion vector generation easily accomplished. Past experience shown extremely high fault coverage 99%) with small ATPG vector sets. these rules followed closely, incorporating scan ATPG require several weeks. highly recommended that FPGA designed using rules Table customer intends someday convert gate array scan/ATPG.
Synopsys Test Compiler Guidelines
Testability Rule Synchronous Design cross coupled gates unregistered feedback Single Edge Clocking Effects Infraction Associated logic untestable Work around Break feedback path with test mode
Clocked device allowed scan chain reduced fault Clocked device allowed scan chain reduced fault coverage allowed scan chain, reduced fault coverage
test mode, create single edge clocking with inverters MUXs data disable flip-flops instead clock enables, disable gating test mode alternate test methods, force latches transparent mode with test mode Reset OR'd with test mode
Clock Gating
Latches
Single External Reset asynchronous resets presets generated chip combinational logic reset path Internal Tri-state Buses
allowed scan chain, reduced fault coverage
Reduced fault coverage, possible Tri-state contention during scan test
MUXs gates, insert gating controls prevent contention
Direct Connections
Dynamic Hazard
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Table Xilinx® FPGA/CPLD/Atmel Gate Array Cross Reference Target Atmel Gate Array(1) ATLS60 Series ATLS60/80 ATLS60/80 ATLS60/100 ATLS60/80 ATLS60/100 ATLS60/120 ATLS60/144 ATLS60/160 ATLS60/225 ATLS60/256 ATL60 Series ATL60/4 ATL60/15 ATL60/15 ATL60/25 ATL60/15 ATL60/25 ATL60/40 ATL60/60 ATL60/85 ATL60/110 ATL60/235 ATL60/300 ATL60/435 ATL60/550 ATLS60/80 ATLS60/80 ATLS60/100 ATLS60/100 ATLS60/120 ATLS60/120 ATLS60/144 ATLS60/144 ATLS60/160 ATLS60/160 ATLS60/208 ATLS60/80 ATLS60/100 ATLS60/120 ATLS60/120 ATLS60/144 ATLS60/144 ATLS60/160 ATLS60/160 ATLS60/208 ATLS60/160 ATLS60/208 ATLS60/208 ATLS60/256 ATL60/15 ATL60/25 ATL60/25 ATL60/40 ATL60/40 ATL60/60 ATL60/60 ATL60/85 ATL60/85 ATL60/110 ATL60/150 ATL60/25 ATL60/40 ATL60/60 ATL60/60 ATL60/85 ATL60/85 ATL60/110 ATL60/110 ATL60/150 ATL60/150 ATL60/200 ATL60/235 ATL60/300 ATL50 ATL50/4 ATL50/15 ATL50/15 ATL50/25 ATL50/15 ATL50/25 ATL50/40 ATL50/60 ATL50/85 ATL50/110 ATL50/235 ATL50/300 ATL50/435 ATL50/550 ATL50/15 ATL50/25 ATL50/25 ATL50/40 ATL50/40 ATL50/60 ATL50/60 ATL50/85 ATL50/85 ATL50/110 ATL50/150 ATL50/25 ATL50/40 ATL50/60 ATL50/60 ATL50/85 ATL50/85 ATL50/110 ATL50/110 ATL50/150 ATL50/150 ATL50/200 ATL50/235 ATL50/300
Xilinx® FPGA XC2064 XC2064L XC2018 XC2018L XC3020A XC3020L XC3030A XC3030L XC3042A XC3042L XC3064A XC3064L XC3090A XC30090L XC3120A XC3130A XC3142A XC3142L XC3164A XC3190A XC3190L XC3195A XC4003E XC4005E XC4005L XC4006E XC4008E XC4010E XC4010L XC4013E XC4013L XC4020E
Note:
Equivalent Usable Gates 1000 1500 1500 2000 3000 5000 6000 1500 2000 3000 4500 6000 7500 3000 5000 6000 8000 10000 13000 20000
Pins
Target array dependent number pins used, pinout.
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Table (continued). Xilinx® FPGA/CPLD/Atmel Gate Array Cross Reference Target Atmel Gate Array(1) ATLS60 Series ATLS60/256(2) ATLS60/256(2) ATL60 Series ATL60/300 ATL60/435 ATL60/300 ATL60/435 ATL60/300 ATL60/435 ATL60/435 ATL60/550 ATL60/550 ATL60/700 ATL60/700 ATL60/870 ATLS60/80 ATLS60/100 ATLS60/120 ATLS60/144 ATLS60/144 ATLS60/160 ATLS60/160 ATLS60/208 ATLS60/225 ATLS60/256 ATLS60/160 ATLS60/208 ATL560/256(2) ATL60/25 ATL60/40 ATL60/60 ATL60/85 ATL60/85 ATL60/110 ATL60/150 ATL60/200 ATL60/235 ATL60/300 ATL60/150 ATL60/200 ATL60/300 ATL60/435 ATL60/700 ATL60/870 ATL60/1100(3) ATL50 ATL50/300 ATL50/435 ATL50/300 ATL50/435 ATL50/300 ATL50/435 ATL50/435 ATL50/550 ATL50/550 ATL50/700 ATL50/700 ATL50/870 ATL50/25 ATL50/40 ATL50/60 ATL50/85 ATL50/85 ATL50/110 ATL50/150 ATL50/200 ATL50/235 ATL50/300 ATL50/150 ATL50/200 ATL50/300 ATL50/435 ATL50/700 ATL50/870 ATL50/1100(3)
Xilinx® FPGA XC4025E XC4028EX XC4028LX XC4036EX XC4036LX XC4044EX XC4044LX XC4052XL XC4062XL XC5202/L XC5204 XC5206/L XC5210 XC5215/L XC6209 XC6216 XC6236 XC6264
Note:
Equivalent Usable Gates 25000 28000 36000 44000 52000 62000 3000 6000 10000 16000 23000 13000 24000 55000 100000
Pins
Target array dependent number pins used, pinout. ATLS60/256 pins will accommodate devices with more than pins. ATL60/1100 pins will only accommodate devices with more than pins.
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Table (continued). Xilinx® FPGA/CPLD/Atmel Gate Array Cross Reference Target Atmel Gate Array(2) ATLS60 Series ATLS60/80 ATLS60/80 ATLS60/80 ATLS60/80 ATLS60/80 ATLS60/80 ATLS60/80 ATLS60/100 ATLS60/120 ATLS60/144 ATLS60/80 ATLS60/80 ATLS60/80 ATLS60/100 ATLS60/120 ATLS60/100 ATLS60/120 ATLS60/144 ATLS60/120 ATLS60/144 ATLS60/160 ATLS60/208 ATLS60/120 ATLS60/144 ATLS60/160 ATLS60/208 ATLS60/160 ATLS60/208 ATLS60/208 ATLS60/225 ATLS60/256 ATLS60/208 ATLS60/225 ATLS60/256 ATL60 Series ATL60/4 ATL60/4 ATL60/15 ATL60/4 ATL60/4 ATL60/4 ATL60/15 ATL60/4 ATL60/15 ATL60/25 ATL60/40 ATL60/60 ATL60/85 ATL60/4 ATL60/15 ATL60/25 ATL60/15 ATL60/25 ATL60/40 ATL60/60 ATL60/25 ATL60/40 ATL60/60 ATL60/85 ATL60/60 ATL60/85 ATL60/110 ATL60/150 ATL60/60 ATL60/85 ATL60/110 ATL60/150 ATL60/110 ATL60/150 ATL60/200 ATL60/235 ATL60/300 ATL60/235 ATL60/300 ATL50 ATL50/4 ATL50/4 ATL50/15 ATL50/4 ATL50/4 ATL50/4 ATL50/15 ATL50/4 ATL50/15 ATL50/25 ATL50/40 ATL50/60 ATL50/85 ATL50/4 ATL50/15 ATL50/25 ATL50/15 ATL50/25 ATL50/40 ATL50/60 ATL50/25 ATL50/40 ATL50/60 ATL50/85 ATL50/60 ATL50/85 ATL50/110 ATL50/150 ATL50/60 ATL50/85 ATL50/110 ATL50/150 ATL50/110 ATL50/150 ATL50/200 ATL50/235 ATL50/300 ATL50/235 ATL50/300
Xilinx® CPLD XC7236A XC7272A XC7318 XC7336 XC7354 XC7372 XC73108 XC73144 XC9536 XC9572 XC95108
Equivalent Usable Gates(1)
Pins
XC95144
XC95180
133,
XC95216
133,
XC95288
168,
XC95432
XC95576
Note:
Equivalent usable gate data available. Target array dependent number pins used, pinout.
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Table Altera FPGA/PLD/Atmel Gate Array Cross Reference Target Atmel Gate Array(1) ATLS60 Series ATLS60/120 ATLS60/144 ATLS60/160 ATLS60/208 ATLS60/225 ATLS60/256 ATLS60/160 ATLS60/208 ATL60 Series ATL60/60 ATL60/85 ATL60/150 ATL60/200 ATL60/235 ATL60/300 ATL60/150 ATL60/200 ATL60/435 ATL60/550 ATL60/550 ATL60/700 ATL60/700 ATL60/870 ATLS60/80 ATLS60/100 ATLS60/120 ATLS60/144 ATLS60/144 ATLS60/160 ATLS60/160 ATLS60/208 ATLS60/208 ATLS60/225 ATL60/25 ATL60/40 ATL60/60 ATL60/85 ATL60/85 ATL60/110 ATL60/150 ATL60/200 ATL60/200 ATL60/235 ATL50 ATL50/60 ATL50/85 ATL50/150 ATL50/200 ATL50/235 ATL50/300 ATL50/150 ATL50/200 ATL50/435 ATL50/550 ATL50/550 ATL50/700 ATL50/700 ATL50/870 ATL50/25 ATL50/40 ATL50/60 ATL50/85 ATL50/85 ATL50/110 ATL50/150 ATL50/200 ATL50/200 ATL50/235
Altera FPGA EPF10K10 EPF10K20 EPF10K30 Flex 10KEPF10K40 EPF10K50 EPF10K70 EPF10K100 EPF8282A EPF8282AV EPF8452 EPF8452A Flex 8000EPF8636A EPF8820 EPF8820A EPF81188 EPF81188A EPF81500 EPF81500A
Note:
Equivalent Usable Gates 31000 63000 69000 93000 116000 118000 158000 2500 4000 6000 8000 12000 16000
Pins
Target array dependent number pins used, pinout.
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Table (continued). Altera FPGA/PLD/Atmel Gate Array Cross Reference Target Atmel Gate Array(1) ATLS60 Series ATLS60/160 ATLS60/208 ATLS60/160 ATLS60/208 ATLS60/208 ATLS60/208 ATLS60/225 ATLS60/80 ATL60 Series ATL60/110 ATL60/150 ATL60/150 ATL60/200 ATL60/200 ATL60/200 ATL60/235 ATL60/4 ATL50 ATL50/110 ATL50/150 ATL50/150 ATL50/200 ATL50/200 ATL50/200 ATL50/235 ATL50/4
Altera EPM9320 EPM9400 9000EPM9480 EPM9560 EPM7032 EPM7032V EPM7032S EPM7064 EPM7064S 7000Max 7000SEPM7096 EPM7096S EPM7128E EPM7128S EPM7160E EPM7160S EPM7192E EPM7192S EPM7256E EPM7256S EPM5032 EPM5064 5000EPM5128 EPM5128A EPM5130 RPM5192 EP610 ClassicEP910 EP1810
Note:
Equivalent Usable Gates 6000 8000 10000 12000
Pins
1250 1800 2500 3200 3750 5000 1250 2500 2500 3200
ATLS60/80 ATLS60/80 ATLS60/100 ATLS60/100 ATLS60/120 ATLS60/100 ATLS60/120 ATLS60/120 ATLS60/144 ATLS60/160 ATLS60/208 ATLS60/80 ATLS60/80 ATLS60/80 ATLS60/100 ATLS60/120 ATLS60/100 ATLS60/120 ATLS60/80 ATLS60/80 ATLS60/80
ATL60/15 ATL60/25 ATL60/25 ATL60/40 ATL60/60 ATL60/40 ATL60/60 ATL60/60 ATL60/85 ATL60/110 ATL60/150 ATL60/4 ATL60/4 ATL60/15 ATL60/40 ATL60/60 ATL60/40 ATL60/60 ATL60/4 ATL60/4 ATL60/15 ATL60/25
ATL50/15 ATL50/25 ATL50/25 ATL50/40 ATL50/60 ATL50/40 ATL50/60 ATL50/60 ATL50/85 ATL50/110 ATL50/150 ATL50/4 ATL50/4 ATL50/15 ATL50/40 ATL50/60 ATL50/40 ATL50/60 ATL50/4 ATL50/4 ATL50/15 ATL50/25
Target array dependent number pins used, pinout.
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Table Actel FPGA/Atmel Gate Array Cross Reference Target Atmel Gate Array(1) ATLS60 Series ATLS60/80 ATLS60/100 ATLS60/100 ATLS60/120 ATLS60/120 ATLS60/144 ATLS60/144 ATLS60/160 ATLS60/160 ATLS60/160 ATLS60/208 ATLS60/208 ATLS60/225 ATLS60/256(2) ATL60 Series ATL60/25 ATL60/40 ATL60/40 ATL60/60 ATL60/60 ATL60/85 ATL60/85 ATL60/110 ATL60/110 ATL60/150 ATL60/200 ATL60/235 ATL60/300 ATL60/435 ATL60/300 ATL60/435 ATLS60/80 ATLS60/80 ATLS60/80 ATLS60/100 ATLS60/100 ATLS60/120 ATLS60/144 ATLS60/160 ATLS60/80 ATLS60/100 ATLS60/100 ATLS60/120 ATLS60/144 ATLS60/160 ATLS60/160 ATLS60/208 ATLS60/225 ATLS60/256 ATL60/4 ATL60/15 ATL60/15 ATL60/25 ATL60/25 ATL60/40 ATL60/40 ATL60/60 ATL60/85 ATL60/110 ATL60/25 ATL60/40 ATL60/40 ATL60/60 ATL60/85 ATL60/110 ATL60/110 ATL60/150 ATL60/235 ATL60/300 ATL50 ATL50/25 ATL50/40 ATL50/40 ATL50/60 ATL50/60 ATL50/85 ATL50/85 ATL50/110 ATL50/110 ATL50/150 ATL50/200 ATL50/235 ATL50/300 ATL50/435 ATL50/300 ATL50/435 ATL50/4 ATL50/15 ATL50/15 ATL50/25 ATL50/25 ATL50/40 ATL50/40 ATL50/60 ATL50/85 ATL50/110 ATL50/25 ATL50/40 ATL50/40 ATL50/60 ATL50/85 ATL50/110 ATL50/110 ATL50/150 ATL50/235 ATL50/300
Actel FPGA A1225XL A1240XL A3265DX Integrator Series 1200XL 3200DX A1280XL A32100DX A32140DX A32200DX A32300DX A32400DX A1010B A10V10B A1020B A10V20B A1225A A1240A A1280A A1415 A1425 A1440 A1460 A14100
Equivalent Usable Gates 2500 4000 6500 8000 10000 14000 20000 30000 40000 1200 2000 2500 4000 8000 1500 2500 4000 6000 10000
Pins
Accelerator Series
Notes: Target array dependent number pins used, pinout. ATLS60/256 pins will accommodate devices with more than pins.
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Table (continued). Actel FPGA/Atmel Gate Array Cross Reference Target Atmel Gate Array(1) ATLS60 Series ATLS60/144 ATLS60/160 ATLS60/160 ATLS60/208 ATLS60/225 ATLS60/256 ATL60 Series ATL60/85 ATL60/110 ATL60/110 ATL60/150 ATL60/235 ATL60/300 ATL50 ATL50/85 ATL50/110 ATL50/110 ATL50/150 ATL50/235 ATL50/300
Actel FPGA A1440BP ACT3 Compliant A1460BP A14100BP
Note:
Equivalent Usable Gates 4000 6000 10000
Pins
Target array dependent number pins used, pinout.
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Table LatticePLD/Atmel Gate Array Cross Reference Equivalent Usable Gates (PLD Gates) 1016E 1024 ispLSI 1000/E
LatticePLD
Pins
Target Atmel Gate Array(1) ATLS60 Series ATLS60/80 ATLS60/80 ATLS60/80 ATLS60/100 ATLS60/120 ATLS60/80 ATLS60/80 ATLS60/100 ATLS60/120 ATLS60/144 ATLS60/160 ATLS60/208 ATLS60/160 ATLS60/208 ATLS60/120 ATLS60/144 ATLS60/256(2) ATLS60/160 ATLS60/208 ATL60 Series ATL60/4 ATL60/4 ATL60/15 ATL60/15 ATL60/25 ATL60/40 ATL60/60 ATL60/4 ATL60/15 ATL60/25 ATL60/40 ATL60/60 ATL60/85 ATL60/110 ATL60/150 ATL60/150 ATL60/200 ATL60/60 ATL60/85 ATL60/300 ATL60/435 ATL60/110 ATL60/150 ATL50 ATL50/4 ATL50/4 ATL50/15 ATL50/15 ATL50/25 ATL50/40 ATL50/60 ATL50/4 ATL50/15 ATL50/25 ATL50/40 ATL50/60 ATL50/85 ATL50/110 ATL50/150 ATL50/150 ATL50/200 ATL50/60 ATL50/85 ATL50/300 ATL50/435 ATL50/110 ATL50/150
2000 4000 6000 8000 1000 2000 4000 6000 7000 9000 11000 12000 14000
1032E 1048E 2032 2032LV
ispLSI® 2000 ispLSI® 2000LV
2064 2064LV 2096 2096LV 2128 2128LV 3160 3192
ispLSI® 3000
3256 3256E 3320
Notes: Target array dependent number pins used, pinout. ATLS60/256 pins will accommodate devices with more than pins.
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Table Cypress FPGA/PLD/Atmel Gate Array Cross Reference Target Atmel Gate Array(1) ATLS60 Series ATLS60/120 ATLS60/144 ATLS60/160 ATLS60/208 ATLS60/160 ATLS60/208 ATLS60/225 ATLS60/256
ATLS60/256
Cypress FPGA CY7C38003 CY7C338003 CY7C38005 CY7C338005 CY7C38007 CY7C38007 Ulta38000CY7C38009 CY7C338009 CY7C380012 CY7C3380012 CY7C380016 CY7C3380016 CY7C380020 CY7C3380020 CY7C381P CY7C3381A CY7C382P CY7C3382A CY7C383A CY7C3383A pASIC380 CY7C384A CY7C3384A CY7C385P CY7C3385A CY7C386P CY7C3386A CY7C387P CY7C3387P CY7C388P CY7C3388P
Note:
Equivalent Usable Gates 3000 5000 7000 9000 12000
Pins
ATL60 Series ATL60/60 ATL60/85 ATL60/110 ATL60/150 ATL60/150 ATL60/200 ATL60/235 ATL60/300 ATL60/300 ATL60/435 ATL60/435 ATL60/550 ATL60/550 ATL60/700
ATL50 ATL50/60 ATL50/85 ATL50/110 ATL50/150 ATL50/150 ATL50/200 ATL50/235 ATL50/300 ATL50/300 ATL50/435 ATL50/435 ATL50/550 ATL50/550 ATL50/700 ATL50/4 ATL50/4 ATL50/15 ATL50/4 ATL50/15 ATL50/25 ATL50/40 ATL50/25 ATL50/40 ATL50/60 ATL50/85 ATL50/60 ATL50/85 ATL50/110 ATL50/150
16000
20000
1000 1000 2000 2000 4000 4000 8000 8000
ATLS60/80 ATLS60/80 ATLS60/80 ATLS60/80 ATLS60/100 ATLS60/80 ATLS60/100 ATLS60/120 ATLS60/144 ATLS60/120 ATLS60/144 ATLS60/160 ATLS60/208
ATL60/4 ATL60/4 ATL60/15 ATL60/4 ATL60/15 ATL60/25 ATL60/40 ATL60/25 ATL60/40 ATL60/60 ATL60/85 ATL60/60 ATL60/85 ATL60/110 ATL60/150
Target array dependent number pins used, pinout. ATLS60/256 pins will accommodate devices with more than pins.
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Table (continued). Cypress FPGA/PLD/Atmel Gate Array Cross Reference Target Atmel Gate Array(2) ATLS60 Series ATLS60/80 ATLS60/120 ATLS60/144 ATLS60/120 ATLS60/144 ATLS60/160 ATLS60/208 ATLS60/160 ATLS60/208 ATLS60/160 ATLS60/208 ATLS60/160 ATLS60/208 ATLS60/160 ATLS60/208 ATLS60/225 ATLS60/256 ATLS60/225 ATLS60/256 ATLS60/80 ATLS60/80 ATLS60/80 ATLS60/80 ATLS60/120 ATLS60/144 ATLS60/80 ATLS60/80 ATLS60/80 ATLS60/80 ATLS60/120 ATLS60/144 ATL60 Series ATL60/15 ATL60/25 ATL60/60 ATL60/85 ATL60/60 ATL60/85 ATL60/110 ATL60/150 ATL60/110 ATL60/150 ATL60/150 ATL60/200 ATL60/150 ATL60/200 ATL60/150 ATL60/200 ATL60/235 ATL60/300 ATL60/235 ATL60/300 ATL60/4 ATL60/4 ATL60/15 ATL60/25 ATL60/15 ATL60/25 ATL60/60 ATL60/85 ATL60/4 ATL60/4 ATL60/15 ATL60/25 ATL60/15 ATL60/25 ATL60/60 ATL60/85 ATL50 ATL50/15 ATL50/25 ATL50/60 ATL50/85 ATL50/60 ATL50/85 ATL50/110 ATL50/150 ATL50/110 ATL50/150 ATL50/150 ATL50/200 ATL50/150 ATL50/200 ATL50/150 ATL50/200 ATL50/235 ATL50/300 ATL50/235 ATL50/30 ATL50/4 ATL50/4 ATL50/15 ATL50/25 ATL50/15 ATL50/25 ATL50/60 ATL50/85 ATL50/4 ATL50/4 ATL50/15 ATL50/25 ATL50/15 ATL50/25 ATL50/60 ATL50/85
Cypress 39192 (84) (160) 39256 (160) (208) 39320 (208) (240) 39384 (240) 39448 (240) (304) 39512 (304) Flash370374 371i 372i 373i(84/100) Flash370i374i(84/100) 375i
Note:
Equivalent Usable Gates(1)
Pins
Ultra3900(3)
Equivalent usable gate data available. Target array dependent number pins used, pinout. Numbers given parenthesis indicates optional counts.
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Atmel FPGAs/PLDs Cross Reference
Table lists target Gate Arrays conversion Atmel FPGAs PLDs. Table Atmel FPGA/Atmel Gate Array Cross Reference Target Atmel Gate Array(1) ATLS60 Series ATLS60/80 ATLS60/80 ATLS60/80 ATLS60/80 ATLS60/100 ATLS60/120 ATLS60/120 ATLS60/144 ATLS60/100 ATLS60/120 ATLS60/208 ATLS60/225 ATL60 Series ATL60/4 ATL60/4 ATL50/4 ATL60/15 ATL60/4 ATL60/15 ATL60/40 ATL60/60 ATL60/60 ATL60/85 ATL60/40 ATL60/60 ATL60/200 ATL60/235 ATL50 ATL50/4 ATL50/4 ATL50/4 ATL50/15 ATL50/4 ATL50/15 ATL50/40 ATL50/60 ATL50/60 ATL50/85 ATL50/40 ATL50/60 ATL50/200 ATL50/235
Atmel PLD/FPGA ATF1500 ATV2500 ATV5000 ATV5100 AT6002 AT6003 FPGA AT6005 AT6010
Note:
Equivalent Usable Gates 1500 2500 5000 5100 2000-4000 3000-6000 5000-10000 10000-20000
Pins
Target array dependent number pins used, pinout.
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