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EE-176
Contributed Eric Yang
Technical notes using Analog Devices DSPs, processors development tools
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Hardware Design Checklist ADSP-TS101S TigerSHARC® Processors
July 2004
Introduction
This EE-Note discusses specific hardware issues when implementing system design that incorporates ADSP-TS101S TigerSHARC® processors. This document provided hardware engineers when designing systems. items provided this EE-Note apply ADSP-TS101S TigerSHARC embedded processors with core clocks.
Reset
Power-up reset: after power-up system, strap options stable, RESET must asserted (low) minimum followed de-asserted (high) pulse minimum SCLK cycles maximum SCLK cycles asserted (low) minimum SCLK cycles. Figure logic device required generate proper timing RESET signal. TRST must also asserted (low) during power-up ensure proper operation device.
Figure
Power-up Reset Waveform
Booting
EPROM used user's system boot TigerSHARC processor's, strap must pulled down with external resistor keep stable during reset. After that, will
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EPROM chip select signal. EPROM used, pull this with resistor directly VDD_IO. ADSP-TS101S processors have three boot modes EPROM, host, link port. Refer "ADSP-TS101S TigerSHARC Processor Boot Loader Kernels Operation (EE-174)" source code files under ".\Analog Devices\VisualDSP\Ts\ldr" learn whole process. Select modes boot TigerSHARC processors your system.
Clock
Derive SCLK LCLK from same clock source. system must work deterministically cycle-by-cycle, integer LCLK multiplication when setting LCLKRAT. Otherwise, non-integer multiplier will also fully functional perfectly acceptable. maximum LCLK/SCLK input jitter tolerance Refer IDT® (www.idt.com) Cypress® (www.cypress.com) site choose proper clock buffer (TurboClock1 RoboClock2). ADSP-TS101S processors cluster (and devices that interface ADSP-TS101S synchronous manner) should following guidelines. Provide single clock source each fan-out buffer. Never frequencies. Refer Figure
ence nput ence nput ence nput
sour equenci
sour sour
sour
sour
sour
Figure Using fan-out buffers
Good
Connections should point-to-point from zero-skew clock buffer output device clock input. Match trace lengths minimize skew. Figure
TurboClockis trademark IDT®. RoboClockis trademark Cypress®.
Hardware Design Checklist ADSP-TS101S TigerSHARC® Processors (EE-176)
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skew SHARC Sour SHARC
SHARC Synchr onous Host SDRAM Synchr onous Devi These ocks shoul engt shoul ched.
Figure
Clock distribution method
Power Supply
Note that analog supply (VDD_A) provides power clock generator PLLs. produce stable clock, systems must provide clean power supply power input VDD_A. Designers must critical attention bypassing VDD_A supply. Figure reference design filtering circuit. Place components close possible device.
10uH VSSA VSSA
Figure
Analog power supply filtering circuit reference design
required power-on sequence provide (and VDD_A) before VDD_IO. Ensure that proper DC/DC module chosen provide right voltage enough current core part TigerSHARC. Refer "Estimating Power ADSP-TS101S (EE-169)" learn method power dissipation calculation. Consider worst case. Place bypass caps bottom side board, close power pins possible. There several ways achieve this.
Hardware Design Checklist ADSP-TS101S TigerSHARC® Processors (EE-176)
10uH
Page
0.1uF low-inductance caps recommended bypass. 0.01uF 0.001uF capacitors also used with 0.1uF capacitors higher frequency filtering, provided their inductance small enough. some cases SPICEing power supply filtering characteristics necessary. blind vias from package balls create sufficient space capacitor placement. disadvantage this that blind vias more expensive that blind vias accessible scope probes. Part traces four quadrants chip four opposite directions, shown Figure resulting open horizontal vertical lanes placing capacitors size 0402 smaller. disadvantage that small capacitor packages difficult handle.
Figure
Bypass capacitors layout scheme
Enough bulk capacitors used prevent voltage vibration power supply plane caused great current variation. Several parallel electrolytic tantalum capacitors preferred order provide high capacitance ESR.
JTAG Port
multiprocessor system, separate buffers drive TCKs different TigerSHARC processors order monotonic rising edges these pins. detailed updated information, refer "Analog Devices JTAG Emulation Technical Reference(EE-68)". Ensure that there enough keep-out space around JTAG connector that JTAG easily plugged onto board. detailed updated information, refer "Analog Devices JTAG Emulation Technical Reference (EE-68)".
Hardware Design Checklist ADSP-TS101S TigerSHARC® Processors (EE-176)
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Strap Pins
Ensure that strap pins desired state during reset.
Signal
Description
EBOOT
EPROM boot. boot from EPROM immediately after reset (default) idle after reset wait external device boot through external port link port
IRQEN
Interrupt Enable. disable IRQ[3 interrupts level-sensitive after reset (default)
enable IRQ[3 interrupts edge-sensitive immediately after reset L2DIR Test Mode required setting during reset. reserved.
TMR0E
Test Mode required setting during reset. reserved.
Table
Strap pins definition
Cluster
single-processor "000". multiprocessor "000" "N-1", where number TigerSHARC processors same cluster (N=1, pins properly. there host cluster common data shared between host TigerSHARC processor, match endianess sides each other. Connect address proper way. Since TigerSHARC processor's addressing wordoriented most host processors' addressing byte-oriented, connect LS-bit TigerSHARC's address LS-bit host's address bus, instead, connect LSbit, regardless whether 32-bit 64-bit width applied. address data buses float several cycles during mastership transitions between TigerSHARC host. "Floating" means that these inputs driven source that DCbiased terminations present. necessary pull-up resistors there reliability issues worst-case power consumption these floating inputs negligible. Unconnected address pins require pull-up pull-down resistors avoid erroneous slave accesses, depending system. Unconnected data pins left floating. host memory width bits, multiprocessing must also bits.
Hardware Design Checklist ADSP-TS101S TigerSHARC® Processors (EE-176) Page
external wait state used, ensure that contention signal will caused. solve this problem, refer "ADSP-TS101 TigerSHARC Processor Hardware Reference". SDRAM connected cluster bus, address pins connection between these devices vary because different width memory size. Refer "ADSP-TS101 TigerSHARC Processor Hardware Reference". FLYBY write transaction used move data directly from memory, IOEN enable output buffer device. External slave devices de-assert wait states external memory accesses. ADSPTS101S de-assert wait states read accesses internal memory, does drive during slave writes. Therefore, external (approximately 10K) pull-up required. fly-by used, ensure that timing external memory device matched. designers want ZBT-SRAM their system, remember that only flow-through ZBTSRAMs connected gluelessly, pipelined ZBT-SRAMs. This because when TigerSHARC accesses cluster using pipelined protocol, write pipeline depth fixed same flow-through ZBT-SRAMs. write pipeline depth pipelined ZBT-SRAMs fixed which incompatible with TigerSHARC processors. multiprocessor system, there fewer than TigerSHARCs same cluster bus, de-assert unused (i.e., pull VDD_IO with resistor). great attention signal integrity cluster multiprocessor system. analysis must performed such case. Designers find ibis model file ADI's site.
Link Ports
Ensure that link port signals have same routing delay. buffers used, shown Figure ensure that buffers have almost same delay synchronization consideration, especially backplane cable connection used. buffers used, prevent contention LxDAT wires, buffers must disabled during reset, since LxDIRs three-stated when RESET asserted. buffers enabled LxDIRs three-stated, buffers both sides drive wires between them same time, potentially causing large current from VDD_IO ground. Because internal-to-internal supported ADSP-TS101S hardware, directly, connect unused link ports together copy memory through this loop-back using respective transmit receive link port channels. LxCLKIN pins should pulled VDD_IO prevent spurious noise from triggering link port transfers corrupting ADSP-TS101 memory. This corruption happen during time between reset signal deassertion disabling unused linkport/DMA channels boot kernel code application code because linkport/DMA receive channels enabled default regardless booting mode. only case which external pullups aren't needed when there link port connection between ADSP-TS101's that share common reset signal, because TS101 will drive these pins stable state right after reset.
Hardware Design Checklist ADSP-TS101S TigerSHARC® Processors (EE-176) Page
pull resistors 10Kohm, tests should performed find ideal value particular board. They must placed very closed device order avoid reflection glitches. cases, link port used boot, controls must disabled soon possible after boot avoid spurious transfers that corrupt memory.
LxCLKIN LxCLKOUT LxDAT Minimal link buffering LxCLKIN LxCLKOUT LxDAT LxDIR Buffered link using LxDIR
LxCLKIN LxCLKOUT LxDAT
LxCLKIN LxCLKOUT LxDAT LxDIR
Figure
Buffered link port configuration
Hardware Design Checklist ADSP-TS101S TigerSHARC® Processors (EE-176)
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Miscellaneous Items
Connect VREF, LCLK_N, SCLK_N reference voltage 1.5V±100mV. Figure shows possible filtering circuit.
Figure
VREF, SCLKN LCLKN filtering scheme
Since control impedance drive strength pins adjusted pull-up pull-down resistors CONTROLIMP[2:0] DS[2:0] pins, configure these pins most proper according result signal integrity analysis. analysis impossible, switches jumpers select between pull-ups pull-downs just populate resistors different ways obtain best signal integrity analysis impossible). Figure
VDD_I VDD_I
TS101S
NTRO NTRO NTRO
TS101S
NTRO NTRO NTRO
popul connect each
ches
Figure
Drive strength configuration methods
Hardware Design Checklist ADSP-TS101S TigerSHARC® Processors (EE-176)
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Internal pull-ups pull-downs weak relied external pull-ups pull-downs keep bi-directional input pins de-asserted state should these pins unused your system during transient time between drivers.
Unused Inputs
Unused Outputs
Pins that must connected
Pins
Handling Method
Pins
Handling Method
Pins
Addr31-0 Data63-0 /WRL /WRH /BRST /BR7-0 /BOFF /HBR /HBG /CPA /DPA /DMAR3-0 /MSSD /RAS /CAS SDCKE /SDWE FLAG3-0 /IRQ3-0 LxData7-0 LxCLKIN TDI2
(internal pull-up1) (internal pull-up1) (internal pull-up1) (internal pull-up1) ID7-1, ID7-1, ID7-1, (internal pull-up (internal pull-up (internal pull-up (internal pull-up1) (internal pull-up (internal pull-down1) (internal pull-up1) (internal pull-up)
/MS1-0 /MSH /BUSLOCK /FLYBY /IOEN /LDQM /HDQM /SDA10 /LxCLKOUT LxDIR /EMU2
LCLK_N LCLK_P LCLKRAT2-0 SCLK_N SCLK_P SCLKFREQ /RESET CONTROLIMP2-0 DS2-0 /BMS3 (Strap EBOOT) /BM3 (Strap IRQEN) TMR0E3 (Strap TM1) L2DIR3 (Strap TM2) VDD_A VDD_IO VREF VSS_A /TRST2 (must pulsed held after power
(internal pull-up) Connection. Pull-up VDD_IO through resistor required. Pull-down through resistor required.
That means there internal pull-up pull-down resistor (100K ±50%) this pin. more detailed information, refer EE-68. Refer Table
Table
Handling pins
Hardware Design Checklist ADSP-TS101S TigerSHARC® Processors (EE-176)
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According anomaly ADSP-TS101S anomaly list [3], LDQM HDQM pins have internal pull-downs instead pull-ups. want external pull-ups, require stronger pull-up resistors overcome internal pull-down resistors. SDCKE internal pull-up pull-down behavior different situations. want pull signal down externally stronger pull-down pull-down resistor overcome internal resistor. Connect LEDs unused flag pins provide explicit indications instruction flow machine status debugging. Provide enough space around device case heat sink needed. Always review latest errata.
Hardware Design Checklist ADSP-TS101S TigerSHARC® Processors (EE-176)
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References
ADSP-TS101 TigerSHARC Processor Hardware Reference. Rev. 1.0, April 2003.Analog Devices Inc. ADSP-TS101S TigerSHARC Embedded Processor Data Sheet. Rev. Analog Devices Inc. TigerSHARC Anomaly List Revision(s) TS101S-0.0, TS101S-0.1, TS101S-02. July 2003. Analog Devices Inc. Estimating Power ADSP-TS101S (EE-169). February 2003. Analog Devices Inc. ADSP-TS101S TigerSHARC Processor Boot Loader Kernels Operation (EE-174). April 2003. Analog Devices Inc. Analog Devices JTAG Emulation Technical Reference (EE-68). Rev. 2.6, July 2003. Analog Devices Inc.
Document History
Version July 2004 Eric Yang Description Bullet added Linkport segment. Title changed from Hardware design checklist ADSP-TS101S Hardware Design Checklist ADSP-TS101S TigerSHARC Processors. Added Introduction section. Modified Table Handling method unused Addr31-0 pins from Handling method unused LxCLKIN pins from
December 2003 Eric Yang
Added section explain method handle LDQM HDQM pins, according anomaly list. Added section explain method handle SDCKE pin. Deleted links bullet Cluster section. Changed names reference materials. Several sentences reworded from language perspective. November 2002 Eric Yang Initial Release
Hardware Design Checklist ADSP-TS101S TigerSHARC® Processors (EE-176)
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