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EE-148
Technical Notes using Analog Devices' components development tools
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Introduction SHARC® Multiprocessor Systems Using VisualDSP++Contributed Maikel Kokaly-Bannourah April 2003
Introduction
following Engineer-to-Engineer note intended give introduction Multiprocessor (MP) systems using VisualDSP++The explanation will based code example written system, which consists ADSP-21160s ADSP21160 EZ-Kit Boards) using VisualDSP++3.0. SHARC® Multiprocessor systems configured different ways: Several DSPs sharing external Link Port point-to-point communication DSP's serial ports multi-channel mode. This note will discuss implementation system with DSPs sharing external bus. more details other implementations please refer ADSP-21160 SHARC® Hardware Reference Manual.
MPMEMORY{}, defines each processor's offset within multi-processor memory space (MMS). linker uses offsets during multiprocessor linking. MEMORY{}, defines memory processors present system. PROCESSOR{} SECTIONS{} commands define each processor place program sections each processor's output file, using memory definitions. SHARED MEMORY{}, needed when external shared memory used system. This command identifies output shared memory items generates Shared Memory executable files (.SM) that reside shared memory system. file generated from source code file (.ASM, .CPP), which must included with project files. This file contains variable definitions data that will placed external shared memory. LINK_AGAINST(), resolves symbols within multiprocessor memory directs linker check specified executables (.DXEs .SMs) resolve variables labels that have been resolved locally. Whenever expressions variables defined (i.e. internal memory another processor system) LINK_AGAINST() command must used LDF. Note: files files included command line, file must placed
Linker Description File (LDF) Systems
very first step setting system create multiprocessor project using multiprocessing capabilities linker, file describe system. describes multiprocessor memory offsets, shared memory, each processor's memory. following commands must considered when writing LDF:
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first, followed other DXE's, linker able resolve variables correctly. maximum number processors that declared architecture-specific (i.e. maximum ADSP-21160's ADSP21065L's). Also note that combination different DSPs with different architectures (i.e. ADSP-21062 ADSP-21160) same supported VisualDSP++TM. However, combination DSPs from same architecture family (i.e. ADSP-2106x members such ADSP-21060, ADSP-21061 ADSP21062) supported although some memory segments definitions considerations must made. example where above commands used shown Figure remainder file basically same default provided with tools (please refer Linker Utilities Manual ADSP-21xxx Family DSPs EE-69 "Understanding Using Linker Description Files (LDFs)" general description files). following example, ADSP21160 external shared memory system defined.
Figure Excerpt from example
Introduction SHARC® Multiprocessor Systems Using VisualDSP++(EE-148) Page
that different sections have been discussed, examine example code that explores some capabilities DSP. system hardware configuration please refer chapter ADSP-21160 SHARC® Hardware Reference. Also information configure cluster system using ADSP-21160 evaluation boards refer ADSP-21160 EZ-KIT Lite User's Guide.
Multiprocessor (MMS)
Memory
Space
multiprocessor memory space divided into number address regions (this number processor specific) that correspond internal memory DSPs system. ADSP-21160's multiprocessor memory space appears Figure Note: programs only Normal word addressing multiprocessor memory space. Other addressing schemes corrupt valid data. Depending address range used, internal memory particular multiprocessor system will accessed source destination. Writes Broadcast region access memory DSPs multiprocessing system. instance, accessing memory location within address range 0x300000 0x3FFFFF, equivalent accessing internal memory system with also access internal memory accessing corresponding memory region. Note that this case, reads/writes from/to internal memory does make access external system bus.
Figure ADSP-21160 Multiprocessor Memory Space
following example from code where used access memory location another system. this case with accesses external port buffer (EPB1) with ID2:
Example
r0=0x200006; dm(EI11)=r0;
example address 0x200000, which then added address corresponding EPB1 (0x6). Therefore, this will result write access ID2's EPB1 external device (DSP host). Note: multiprocessor systems with ID=001 must present, since this responsible driving external control lines stable during reset.
Introduction SHARC® Multiprocessor Systems Using VisualDSP++(EE-148) Page
External Memory
External memory widely used systems. important point keep mind that DSPs system must initialize their control registers before trying access external memory (i.e. WAIT register case SBSRAM). ADSP-21160 gluelessly interfaced synchronous asynchronous SRAM devices, however DRAM requires external controller. very important proper access mode type memory used hardware system. access mode programmed WAIT register. Default power up/reset settings System Control (SYSCON) WAIT registers detailed ADSP-21160 Hardware Reference Manual. User defined settings must support external memory address ranges that user intends their code hardware systems well access mode appropriate memory device(s) (i.e. synchronous asynchronous accesses). MSIZE setting must also exceed size actual physical memory connected user's system. Note that SDRAM gluelessly supported certain devices like ADSP-21065L ADSP-21161. these cases, specific registers must initialized prior accessing external memory. SDRDIV IOCTL, ADSP-21065L, SDRDIV SDCTL, ADSP-21161, registers processors system must initialized same value. Once DSP's internal memory controller been configured, external memory accessed external bus. example project, shared.asm file contains variable definitions data that will placed external shared memory. Note: with lowest number (and therefore highest external arbitration priority system) responsible initializing external data defined .ASM shared memory file during booting-up sequence.
Inter Processor Messages Vector Interrupts
Message Passing registers (MSGRx) general-purpose memory mapped registers that used message passing between host between DSPs. Similarly, Vector Interrupts used inter-processor communication between host between DSPs. MSGRx VIRPT registers used message passing following ways: Message Passing. host master DSP) message registers, MSGR0 through MSGR7, communicate with DSP. Vector Interrupts. host master DSP) issue vector interrupt writing address interrupt service routine VIRPT register. When serviced, this high priority interrupt causes branch service routine that address.
Example
Excerpt from ID2: VIRPT Generation I0=0x100001; VIRPT reg. address R0=0x40080; SFT0I address will executed DM(I0,M0)=R0;// write VIRPT reg.in Excerpt from ID1: VIRPT Service Routine SFT0I user software interrupt vector address IMASK VIRPTI; VIRPT enabled vector interrupt table R0=0x2f2f2f2f; Value msg. Passing (DB);// Serve VIRPTI generated I0=MSGR0;// Load address MSGR0 write value DM(MMS_ID2,I0)=R0;
Introduction SHARC® Multiprocessor Systems Using VisualDSP++(EE-148) Page
example triggers vector interrupt writing address service routine served (0x40080 SFTOI) VIRPT (0x100001 VIRPT address 0x100000 ID1). Then, service routine writes test value MSGR0 register ID2, using previously defined offset value (MMS_ID2 0x200000). This just example inter-processor message passing VIRPT interrupts used flags just indicate program execution completion systems.
MODE2 BUSLK; jump(PC,0); ustat1 DM(SYSTAT); USTAT1 jump(PC,-2); Broadcast_data; MMS_Broadcast; lcntr broadcast_transfer until lce; broadcast_transfer: dm(i1,m1); pm(i8,m8) pm(i8,m8) MODE2 BUSLK;
Lock Semaphores
Semaphores useful synchronizing tasks performed system. semaphore flag that accessed DSPs present system. critical tasks (i.e. should interrupted), when attempting read-modify-write operation semaphore, must have mastership duration operation. This achieved using DSP's lock feature, which retains mastership prevents other processors from simultaneously accessing semaphore. read-modify-write operation accomplished with following steps (Example Request lock setting BUSLK MODE2. Wait mastership acquired. Wait until Direct Write Pending (DWPD) zero. Read semaphore, test write following Excerpt from ID1's code demonstrating Lock Broadcast write:
Example
Excerpt code: BROADCAST write using Lock
While BUSLK set, determine acquired mastership executing conditional instruction with Master (Not condition code. become master, proceed with external read write. not, clear BUSLK again later. After mastership acquired, Direct Write Pending (DWPD) bit's status SYSTAT must checked ensure that semaphore write another processor pending. lock used combination with broadcast writes implement reflective semaphores multiprocessing system. reflective semaphore (i.e. located DSP's internal memory processor register) must located same address each DSP. Once become master, performs broadcast write specified address every DSP, including itself. Lastly, BUSLK must cleared free after broadcast transfer finished.
Multiprocessor Data Transfers
Throughout code, several types data transfers have been implemented: Master Slave Direct Memory Access (DMA) between ID2,
Introduction SHARC® Multiprocessor Systems Using VisualDSP++(EE-148) Page
Master from external memory, Core transfer, Broadcast Write DSPs system. Let's examine different types data transfers performed. Note that Broadcast Write already been discussed previous sections.
7.1. Master Slave Direct Memory Access (DMA) between
Setup Master
initiate master mode transfer sets channel's enable (DEN) bit. will then start transferring data EPB1 buffer FIFO, where slave DSP, this case ID2, access needs Slave before data transferred internal memory.
Setup Slave
channel this mode independently initiate internal external memory transfers. Master mode applies external port channels: example channel used perform Master transfer from follows:
Example
Excerpt from ID1:Master DMA,DMA channel transfer from r0=0; dm(DMAC11)=r0;// clear Contr source r0=1; dm(IM11)=r0; modifier r0=10; dm(C11)=r0; r0=0x200006; dm(EI11)=r0; write slave EPB1 r0=0; dm(EM11)=r0; ext. modifier r0=10; dm(EC11)=r0; ext. counter ustat1=0x0404; dm(DMAC11)=ustat1; ustat1=dm(DMAC11); ustat1 0x1; enable channel dm(DMAC11)=ustat1; transmit data counter
slave mode channel, when data transfer direction external internal, slave mode channel does initiate transfers until external device this case ID1) writes data channel's EPB1 buffer FIFO. Slave transfer example looks follows:
Example
Excerpt from ID2:Slave DMA, channel 11,receive data transmitted r0=0; dm(DMAC11)=r0;// clear Control Reg. r0=DMA_dest_ID2; dm(II11)=r0; destination r0=1; dm(IM11)=r0; modifier r0=10; dm(C11)=r0; r0=0x01; dm(DMAC11)=r0; enable receive data counter
Note that processor does registers slave mode DMA. From previous Master transfer, transmits data EPB1 buffer FIFO. detects that data present performs transfer internal memory, emptying EPB1 buffer FIFO.
Master from External SBSRAM
sets channel's parameter registers. processor uses registers access master mode DMA. will write FIFO (EPB1) ID2. Note that external modifier zero.
Note that previous transfer, where FIFO (EPB1) used, master slave need configured. type Master where slave needs when master writes/reads directly (without EPBx slave FIFOs) from/to
Introduction SHARC® Multiprocessor Systems Using VisualDSP++(EE-148) Page
external memory. advantage using this type transfer that only needs configured. Same setup used when reading/writing from/to internal memory MMS. Note: direct read/write from/to internal memory it's supported certain devices (ADSP-21065L ADSP-21161). These devices access internal memory indirectly with DMA. example channel used perform Master transfer from external SBSRAM ID1's internal memory follows:
Example
Excerpt from ID1: Master DMA, channel transfer from SBSRAM r0=0; dm(DMAC10)=r0;// clear Control Reg. r0=ext_mem_data; dm(EI10)=r0; source SBSRAM
Address Generators (DAGs) used directly transfer data from internal memory internal memory ID1. example this shown below:
Example
Excerpt from ID2: Core transfer,ID2 ID1. b1=DAG_source_ID2; Source l1=0;m1 b8=DAG_dest_ID1;// Dest. l8=0; r2=dm(i1,m1); lcntr N-1,do DAG_transfer until lce; DAG_transfer: //Dual access cycle dm(i1,m1),pm(i8,m8) pm(i8,m8)
data arrays declared, each DSP's internal memory. example accesses array stored through space. registers used access data buffers perform direct data transfer. Note that values fetched from both program data memory, resulting dual memory access executing just cycle.
r0=1; dm(EM10)=r0; modifier r0=10; dm(EC10)=r0; counter r0=DMA_dest_ID1; dm(II10)=r0; dest. ID1's int. mem. r0=1; dm(IM10)=r0; modifier r0=10; dm(C10)=r0; ustat1=0x0400; dm(DMAC10)=ustat1; ustat1=dm(DMAC10); ustat1 0x1; enable channel dm(DMAC10)=ustat1; receive data counter
Some Considerations
Performance
Like before, sets channel's parameter registers. only difference with respect previous example that there need slave DMA. SBSRAM master mode transfer internal memory will initiate once channel's enable (DEN) set.
Core transfer
Core data transfers nice fast transferring words data since code optimized transfer word data cycle. However, better choice when large amounts data need transferred since core utilized computational processing. Remember that transfers operate background freeing core. Also, master transfer configured slave host), increasing performance applications where master might overloaded with processing activity. more details DMAs data transfer, please refer EE-84 "SHARC® Modes Operation" Processor
Core transfer different handling data where used. this case,
Introduction SHARC® Multiprocessor Systems Using VisualDSP++(EE-148) Page
chapter ADSP-21160 SHARC® Hardware Reference Manual.
Checking
This routine used check whether executable file generated gets loaded into correct system. This code ensures that mismatch occurs.
Example
Excerpt from ID2: Checking R0=DM(SYSTAT); SYSTAT value R1=FEXT 8:3; value R2=0x2; ID=2 R1=R1-R2; this ID2? JUMP incorrect_ID; incorrect jump endless loop
debugger operations like load, reset provide user with capability testing system with full synchronization DSPs. Note: VisualDSP++Simulator allows fully test algorithms core code each system independently. Some debugger features are: Multiprocessor debug commands allow user download, reset, restart, step through code just like with single-processor commands, except that they work synchronously active DSPs selected group. Debugger provides Multiprocessor Status window. This window displays current status each system: Running, Halted, Unknown. contents each debugger window within emulation debugger session reflects selected DSP, i.e. window Focus. default, contents each window will change depending which focus. debugger supports Pinning windows (Memory, Registers, etc.) dedicating them specific system. This will allow user dedicate particular debugger window only display information from particular system, opposed having contents window change whenever processor selected Status window. debugger provides Multiprocessor Group window from which processors grouped into multiple, logical units upon which commands applied. This window particularly useful when many processors present system user wishes control/debug subsets these processors together.
Basically, reads value from SYSTAT register compares with theoretical value this case, code been written ID2, makes sure been loaded into correct target, which false, will enter endless loop indicating that error occurred. Note: loading executable file into wrong will cause program work properly since offset values will correspond correct ones therefore, inter-processor accesses will fail.
Multiprocessor Debugger Support
VisualDSP++Multiprocessor Debugger provides user with full system evaluation using Emulator. Emulator allows code testing evaluation hardware platform. inter-processor communications well data transfers supported.
Introduction SHARC® Multiprocessor Systems Using VisualDSP++(EE-148) Page
Figure Multiprocessor Debugger Support
pinning, processor status items Multiprocessor window, conjunction with single-processor debug commands debug individual processors session.
VisualDSP Configurator
Debugger allows emulator targets. Circuit Emulator (ICE) development tool debugging programs running real time target system hardware. emulator reads executable files loads them into DSP. provides controlled environment observing, debugging, testing activities target system connecting directly target processor through JTAG interface.
system emulation, Summit-ICE Universal Emulator system used. first step, platform must configured using Visual Configurator. Configurator used describe user's hardware platform JTAG emulator. Once platform been described, emulator target session based upon following steps should followed when configuring platform: Open VisualDSP Configurator. Create platform. Specify name, number type devices included part platform. These steps illustrated Figure
Introduction SHARC® Multiprocessor Systems Using VisualDSP++(EE-148) Page
Please aware Initial Reset Startup option, which appears Device Properties window shown Figure Enabling this option will perform complete reset selected device every time emulator session initiated. systems where some settings need preserved (i.e. WAIT register) this option should cleared. Note: there also similar option debugger itself, reset before loading executable, which performs complete reset devices system upon downloading code DSPs. This option found under Settings/Target Options/.
Figure VisualDSP Configurator
Test Utility JTAG Scan Test
Before getting into actual system debugging, must tested make sure that been properly configured. Test Utility (Figure used this purpose. Open utility, select proper emulator address, check continuous scan start testing. scan test will then performed output window would look follows after successfully completed scan test:
Figure VisualDSP Test Utility.
Introduction SHARC® Multiprocessor Systems Using VisualDSP++(EE-148) Page
case test does complete successfully, error message will displayed with possible solution problem. Here description some issues that should kept mind system design: multiprocessor system imperative that JTAG header buffered. This will keep signals clean avoid noise problems that occur with longer signal traces (ultimately resulting reliable emulator operation). scan chain, recommended more than eight physical devices (although, theoretically, devices that supported JTAG scan chain software about 50). recommendation more than eight physical devices mostly transmission line effects that appear long signal traces, based some fieldcollected empirical data. power-on sequence target emulation system follows: Apply power emulator first, then target board. This ensures that JTAG signals correct state free. Please refer EE-Note Analog Devices JTAG Emulation Technical Reference (2.5) more detailed description this topic.
System Emulation
Confirmation window (Figure appears. This window enables user select which .DXE file loaded into which DSP.
Figure Load Multiprocessor Processor Window.
Once code been successfully loaded into each DSP, system fully evaluated using features previously described. After running code both DSPs user view contents data memory windows should able verify that data transfers between DSPs have completed successfully. Figure illustrates classical example some debugger windows that viewed when evaluating system. Running code targets (synchronously both DSPs independently), setting break points, viewing memory contents, system registers just some VisualDSP++MP debugger capabilities.
that project been created emulator platform ready debugging, begin with hardware emulation. First all, executable files (.DXE's) downloaded corresponding DSPs. emulation, Load Multiprocessor
Introduction SHARC® Multiprocessor Systems Using VisualDSP++(EE-148) Page
Figure VisualDSP++Multiprocessor Session
Introduction SHARC® Multiprocessor Systems Using VisualDSP++(EE-148) Page
References
ADSP-21160 SHARC® Reference, Analog Devices Inc. Hardware VisualDSP++Emulation Tools Installation Guide Windows 95/98/NT/2000, Analog Devices Inc. Analog Devices JTAG Emulation Technical Reference (EE-68), Analog Devices Inc. Understanding Using Linker Description Files (LDFs) (EE-69), Analog Devices Inc. SHARC® Modes Operation (EE-84), Analog Devices Inc.
ADSP-21160 EZ-KIT Lite User's Guide, Analog Devices Inc. VisualDSP++Linker Utilities Manual ADSP-21xxx Family DSPs DSPs, Analog Devices Inc. VisualDSP++Users Guide ADSP21xxx Family DSPs, DSPs, Analog Devices Inc.
Document History
Version March 2003 M.Kokaly-Bannourah October 2001 M.Kokaly-Bannourah Description Updated document code (VisualDSP++3.0 compatible) Initial Release
Introduction SHARC® Multiprocessor Systems Using VisualDSP++(EE-148) Page

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