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EE-179
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ADSP-TS201S TigerSHARC® System Design Guidelines
Contributed Greg John Phil 2004 supply voltages beyond normal supply tolerances eliminate problems short term. Power Supply power supply pins used power internal logic except eDRAM, I/O's PLL. VDD_A Power Supply VDD_A power supply pins used directly power PLL. These pins isolated from internal supply pins additional decoupling filtering circuits added reduce noise. multiprocessor designs recommends keeping VDD_A supplies separate each processor. Refer VDD_A supply decoupling section further details. VDD_IO Power Supply VDD_IO power supply pins provide power I/O's including link port LVDS pins. VDD_DRAM Power Supply VDD_DRAM power supply pins provide power internal embedded DRAM logic.
Introduction
This EE-Note discusses specific hardware issues when implementing system design, which incorporates ADSP-TS20xS TigerSHARC® processors. This document provided hardware engineers designing systems with silicon revision higher. guidelines provided this EE-Note apply ADSPTS201S, ADSP-TS202S ADSP-TS203S TigerSHARC embedded processors.
Power Supplies
ADSP-TS20xS processor four power supply domains (Internal), VDD_A (Analog PLL), VDD_IO (External I/O) VDD_DRAM (DRAM) domain. VDD_A supply filtered version supply. table below specifies power supply voltages ranges ADSP-TS20xS. Refer ADSP-TS201S TigerSHARC Embedded Processor Data Sheet more details. Supply VDD_A VDD_IO VDD_DRAM Range note below note below 2.5V 1.5V Table-1: Power Supplies Note recommends that designers include method vary and/or adjust VDD_A power supplies voltages range between 1.26 many initial designs, insufficient bypass capacitors, poor ground supply connections numerous other reasons cause degradation chip performance intermittent functionality. these cases increasing decreasing
Ground Supply
ADSP-TS20xS contains single ground supply VSS. pins ground returns VDD, VDD_A, VDD_DRAM VDD_IO supply pins.
Copyright 2004, Analog Devices, Inc. rights reserved. Analog Devices assumes responsibility customer product design application customers' products infringements patents rights others which result from Analog Devices assistance. trademarks logos property their respective holders. Information furnished Analog Devices Applications Development Tools Engineers believed accurate reliable, however responsibility assumed Analog Devices regarding technical accuracy topicality content provided Analog Devices' Engineer-to-Engineer Notes.
Power Supply Current
VDD, VDD_A, VDD_DRAM VDD_IO power supply currents calculated with formulas specified application note Estimating Power ADSPTS201S (EE-170) [5]. SPICE analyses power characteristics necessary. supply filtering Enough "bulk" capacitors must used prevent power supply ripple that exceeds max/min power supply tolerances (+/- caused current transients system. Several parallel electrolytic and/or tantalum capacitors preferred order minimize provide sufficient capacitance.
Power Supply Sequencing
There power sequencing requirements other than VDD_DRAM voltage must occur last. Refer Figure below.
Supply Decoupling
analog (VDD_A) supply pins power clock generator PLLs. produce good stable clock, systems must provide "clean" power supply VDD_A domain. Therefore, system designer must critical attention bypassing filtering VDD_A supply. decoupling capacitor placement VDD_A should given first priority over other supplies. figure below shows recommended design VDD_A filtering circuit. components used this circuit should placed close possible VDD_A pins minimize inductance stray capacitance. VDD_A supply consumes approximately thus proper inductor with resistance should used.
Place close pins possible Place close pins possible
3.3V
V3.3V VDD_IO
Supplies Stable
3.3V
V3.3V VDD_IO
Supplies Stable
2.5V
2.5V
2.0V
2.0V
1.5V
VDD_DRAM
DD_A
1.5V
VDD_DRAM VDD/V DD_A
1.0V
1.0V
Time
Time
(Recommended)
Figure-1: Power Supply Sequence During power supply sequence important hold /RST_IN asserted (low) also make sure SCLK held until supplies stable. Refer reset SCLK sections further details. Although both power supply sequences above valid recommends that VDD_IO sequenced first same time VDD/VDD_A supply.
10uH
TS20xS VDD_A VDD_A
10uH
TS20xS VDD_A VDD_A
Figure-2: VDD_A Supply Decoupling recommended that VDD_A decoupling circuit duplicated each processor multiprocessor systems. Place inductor capacitor together with good connections VDD, VDD_A. Place (minimum) capacitors close VDD_A package pins possible. Make sure VDD_A trace isn't close noise generating signals.
Supply Bypass Capacitors
ADSP-TS20xS processor requires bypass capacitors each supply. many cases difficult place lots supply bypass capacitors close package pins, especially bottom side board. recommends that designers prioritize decoupling capacitor placement following order: VDD_A bypass capacitors bypass capacitors VDD_DRAM bypass capacitors VDD_IO bypass capacitors
Supply Decoupling
Below minimal recommended bypass capacitor requirements single processor's VDD_DRAM supply. capacitors should duplicated each processor system.
Low-ESR/low-ESL capacitors recommended proper bypassing. higher-frequency filtering, 0.01 0.001 capacitors also used addition capacitors), provided their inductance small enough. some cases, performing
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Minimum high frequency bypass capacitors located close package pins possible. least bypass capacitor located close package pins possible. least four bypass capacitors located close package pins possible. minimum "bulk" (less then 100m) capacitors each processor connected VDD_DRAM supply recommended. These capacitors used reduce power supply ripple during high peak transient currents. Single Electrolytic: Panasonic Series Sanyo OS-CON series Single tantalum: series Multiple ganged capacitors: series Multiple ganged capacitors: series
Supply Decoupling
important provide proper decoupling VDD_IO supply. Although important VDD_A, VDD_DRAM supplies, careful capacitor placement supply ripple analysis required ensure adequate decoupling. Minimum high frequency bypass capacitors located close package pins possible. least bypass capacitor located close package pins possible. least four bypass capacitors located close package pins possible. minimum "bulk" (less than capacitors each processor connected supply recommended. These capacitors used reduce power supply ripple during high peak transient currents. Single Electrolytic: Panasonic Series Sanyo OS-CON series Single tantalum: series Multiple capacitors: series
Supply Decoupling
High frequency noise internal supplies adversely affect speed device. always important provide robust supply bypassing internal supplies especially products whose internal voltages less than recommended that many highfrequency capacitors possible connected supplies close package pins possible. minimum "bulk" (less than 100m) capacitors each processor connected supply recommended. These capacitors used reduce power supply ripple during high peak transient currents. Minimum high frequency bypass capacitors located close package pins possible. least bypass capacitor located close package pins possible. least four bypass capacitors located close package pins possible. minimum "bulk" (less than capacitors each processor connected supply recommended. These capacitors used reduce power supply ripple during high peak transient currents. Single Electrolytic: Panasonic Series Sanyo OS-CON series Single tantalum: series
ADSP-TS20xS contains single VREF voltage reference pin. This sets input reference voltage certain input pins. exact list pins whose threshold VREF refer ADSP-TS201S TigerSHARC Embedded Processor Data Sheet [1]. VREF voltage should value specified data sheet with recommended circuit Figure-3 below. resistor tolerances must
VDD_IO 2.87K
Place close VREF
VREF VREF
Figure-3: Recommended VREF circuit multiprocessor designs where VREF shared between DSPs, important make sure that each processor least (preferably more) high speed decoupling
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capacitor located close VREF pin. also important keep noise sources from coupling into VREF signal.
SCLK_V
ADSP-TS20xS contains single SCLK_VREF voltage reference pin. This sets input reference voltage certain input pins. exact list pins whose threshold SCLK_VREF refer ADSP-TS201S TigerSHARC Embedded Processor Data Sheet [1]. SCLK_VREF voltage should value specified data sheet with recommended circuit figure below. resistor tolerances must
Place close SCLK_VREF pins
When using default configuration, external connection needed; should treated Connect). other configurations (non default), must connected VDD_IO directly through resistor (maximum) pin. multi-processor designs where configuration pins likely wired together (SCLKRAT2-0 connected several processor's) make sure that proper value resistor used override default pull-down/up. maximum resistor value divided number processors. initial prototype designs advantageous have pads populating strap resistors change default setting SCLKRAT2-0, CONTROLIMP1-0 DS2-0 pins. Configuration pins, which have default pull-ups, should have resistor pads between default pull-downs should have resistor pads between VDD_IO. CONTROLIMP1-0 Configuration Pins CONTROLIMP0 internal pulldown resistor CONTROLIMP1 internal pull-up resistor. These pins control output driver impedance. designs recommended CONTROLIMP1-0 "00" (Normal). CONTROLIMP1-0 (Recommended) (default) Driver mode Normal Reserved Mode Reserved
SCLK_SUPPLY (3.3 2.5V)
SCLK_V
SCLK_V
Figure-4: Recommended SCLK_VREF circuit multiprocessor designs where SCLK_VREF shared between DSPs, important make sure that each processor least (preferably more) high speed decoupling capacitor located close SCLK_VREF pin. also important keep noise source from coupling into SCLK_VREF signal.
No-Connect (NC) Pins
ADSP-TS20xS contains several No-Connect (NC) pins. These pins must connect supply ground (VDD, VDD_IO, VDD_A, VDD_DRAM VSS) they must connect other pin. pins must left totally unconnected.
Table-2: CONTROLIMP1-0 Configuration options SCLKRAT2-0 Configuration Pins SCLKRAT2-0 pins have internal pulldown resistor. These pins multiplier, which generates core clock from SCLK input. Note duty cycle SCLK specified 60/40 multiplier rates except which require tighter duty cycle 55/45.
Configuration Pins
ADSP-TS20xS configuration pins SCLKRAT2-0, ID2-0, CONTROLIMP1-0 DS2-0 used select various chip functions such clock ratio, chip-ID output impedance. These pins typically have either internal pull-up pull-down resistor. configuration pins must have constant value while ADSP-TS20xS powered.
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SCLKRAT2-0 (default) Ratio Reserved SCLK duty cycle 60/40 55/45 60/40 55/45 60/40 60/40 60/40 Figure-5: External port connection between TS20x's; ID's must
FPGA EXTRNAL PORT TS20x ID=0 EXTRNAL PORT FPGA TS20x ID=0 EXTRNAL PORT Used
TS20x ID=0
TS20x ID=0
EXTRNAL PORT
Other
Single TS20x
Multi-processor TS20x
Table-3: SCLKRAT2-0 Configuration options ID2-0 Configuration Pins ID2-0 pins have internal pull-down resistor. single processor systems multiprocessor designs where External port connected other TS20xS device, pins should default value (000). This because internal pull-up/pull-downs certain pins, like memory interface arbitration enabled only when ID2-0 (000). Setting ID2-0 (000) eliminates need external resistors. Refer ADSP-TS201S TigerSHARC Embedded Processor Data Sheet more details. Note that ID2-0=[000] only processor which enable SDRAM start sequence. multiprocessor designs where External port shared between TS20xS devices, each processor must programmed unique device starting with ID2-0 (000) incrementing upwards. table figures below describe various configurations ID2-0 assignments. ID2-0 (default) Multiprocessor Table-4: ID2-0 Configuration options
TS20x ID=0 EXTRNAL PORT FPGA
TS20x ID=1
EXTRNAL PORT
TS20x ID=7
EXTRNAL PORT
Other
Multi-processor TS20x
Figure-6: External port connection between TS20x's; ID's must different. DS2-0 Configuration Pins pins contain internal pullup resistor; contains internal pull-down resistor. These pins control drive strength ADSP-TS20xS output drivers. further information refer ADSP-TS201S TigerSHARC Embedded Processor Data Sheet application note User Guide ADSP-TS201S TigerSHARC processor IBIS files (EE-198) [7].
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DS2-0 (default) Drive Strength
(CONTROLIMP1
Output
(CONTROLIMP1
11.1% 23.8% 36.5% 49.2% 61.9% 74.6% 87.3% 100%
whether /RST_IN active (low) /RST_IN deasserted (high). table above shows what resistors connected during active reset during normal operation. /BMS Strap (EBOOT) /BMS strap sets EEPROM (default) External boot mode. During reset, /RST_IN (low), pull-down resistor enabled /BMS chip's ID2-0 pins programmed (000). remaining DSPs ID2-0 programmed system, will have pull-downs pull-ups active /BMS. over-ride default, place resistor between /BMS VDD_IO.
Table-5: DS2-0 Configuration options
Strap Pins;
ADSP-TS20xS processor contains four dual-purpose strap pins /BMS, /BM, TMR0E /BUSLOCK. These strap pins select boot-mode, SYSCON/SDRCON write enable, link port width interrupt (edge/level). These strap pins also have additional functionality after reset. When default configuration used, external resistor needed. other configurations, resistor connected VDD_IO required. strap these pins directly supply other pin. designs which driving strap pins directly from FPGA, ASIC other device, refer data sheet timing details when strap pins sampled when FPGA, ASIC device should stop driving strap data value. /BMS TMR0E /BUSLOCK /RST_IN=0 (pd_0) (pd) (pd) (pd_0) /RST_IN=1 (pu_0) Driven Driven (pu_0) /BMS strap pins high, deassertion /RST_IN, processor starts running from memory address selected /IRQ3-0 signals (one /IRQ signals should asserted). table below shows starting memory address. /BMS (default) Boot Mode EPROM Boot External Link port Boot Table-7: /BMS strap options Strap (IRQEN) strap sets Interrupt disable (default) Interrupt enable /IRQ3-0. During reset, /RST_IN (low), pull-down resistor enabled. over-ride default, place resistor between VDD_IO.
(default)
Interrupt Enable, (IRQ3-0) Type Disable interrupts, level-sensitive Enable interrupts, edge-sensitive Table-8: strap options
internal pull-down pd_0 internal pull-down only processor who's ID2-0 =(000) pu_0 internal pull-up only processor who's ID2-0 (000) Table-6: Strap internal pull-up/pull-down resistors four strap pins have internal pull-down resistor, pull-up resistor no-resistor (three-state) each pin. resistor type, which connected pad, depends
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Interrupt
/IRQ0 /IRQ1 /IRQ2 /IRQ3
Address
0x3000 0000 (External Memory, /MS0) 0x3800 0000 (External Memory, /MS1) 0x8000 0000 (External Memory, /MSH) 0x0000 0000 (Internal Memory)
when /RST_IN active (low) these pins three-stated pull-up resistor enabled. FPGAs some ASICs three-state their pins before they programmed. During this time, some FPGAs and/or ASICs typically turn internal pull-up pulldown resistor. These resistors used keep signals from floating mid-scale before programming. important make sure that FPGA ASIC which connects Link Port Block Completion pins don't have internal pull-down resistor active while /RST_IN asserted (low). FPGA ASIC pull-up this Note, only link ports have special test mode straps. only link port requires connection FPGA ASIC, link port since this Link Port Block Completion signal doesn't have test mode straps associated with designs which driving Test Mode strap pins directly from FPGA, ASIC other device, refer data sheet timing details when Test Mode strap pins sampled when FPGA, ASIC device should stop driving strap data value. Note: under circumstances, rising edge reset (de-assertion edge), test mode Block Completion signals value other than logic-1 processor test mode will enabled. assist debugging recommend that designers include option placing optional pull-down resistors between Test Mode Strap pins VSS. also recommended that designers include option placing optional pull-up resistors between Test Mode Strap pins VDD_IO. These resistors added removed enable disable test modes.
Table-9: Boot, From Memory Address TMR0E Strap (LINK_DWIDTH) TMR0E strap sets Link Port Data Width, 1-bit (default) 4-bit, Link Ports. During reset, /RST_IN (low), pull-down resistor enabled TMR0E pin. over-ride default, place resistor between TMR0E VDD_IO.
TMR0E (default)
Link Port Input Data Width 1-Bit 4-bit Table-10: TMR0E strap options
/BUSLOCK Strap (/SYS_REG_WE) /BUSLOCK strap sets write enable always writable one-time writable (default) SYSCON SDRCON registers. During reset, /RST_IN (low), pull-down resistor enabled /BUSLOCK chip's DSP-ID programmed "0". remaining DSPID's (1-7), system, will have pulldowns pull-ups active /BUSLOCK. over-ride default, place resistor between /BUSLOCK VDD_IO.
Test Mode Description
Strap /L1BCMPO /L2BCMPO /L3BCMPO
/BUSLOCK (default)
SYSCON/SDRCON write enable One-time writable after reset Always writable
CCLK/4 /L0BCMPO SOCCLK/2 /L1BCMPO SCLK /L2BCMPO
Table-11: /BUSLOCK strap options
Test Mode Strap Pins (Link Port)
There three special test strap pins /L1BCMPO, /L2BCMPO /L3BCMPO, which enable test mode functions. These pins Link Port Block Completion signals. They normally outputs however,
Table-12: Link Port test mode strap options TS201/TS202
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Test Mode Description CCLK/4 /L0BCMPO SOCCLK/2 /L1BCMPO SCLK Table-13: Link Port test mode strap options TS203 Strap /L1BCMPO low-jitter clock buffer driver. output-to-output skew clock buffer driver. clock signals from clock buffer outputs SCLK inputs should carefully reviewed. single multiple-output clock buffer should used drive clock signals devices including DSPs, FPGAs, ASICs Memories. Using multiple clock buffer chips increases clock-to-clock skew between clock signals recommended.
SCLK
During initial power-up conditions (after supplies stable) SCLK must least while reset asserted (/RST_IN low). recommended that incoming SCLK signal remain (stopped) until TS20xS supplies have stabilized. After power-up SCLK signal should stop running unless reset signal (/RST_IN) asserted. SCLK needs stop following power-up sequence, /RST_IN must also asserted. When re-starting SCLK from this condition, follow same guidelines power-up sequence.
Single CLOCK BUFFER
Matched Length
CLK#1 CLK#7 CLK#8
TigerSHARC ID=1
TigerSHARC ID=7
Other Devices (Memory, Host)
Figure-7: Recommended Clock Distribution Method
more CLOCK BUFFERS
Matched Length
CLOCK SOURCE
CLK#0 CLK#5
TigerSHARC ID=0 TigerSHARC ID=5
CLK#6
TigerSHARC ID=6 Other Devices (Memory, Host)
SCLK Distribution
single multiprocessor designs careful clock design distribution required ensure proper full-speed internal external operation. Listed below some guidelines clock distribution. connections should point-to-point from clock buffer output clock inputs. Trace lengths should matched (+/- mils) minimize skew. Capacitance clock signals should matched within Minimize number vias. Maintain same number vias each clock signal. clock signals close other signals same layer. Keep least minimum spacing other signals. signals directly above below clock signals. high quality jitter clock source generating clock reference.
CLK#8
Figure-8: Recommended Clock Distribution Method
SCLK Startup Considerations
required that designers follow techniques specified ensure proper operation ADSP-TS20xS. These techniques insure that during VDD/VDD_A power supply ramp, internal core clock isn't running. VDD_IO stable (2.5 SCLK running while VDD/VDD_A ramping, will cause additional current consumed supply when supply near VDD/2. This added dynamic current could cause regulator supply overload shut down excessive current while supply ramping. avoid this problem techniques ensure internal core clock isn't running while supply ramping. Gate SCLK (keep low) until supplies stable. (Recommended) Sequence Supplies such that supply stable before ramping VDD_IO supply. This
ADSP-TS201S TigerSHARC® System Design Guidelines (EE-179)
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CLUSTER
CLUSTER
CLOCK SOURCE
CLK#0
TigerSHARC ID=0
ensures that internal SCLK receiver disabled, forcing internal clock while supply ramping.
THIGH 3.3V SCLK_VREF 1.65V 3.3V THIGH SCLK_VREF 1.25V
SCLK Design Considerations
Careful analysis required when choosing components generating, buffering distributing SCLK signals PCB. Refer ADSP-TS20xS data sheet specification SCLK input jitter requirements. Single-stage dual-stage clock tree designs typically used create clock distribution network. Below couple examples these types designs.
Recommended
Recommended
Figure-10: Duty-cycle impact Vdd/2 SCLK_VREF Other factors consider: When selecting components, output-to-output skew between various clock buffer outputs should small possible ensure high speed operation external interface. Make sure output rise fall times clock drivers symmetrical. Review power supply grid supply decoupling clock generation components. Signal integrity analysis should clock signals ensure external coupling they meet exceed SCLK specifications.
Dual-Stage
Single-Stage
CLK1
CLK1
CLKGEN
CLKn
CLKn
Reset Pins
There four external pins /RST_IN, /RST_OUT, /POR_IN /TRST associated with reset circuitry ADSP-TS20xS. Three pins /RST_IN, /RST_OUT /POR_IN associated with resetting core internal DRAM. These pins must configured shown Figure-11 below. /TRST JTAG Emulator reset pin. recommends designers place resistor between /RST_OUT /POR_IN. This provides useful place connecting trigger logic-analyzer oscilloscope debugging potential system problems.
Figure-9: Clock Generation Examples most instances single stage clock designs provide lower jitter specifications tighter duty-cycle control than dual multi-stage clock designs. very important simulate designs, however dual multi-stage designs require special attention when analyzing total jitter (OSC jitter jitter) duty cycle impact. some cases jitter additive, therefore jitter jitter could result total peak-to-peak jitter. some products, however, some input jitter filtered resulting only fraction input jitter being added inherent jitter. Designers should review manufacturer data sheets application notes before choosing Oscillators, Crystals clock driver components ensure they meet jitter duty cycle requirements SCLK ADSP-TS20xS. important that designs using clock buffer special attention SCLK_VREF reference voltage. ADSP-TS20xS will work with 1.25 SCLK_VREF voltage, provided duty-cycle SCLK measured 1.25 better than 40/60. important note that duty cycle worsens SCLK_VREF voltage below above VDD(clock supply)/2 clock signal shown following diagram. therefore best SCLK_VREF voltage 1.65 maintain best possible duty cycle when using clock source.
RESET CIRCUIT
/RST_IN /RST_OUT
/RST_IN /RST_OUT
/POR_IN /POR_IN
Figure-11: Hardware Reset Connections /RST_IN chip hardware reset pin, /RST_OUT delayed synchronized internal version /RST_IN /POR_IN used reset internal DRAM. multiprocessor designs, /RST_IN signal must connected devices provide common reset sequence. Each processor should connect /RST_OUT /POR_IN pin.
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required that circuit supplying /RST_IN should hold signal asserted (low) when power supply ramping stable value. TS20xS four types resets; Power-Up Reset, Normal Reset, DSP-Core Reset JTAG/Emulator Reset. DSP-Core Reset: When setting SWRST register EMUCTL, core reset, external ports I/O. This sometimes referred software reset. /TRST Boundary Scan Emulator Reset: /TRST reset only resets IEEE 1149.1 Boundary Scan port also provides reset signal Emulator interface. This signal requires special considerations Emulator Boundary Scan port being used. table below outlines some possible Boundary Scan Emulator configurations describes necessary logic required control /TRST Boundary Scan Emulator operation. column describes whether Boundary Scan implemented, column indicated whether there Boundary Scan Controller PCB, column describes Emulator supported column indicates /TRST connection. Boundary Scan Boundary Scan Controller Emulator Support /TRST Connection
Power-Up Reset:
During power-up, while supplies ramping nominal value, /RST_IN must asserted (low) must remain minimum after supplies stable. addition, SCLK must running stable least after supplies stable before /RST_IN de-asserted. strap test mode pins sampled SCLK cycles after /RST_IN de-asserted. Refer ADSP-TS201S TigerSHARC Embedded Processor Data Sheet exact timing when theses pins latched.
Supplies Stable DD_I
/RST_IN /RST_OUT deasserted deasserted ~1.5
2.5V /RST_IN 2.0V /RST_OUT
SCLKstarts after supplies stable
SCLK
DD_DRA
1.5V
1.0V
DD_A
4.7K 4.7K Note Note Note Note
Figure-12: Power-up Reset Timing Diagram Normal Reset Normal Reset defined chip reset (assertion /RST_IN) following initial Power-Up Reset. supplies, SCLK other signals must stable.
SCLK Supplies Stable 2.5V VDD_IO /RST_IN SCLK /RST_OUT 1.0V VDD/VDD_A /RST_IN asserted (min) /RST_OUT de-asserted ~1.5
Table-14: Boundary Scan Emulator Configuration
2.0V VDD_DRAM
1.5V
Figure-13: Normal Reset Timing Diagram
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Note This section covers designs where TS20xS Emulator needed Boundary Scan interface being used board-level testing. external Boundary Scan board tester does boardlevel testing connections done through special test pads located PCB. Most designs typically have 5-pin Boundary Scan interface, however, some Boundary Scan testers only support 4-pin interface outlined figures below. designs using 4-pin interface, Power-On-Reset signal, show below /TRST_POR, required drive TS20xS /TRST ensure proper operation TS20xS Boundary Scan interface. /TRST_POR signal should held least SCLK cycles after power-supplies stable. During this time /RST_IN signal must asserted. /TRST_POR timing diagram below shows proper relationship between power supplies, SCLK /TRST.
CHIP-1 /TRST Boundary Scan supply BTDI BTCK BTMS /BTRST
CHIP-1 /TRST
SCLK Supplies Stable
/TRST_POR /TRST (min)
/RST_IN
100-SCLKs (min)
Figure-16: /TRST_POR timing diagram Note This section covers designs where TS20xS Emulator needed Boundary Scan interface connected on-board Boundary Scan test controller. this configuration Power-OnReset signal required meet requirements TS20x's /TRST pin. Power-On-Reset signal same timing (/TRST_POR) Note above. Boundary Scan sequence must start after de-assertion /TRST_POR. Shown below signal connections this configuration.
TS201S-1
/TRST /EMU
CHIP-N
/TRST
TS201S-1 /TRST /EMU
CHIP-N /TRST
BTDO Buffer 74AC11244 (3.3V) Equivalent Pads Board Level Boundary Scan Tests
Control Interface
On-Board Boundary-Scan Controller
BTDI BTCK BTMS /BTRST BTDO
Figure-14: 5-Pin Boundary Scan interface board tester
CHIP-1 /TRST Boundary Scan supply BTDI BTCK BTMS BTDO Buffer 74AC11244 (3.3V) Equivalent Pads Board Level Boundary Scan Tests er-On-Reset (/TRST_POR) TS201S-1 /TRST /EMU CHIP-N /TRST
/TRST er-On-Reset(/TRST_POR)
Figure-17: On-board Boundary Scan controller Emulator) Note This section covers designs where TS20xS Emulator needed Boundary Scan interface being used boundary scan. external Boundary Scan board tester does board-level testing connections done through special test pads located PCB. this configuration, jumper pins needed Emulation Header must inserted when Boundary Scan executed. jumper pins removed when using emulator. Another approach would 3-state buffers Muxes select between boundary scan pads emulation header selecting Boundary Scan signals TS20xS. Below implementation example, make sure buffer signals. Refer Analog Devices JTAG Emulation Technical Reference (EE68) additional information.
/TRST
Figure-15: 4-Pin Boundary Scan interface board tester
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Insert Jumpers JTAG Remove jumpers Emulator pin)
/EMU
BTMS
DSP's Buffers
EE-68 recommends that multi-processor systems, signals TigerSHARC processors should driven separate buffers order monotonic fast rising falling edges these pins. This allows faster clocks which results faster emulator throughput. version emulator support TCLK speeds MHz. some designs possible reduce number buffers combining several devices TCKs single buffer. this case, signals must properly simulated ensure monotonic (glitch-free) signal with fast rising falling edges must have edge rates less than 3-4ns. This makes possible emulator connection. Please ensure that there enough "keep-out" space around Emulator connector that emulator easily connected board.
BTCK pads Boundary scan
/BTRST
/TRST
BTDI
Figure-18: Emulator with external Boundary Scan controller Note This section covers design where TS20xS Emulator needed Boundary Scan interface connected on-board Boundary Scan test controller. this configuration Power-On-Reset signal required meet requirements TS20xS /TRST pin. Power-On-Reset signal same timing (/TRST_POR) Note above. example below, used select between Emulation header On-Board Boundary Scan controller.
ulator Header /EMU BTDI BTCK BTMS /BTRST BTDO
BTDI BTCK BTMS /BTRST BTDO
/TRST
HPPCI users
designs that will ADI's Circuit Emulator (ICE), aware that signals needs buffered properly. During initial setup user programmed various clock speeds from slow faster rate max. Fast edges skew between TCK's needed ensure optimal emulator performance. Refer application note EE-68 more details. careful clock buffers, which contain PLL; example zero-delay buffers. stop during certain conditions. This will cause severe problems design uses PLL-based buffering method. Therefore, users should based buffering method instead traditional buffers.
TS201S-1
TS201S-N
/TRST
/TRST
/EMU
/EMU
External Ports Pins
ulatorEn
er-On-Reset (/TRSTPOR)
On-Board JTAG Controller
Figure-19: Emulator with on-board JTAG controller
Boundary Scan Emulator Pins
ADSP-TS20xS pins associated with Boundary Scan Emulator interface. pins, /EMU, TCK, TDI, TDO, /TRST should connected Boundary Scan connector ADSP-TS20xS emulator used. detailed updated information this subject, please refer engineering note Analog Devices JTAG Emulation Technical Reference (EE-68) [4].
single-processor system, ID2-0 pins single processor must "000". multi-processor system, processor must uniquely assigned starting from "000" "111"; single TigerSHARC cluster gluelessly support DSPs. both single multiple processor topologies, imperative include processor ID2-0 "000" system, since this processor supports following features upon reset: active internal pull-ups pull-downs certain external signals when ID2-0= "000" (DSP ADSP-TS201S TigerSHARC Embedded Processor Data Sheet details.
ADSP-TS201S TigerSHARC® System Design Guidelines (EE-179)
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default master, therefore provide active arbitration signals external host processor. on-chip SDRAM controller, which provides sequence external SDRAM present system. Name LxDATAO30P/N LxCLKOUTP/N LxACKI /LxBCMPO Connection Link Partner Link Partner Link Partner Link Partner;
there external host cluster common data shared between host TigerSHARC processor(s), endianess both sides must matched each other. Note, TigerSHARC processor only little endian does support endian. TigerSHARC processor's addressing word-oriented (32-bit). Some host processors' addressing byteoriented. Therefore, connecting these processors least-significant TigerSHARC processor's address should connected third least-significant host processor's address bus, regardless 32-bit 64-bit width specified. address data busses float several cycles during bus-mastership transitions between TigerSHARC processor host. Floating this case means that these inputs driven source. ADSP-TS20xS contains internal pull-up resistors ensure busses don't float under these conditions. either host external memory widths configured 64-bits, then multiprocessing memory space must configured 64-bits well. external wait-state mode used, please ensure that contention signal occurs.
Table-15: 4-bit Transmit Link Port
Name LxDATAO31P/N LxDATAO0P/N LxCLKOUTP/N LxACKI /LxBCMPO
Connection Link Partner Link Partner Link Partner Link Partner;
Table-16: 1-bit Transmit Link Port
Name LxDATAO30P/N LxCLKOUTP/N LxACKI /LxBCMPO
Connection
Link Ports Pins
ADSP-TS201S ADSP-TS202S contain four full duplex Link port whereas (ADSP-TS203S) contains only full duplex Link Ports. Each link port's receive transmit sections operate independently used connected other link partners. link ports used then link port pins must connected between link partners. only exception 1-bit data mode operation. Refer following sections connecting terminating transmit receive link port. Transmit Link Port Connections Transmit link port connections should follow guidelines tables below. Note that /LxBCMPO pins transmit link ports used test mode straps. Refer test mode strap section details. cases where only data transmit signal pair used, remaining transmit pairs should left unconnected.
Table-17: Unused Transmit Link Port Refer Test Mode strap section information providing pads optional resistor placement system debug. Receive Link Port Connections Receive link port connections should follow guidelines tables below. receive link port used, pins must connected with exception data pins when using 1-bit wide data port. Each LVDS receive pair which connected link partner requires external terminating resistor. These resistors must placed close receiving link port pins possible.
ADSP-TS201S TigerSHARC® System Design Guidelines (EE-179)
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1%External LVDSTerminating Resistor
Using Connectors Link Port Communication Some applications require either daughter-cards cable connectors communications between link ports separate systems. This requires special considerations inputs when cable perhaps daughter-board used plugged following guidelines should followed when using connectors: LxDATAO3-0P/N, LxCLKOUTP/N, LxBCMPO LxACKO; these outputs should connected connector left unconnected used (for example using only 1-bit data). LxDATAI3:0P/N LxCLKINP/N; these differential inputs require input termination resistor located close receiver pins they used. LxACKI; this signal internal pull-down resistor. special requirements needed. /LxBCMPI; this signal internal pull-up resistor. special requirements needed.
Routing
LVDS
LVDS
Link Transmitter
Link Receiver
Figure-20: LVDS Receive Termination
Name LxDATAI3-0P/N LxCLKINP/N LxACKO /LxBCMPI
Connection Link Partner Link Partner Link Partner Link Partner
Terminatio Resistor
Table-18: 4-bit Receive Link Port
Name LxDATAI3-1P/N LxDATAI0P/N LxCLKINP/N LxACKO /LxBCMPI
Connection VDD_IO Link Partner Link Partner Link Partner Link Partner
Terminatio Resistor
Link Port LVDS Guidelines
traces should optimized differential impedance. Connections should point-to-point from Link Port source Link Port destinations. Trace lengths should matched minimize skew. trace lengths should mils. This limits trace delays high-speed 4-bit Link Port operation, place Link Port clock signals between four sets LVDS data signals
Table-19: 1-bit Receive Link Port
Name LxDATAI3-0P/N LxDATAI0P/N LxCLKINP/N LxACKO /LxBCMPI
Connection VDD_IO VDD_IO VDD_IO
Terminatio Resistor
Plane
Figure-21: 4-Bit Link Port Clock placement Minimize number vias. Vias reduce signal integrity. Additional stub length cause unwanted reflections. signals vias between LVDS pairs.
Table-20: Unused Receive Link Port
ADSP-TS201S TigerSHARC® System Design Guidelines (EE-179)
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Supply/Gnd plane
Supply/Gnd plane
LVDS PAIR SIGNAL Recommended
LVDS PAIR Recommended
LVDS PAIR
SIGNAL
SIGNAL
LVDS PAIR
SIGNAL
Recommended
Recommended
Figure-22: Signals Between LVDS signal place closely spaced signals vias between adjacent LVDS pairs unless careful analysis done.
Plane
LVDS PAIR
SIGNAL
LVDS PAIR
SIGNAL
Recommended
Recommended
Figure-25: Signals above/below LVDS signals
LVDS PAIR SIGNAL LVDS PAIR
Recommended
Figure-23: Signals Between LVDS pairs degrees angles LVDS routing. 45degree bends maintain constant width space between LVDS pairs spacing between adjacent LVDS pairs.
LVDS PAIR degrees recommended
Place LVDS differential signals bottom layer possible. solid supply ground plane directly underneath LVDS signals also required. This configuration typically referred "MicroStrip".
Supply/Gnd Plane
ground Planes
LVDS PAIR
"MicroStrip"
Figure-26: MicroStrip Example
degrees recommended
Figure-24: 90-Deg Angles LVDS signals signals under above LVDS pairs.
placement LVDS signals possible bottom layers PCB, acceptable sandwich LVDS layers between supply and/or ground planes. This configuration referred "StripLine".
"StripLine"
LVDS PAIR
Figure-27: StripLine Example
ADSP-TS201S TigerSHARC® System Design Guidelines (EE-179)
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Although StripLine topology significantly reduces EMI, does have some drawbacks. Difficulty maintaining constant impedance Higher propagation delay times) require additional vias layers
(Supply Ground Plane)
recommended that supply and/or ground plane extend past edges LVDS signals.
Supply/Gnd Plane
Stripline (Supply Ground Plane)
Figure-31: StripLine guidelines Width trace Space between LVDS pair. Distance between LVDS pairs Space ground supply plane edge Distance neighboring supply trace Height between signal next layer Note: following Ratios also required. Optimize differential impedance
LVDS PAIR
Figure-28: Supply Plane overlap LVDS signal Non-LVDS (single ended) signal must same plane LVDS signals, ground supply trace should inserted between LVDS signal Non-LVDS signal.
Supply/Gnd Plane
LVDS PAIR
Booting
understand booting process each boot modes further detail, please refer TigerSHARC processor engineering note ADSP-TS20x TigerSHARC Processor Boot Loader Kernels Operation (EE-200) [8]. After reset, ADSP-TS20xS four boot options beginning operation: EPROM Boot, Host Boot, Link Port Boot, Boot.
Figure-29: LVDS signal LVDS distance Below some industry standard guidelines LVDS signal routing.
LVDS Pair LVDS Pair
EPROM Boot:
Master Boot Mode, TigerSHARC processor starts actively fetching externally. ADSP-TS20xS processor defaults EPROM booting depending value /BMS strap pin. When processor configured boot from EPROM, /BMS active during boot sequence should connected chip select signal EPROM. additional information refer /BMS strap section.
Microstrip (Supply Ground Plane)
Figure-30: MicroStrip guidelines
ADSP-TS201S TigerSHARC® System Design Guidelines (EE-179)
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Host Boot:
Slave Boot Mode: TigerSHARC processor expects code placed internally. ADSP-TS20xS processor supports booting from external master (host another ADSP-TS20xS). master cluster boot ADSPTS20xS through writes internal memory through auto DMA. host boot, place resistor between /BMS VDD_IO. Link Port Boot: Slave Boot Mode: TigerSHARC processor expects code placed internally. four receive link port channels initialized after reset transfer 256-word block internal memory addresses through 255, issue interrupt block (similar external port DMA). corresponding interrupts address zero. additional information refer /BMS TMR0E strap sections. Link Port boot place resistor between /BMS VDD_IO. Boot: Master mode: TigerSHARC processor will start from vector (externally internally) fetching data. ADSP-TS20xS processor will begin execution from memory address selected with /IRQ3-0 interrupt signals. Using boot' option, ADSP-TS20xS will start running from memory when interrupts asserted. additional information refer /BMS strap sections. boot (boot from memory address) place resistor from VDD_IO resistor from /BMS VDD_IO. other pins, which used design listed tables below, should left unconnected. Unconnected pins DSP-ID following table outlines connections pins, which used DSP-ID [0]. Signal Name /BR7-1 /BOFF /HBR /DMAR3-0 SDCKE /TRST LxDATAI3-0P/N LxCLKINP LxCLKINN /LxBCMPI Connection VDD_IO VDD_IO VDD_IO VDD_IO Pull-down VDD_IO VDD_IO VDD_IO
Table-21: Unconnected pins DSP-ID
Unconnected pins
This section outlines signal pins that used design. Although ADSP-TS20xS included lots internal pull-ups pull-downs save external resistors and/or supply connections, some still required. Listed below sections which outline what connections (pull-ups, pull-downs supply connections) required when DSP-ID when DSP-ID ADSP-TS201S TigerSHARC® System Design Guidelines (EE-179) Page
Unconnected pins DSP-ID [1-7] following table outlines connections pins, which used DSP-ID [1-7]. Signal Name /WRL /WRH /BR7-1 /BOFF /BUSLOCK /HBR /HBG /CPA /DPA /DMAR3-0 /MSSD3-0 /RAS /CAS SDCKE /SDWE /BRST /TRST LxDATAI3-0P/N LxCLKINP LxCLKINN /LxBCMPI Connection Pull-up Pull-up Pull-up Pull-up VDD_IO input), output) VDD_IO (Strap pin) VDD_IO Pull-up Pull-up Pull-up VDD_IO Pull-up Pull-up Pull-up Pull-down Pull-up Pull-up VDD_IO VDD_IO VDD_IO
Miscellaneous Items
important signal integrity analysis signals single multiprocessor ADSPTS20xS based systems.
Table-22: Unconnected pins DSP-ID [1-N] figure below shows ADSP-TS201S/ADSP-TS202S package with supplies, grounds, configuration, straps, NC-pins, voltage reference pins, link port pins, address data pins. figure intended provide guidance floor planning, signal routing initial bypass capacitor placement.
ADSP-TS201S TigerSHARC® System Design Guidelines (EE-179)
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ADSP-TS201S 576-BGA CONFIGURATION (TOP VIEW)
DATA[63:0]
ADDR[31:0]
LINK0-RX LINK0-TX
LINK1-RX
LINK1-TX
LINK3-TX LINK3-RX LINK2-TX LINK2-RX BOUNDARY SCAN VDD-IO VDD-DRAM VDD-A VREF SCLK_VREF SCLK SIGNAL CONFIG STRAP
Test DD_IO Test
Test PinNC
Figure-32: ADSP-TS201S ADSP-TS202S package
ADSP-TS201S TigerSHARC® System Design Guidelines (EE-179)
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References
ADSP-TS201S TigerSHARC Embedded Processor Data Sheet, Analog Devices, Inc. ADSP-TS201S TigerSHARC Processor Hardware Reference, Analog Devices, Inc. ADSP-TS201S TigerSHARC Processor Programming Reference, Analog Devices, Inc. Analog Devices JTAG Emulation Technical Reference (EE-68), Analog Devices, Inc. Estimating Power ADSP-TS201S (EE-170), Analog Devices, Inc. Thermal Relief Design ADSP-TS201S TigerSHARC Processor (EE-182), Analog Devices, Inc. User Guide ADSP-TS201S TigerSHARC processor IBIS files (EE-198) ADSP-TS20x TigerSHARC Processor Boot Loader Kernels Operation (EE-200), Analog Devices, Inc. Considerations porting code from ADSP-TS101S TigerSHARC processor ADSP-TS201S TigerSHARC processor (EE-205), Analog Devices, Inc.
Document History
Version 2003 John Phil October 2003 Phil Description Discussing Silicon
Revised title from ADSP-TS201S TigerSHARC System Design Guidelines ADSP-TS20xS TigerSHARC System Design Guidelines First released version
October 2003 Greg John Phil
ADSP-TS201S TigerSHARC® System Design Guidelines (EE-179)
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