9106 P.O. NORWOOD, MASSACHUSETTS 02062-9106 617/32

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9106 P.O. NORWOOD, MASSACHUSETTS 02062-9106 617/32

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AN-413 APPLICATION NOTE
9106
P.O.
NORWOOD,
MASSACHUSETTS 02062-9106
617/329-4700
Evaluation Board AD7890, 12-Bit Serial, Data Acquisition System
Albert O'Grady
INTRODUCTION This application note describes evaluation board AD7890 12-bit serial data acquisition system. AD7890 eight-channel 12-bit data acquisition system which operates from single supply contains input multiplexer, on-chip track-and-hold amplifier, high speed 12-bit ADC, reference high speed serial interface. AD7890 accepts analog input range 4.096 +2.5 depending version part being used.
78L05
CLKIN 74HC4050 DATA DATA 74HC125 SCLK DVDD DGND CONVST 120pF CONVST CEXT AGND AGND DGND 74HC125 SCLK SMODE VIN2 VIN1 VIN4 VIN3 CLKIN DATA REFOUT/ REFIN 0.1µF
part contains on-chip control register accessible serial port allows control channel selection, conversion start, power down part. This flexible serial interface allows AD7890 connect directly digital signal processors (ADSP-2101, TMS320C25, etc.) microcontrollers (8XC51, 68HC11, etc.). Full data AD7890 available AD7890 data sheet available from Analog Devices should consulted conjunction with this application note when using evaluation board.
10µF 10µF 0.1µF VIN8 VIN7 0.1µF 10µF 10µF AD713JN 0.1µF
AD780
VOUT
DATA
VIN6
AD7890
VIN5
Figure Evaluation Board Circuit Diagram
Onboard components include AD780, programmable +2.5 ultrahigh precision bandgap reference, buffers serial data lines input buffer amplifiers buffer eight analog inputs. Interfacing this board through 9-way D-type connector. External sockets provided conversion start input, analog inputs, out, external reference input options. OPERATING AD7893 EVALUATION BOARD Power Supplies This evaluation board three analog power supply inputs: AVDD, AGND VSS. These supplies respectively used power onboard AD713 buffer amplifiers. supply used conjunction with LM78L05, linear regulator, provide AD7890 AD780 voltage reference. There digital power supply inputs, DVDD DGND, that used power digital logic board. These supplies provided through D-type connector through connection pins labelled board. supplies decoupled ground with tantalum ceramic disc capacitors. AVDD supplies decoupled AGND plane while DVDD supply decoupled DGND plane. evaluation board uses extensive ground planing minimize high frequency noise interference from onboard clocks other sources. Once again, ground planing analog section kept separate from that digital section they joined only AD7890 AGND DGND pins. Shorting Plug Options There five shorting plug options that must before using evaluation board. These outlined below: This double link used configure bidirectional buffer SCLK inputs AD7890. position this link also controls SMODE AD7890 configuring part self-clocking external clocking mode operation. external clocking mode both links must Position setting SMODE AD7890 logic high routing SCLK signals from 9-way D-type connector AD7890. self-clocking mode both links must Position configuring SMODE AD7890 logic routing SCLK output signals from AD7890 9-way D-type connector.
This option used select reference source AD7890 REFIN/REFOUT pin. With this link Position on-chip reference used reference AD7890. output impedance this reference allowing this reference overdriven when using external reference. Position AD780 reference selected reference AD7890. Position reference part provided from external socket SKT9. This link, when place, connects When this link removed, output multiplexer appears also (SKT12), thus user insert antialiasing filter signal conditioning between multiplexer ADC. output range from output impedance input on-chip track hold high impedance input accepts signals range driven directly from SKT13 with removed. This provides options each analog input channels. Option selects analog input each channel from external socket. second option facilitates grid signal conditioning signal linked VIN. following table describes options associated with LK4. Table Options Associated with Option Function Grid VIN1 buffer amplifier SKT1 VIN1 buffer amplifier Grid VIN2 buffer amplifier SKT2 VIN2 buffer amplifier Grid VIN3 buffer amplifier SKT3 VIN3 buffer amplifier Grid VIN4 buffer amplifier SKT4 VIN4 buffer amplifier Grid VIN5 buffer amplifier SKT5 VIN5 buffer amplifier Grid VIN6 buffer amplifier SKT6 VIN6 buffer amplifier Grid VIN7 buffer amplifier SKT7 VIN7 buffer amplifier Grid VIN8 buffer amplifier SKT8 VIN8 buffer amplifier
This link place connects together useful applications which require that data transmitted received same time.
EVALUATION BOARD INTERFACING Interfacing evaluation board 9-way D-Type connector, SKT14. pinout this connector shown Figure designations given Table
DVDD
Digital Supply. This line connected DVDD supply line evaluation board. allows user provide digital supply connector along with other digital signals.
SKT14 DESCRIPTION SCLK Serial Clock Input/Output. external clocking mode (LK1 Position external serial clock applied through this input load data control register access data from output register. self-clocking mode (LK1 Position internal serial clock used load data control register access data from data register. This clock appears SCLK pin. internal serial clock derived from master clock. This serial clock buffered using 74HC125 three-state buffer evaluation board determines direction this bidirectional buffer depending mode operation. Receive Frame Sync. This input output depending mode operation. external clocking mode this used provide active framing pulse access data from data register. self-clocking mode active framing pulse which internally generated part appears this pin. This signal buffered board using 74HC125 three-state buffer configured bidirectional operation using LK1. Transmit Frame Sync. This buffered input controls AD7890 input, serial data expected after falling edge this signal. There pull-up resistor this line pull inactive state left unconnected. This buffered input used provide serial data loaded control register AD7890. Digital Ground. This line connected digital ground plane evaluation board. allows user provide digital supply connector along with other digital signals.
Figure Configuration SKT14, D-Type Connector
Table SKT14 Functions Mnemonic SCLK DATA DGND DATAOUT DVDD
SOCKETS There fourteen sockets relevant operation AD7890 this evaluation board. functions these sockets outlined Table III. Table III. Socket Functions Socket SKT1-SKT8 SKT9 SKT10 SKT11 SKT12 Function Subminiature Sockets Eight Analog Input Channels Subminiature Socket External Reference Subminiature Socket CONVST Input Subminiature Socket Master Clock Input Subminiature Socket OUT. output on-chip multiplexer appears this pin. Subminiature Socket Pin. input on-chip track/hold applied this socket. 9-Way D-Type Connector
DATA
DGND
SKT13
SKT14
DATAOUT Serial Data Output. Serial data from part obtained this output. This data buffered 74HC4050 buffer before arriving DATAOUT connector. serial data clocked rising edge SCLK valid falling SCLK.
SET-UP CONDITIONS Care should taken before applying power signals evaluation board ensure that link positions required operating mode. Figure shows silkscreen layout board order ease setup. following required link positions modes operation. External Clocking Mode Both links Position configuring both SCLK inputs. This link selects reference input placed positions. A-internal reference, B-AD780, C-external reference from SKT9. This should place connecting There should link inserted each following positions connect analog inputs from SKT1 SKT8 their respective input, This link place applications that require data transmitted received same time, i.e., ties together. this facility required then link omitted. Internal Clocking Mode Both links Position configuring both SCLK outputs. other links configured external clocking mode described above. CONTROLLING AD7890 There modes (external clocking selfclocking) operation applicable AD7890 selected SMODE which controlled from evaluation board. Channel selection controlled through 5-bit control register which accessible through serial port (SKT14). This control register contains three bits channel address, software conversion start part into sleep mode. There methods initiating conversion AD7890, software conversion start hardware conversion start which applied through conversion start input (SKT10). rising edge this CONVST input puts track/hold into hold mode conversion initiated. conversion time part determined from clock signal applied (SKT11) board. With master clock, conversion time AD7890 from rising edge CONVST signal. required track/ hold acquisition time. internal pulse generated appears CEXT whenever multiplexer address loaded AD7890 control register, duration will depend value CEXT used. applications where multiplexer switched conversion initiated same time capacitor should connected CEXT allow acquisition time track/hold before conversion initiated.
Software conversion starts initiated writing logic CONV control register. internal pulse conversion process initiated after sixth serial clock cycle write cycle written CONV bit. With CONV external CONVST input disabled. Writing CONV control register enables external convert start. External Clocking Mode AD7890 configured external clocking mode tying SMODE device logic high (LK1 evaluation board Position this mode, SCLK AD7890 configured inputs. This external clocking mode designed direct interface systems which provide serial clock output which synchronized serial data output including microcontrollers such 80C51, 87C51, 68HC11 68HC05 most digital signal processors. Figure shows timing control sequence required obtain optimum performance from part external clocking mode. sequence shown Figure conversion initiated rising edge CONVST, data available output register AD7890 later. Once read operation taken place, further should allowed before next rising edge CONVST optimize settling track/hold before next conversion initiated. diagram shows read operation write operation taking place parallel. sixth falling edge SCLK write sequence, internal pulse will initiated. Assuming connected required between this sixth falling edge SCLK rising edge CONVST allow full acquisition time track/hold amplifier. With serial clock rate maximum MHz, achievable throughput rate part (conversion time) plus (six serial clock pulses before internal pulse initiated) plus (acquisition time). This results minimum throughput time (equivalent throughput rate kHz). part operated with slower serial clock, will impact achievable throughput rate. Applications that want achieve optimum performance from AD7890 will have ensure that data read does occur during conversion during prior rising edge CONVST. This achieved either ways. first ensure software that read operation initiated until after rising edge CONVST. This will only possible software knows when CONVST command issued. second scheme would CONVST signal both conversion start signal interrupt signal. simplest this would generate square wave signal CONVST with high times (see Figure Conversion initiated rising edge CONVST. falling edge CONVST occurs later used either active falling edge-triggered interrupt signal tell
processor read data from AD7890. Provided read operation completed before rising edge CONVST, AD7890 will operate specification. This scheme limits throughput rate 11.8 minimum. Self-Clocking Mode AD7890 configured self-clocking mode tying SMODE device logic (LK1 board position this mode, AD7890 provides
serial clock signal serial data framing signal used transfer data from AD7890. This selfclocking mode used with processors that allow external device clock their serial port including most digital signal processors. Interface timing obtained from AD7890 data sheet.
CONVST
SCLK
tCONVERT
500ns
CONVERSION INITIATED TRACK/HOLD GOES INTO HOLD
CONVERSION ENDS 5.9µs LATER
SERIAL READ WRITE OPERATIONS
READ WRITE OPERATIONS SHOULD 500ns PRIOR NEXT RISING EDGE CONVST
NEXT CONVERSION START COMMAND
Figure Control Sequence Obtain Optimum Performance from AD7890
CONVST
SCLK
tCONVERT
500ns
CONVERSION INITIATED TRACK/HOLD GOES INTO HOLD
CONVERSION ENDS 5.9µs SERVICE POLLING LATER ROUTINE
SERIAL READ READ WRITE NEXT CONVST WRITE OPERATIONS SHOULD RISING EDGE OPERATIONS 500ns PRIOR NEXT RISING EDGE CONVST
Figure Sequence Using CONVST Interrupt Signal
COMPONENT LIST Integrated Circuits IC4, Capacitors C12, C11, C13, C17,
Resistors AD7890 AD780 Voltage Reference AD713 Buffer Amplifier LM78L05 Voltage Regulator 74HC4050 Buffer 74HC125 Quad Buffers with Three State Outputs Capacitors Capacitors Capacitors Capacitor Links LK1, LK2, LK3, LK4, Sockets SKT1 SKT13 SKT14
Resistors Shorting Plugs
Subminiature Sockets 9-Way Type Connector
E2136-12-5/96
Figure Silkscreen Layout Evaluation Board
PRINTED U.S.A.

9106 P.O. NORWOOD, MASSACHUSETTS 02062-9106 617/32

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