Technical Notes using Analog Devices' components development tools

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Technical Notes using Analog Devices' components development tools

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Technical Notes using Analog Devices' components development tools
Phone: (800) ANALOG-D, FAX: (781) 461-3010, EMAIL: dsp.support@analog.com, FTP: ftp.analog.com, WEB: www.analog.com/dsp Copyright 1999, Analog Devices, Inc. rights reserved. Analog Devices assumes responsibility customer product design application customers' products infringements patents rights others which result from Analog Devices assistance. trademarks logos property their respective holders. Information furnished Analog Devices Applications Development Tools Engineers believed accurate reliable, however responsibility assumed Analog Devices regarding technical accuracy content provided Analog Devices' Engineer-to-Engineer Notes.
Considerations FLASH PROMS with Timing Requirements
H.D.
Attached waveform 21065L from digital scope that should help make this clear.
Question:
need know minimum time between rising edge /RESET falling edge /BMS when EBOOT high LBOOT low. This parameter important since flash PROMS also have /RESET input minimum timing requirement between rising edge /RESET falling edge /OE. need implement early /RESET flash PROM, until know soon SHARC asserts /BMS, don't know much earlier PROM needs reset.
Answer:
following applies only 21060/60L, 21062/62L 21061/61L: first cycle that RESET deasserted (goes high) cycle then will asserted LOW) cycle following applies only 21065L: first cycle that RESET deasserted (goes high) cycle then will asserted LOW) cycle Note: cycle defined CLKIN cycle. CLKIN 30MHz, cycle 33.3ns length.

Technical Notes using Analog Devices' components development tools

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