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EE-167
Technical Notes using Analog Devices' components development tools
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Introduction TigerSHARC® Multiprocessor Systems Using VisualDSP++Contributed Maikel Kokaly-Bannourah April 2003
Introduction
following Engineer-to-Engineer note intended give introduction Multiprocessor (MP) systems using VisualDSP++. explanation will based assembly code written ADDS-TS101S EZ-Kit Lite, consisting TigerSHARC® Processors, using VisualDSP++ 3.0. TigerSHARC® Multiprocessor systems configured different ways: Several processors sharing external Link Port point-to-point communication This note will discuss implementation system with processors sharing external bus. more details other implementations please refer TigerSHARC® Processor Hardware Reference. addition assembly code explored throughout this note, code example written also available.
memory. following commands must considered when writing LDF: MPMEMORY{}, defines each processor's offset within multi-processor memory space (MMS). linker uses offsets during multiprocessor linking. MEMORY{}, defines memory processors present system. PROCESSOR{} SECTIONS{} commands define each processor place program sections each processor's output file, using memory definitions. SHARED_MEMORY{}, needed when external shared memory used system. This command identifies output shared memory items generates Shared Memory executable files (.SM) that reside shared memory system. file generated from source code file (.ASM, .CPP), which must included with project files. This file contains variable definitions data that will placed external shared memory. LINK_AGAINST(), resolves symbols within multiprocessor memory directs linker check specified executables (.DXEs .SMs) resolve variables labels that have been resolved locally. Whenever expressions variables defined (i.e. internal memory another processor system) LINK_AGAINST() command must used LDF.
Linker Description File (LDF) Systems
very first step setting system create multiprocessor project using multiprocessing capabilities linker, file describe system. describes multiprocessor memory offsets, shared memory, each processor's
Copyright 2003, Analog Devices, Inc. rights reserved. Analog Devices assumes responsibility customer product design application customers' products infringements patents rights others which result from Analog Devices assistance. trademarks logos property their respective holders. Information furnished Analog Devices Applications Development Tools Engineers believed accurate reliable, however responsibility assumed Analog Devices regarding technical accuracy topicality content provided Analog Devices' Engineer-to-Engineer Notes.
Note: files files included command line, file must placed first, followed other DXE's, linker able resolve variables correctly. maximum number processors that declared architecture-specific (i.e. maximum ADSP-TS101S's). Also note that combination different DSPs with different architectures (i.e. ADSP-TS101S ADSP21160) same supported VisualDSP++.
Figure 1Excerpt from example
example where above commands used shown Figure remaining file basically same default provided with tools (please refer "Linker Utilities Manual TigerSHARC® DSPs" "EE-69 Understanding Using Linker Description Files (LDFs)" general description files).
Figure ADSP-TS101S external shared memory system defined that different sections have been discussed, examine example code that explores some capabilities processor. system hardware configuration please refer Cluster chapter TigerSHARC® Processor Hardware Reference.
Introduction TigerSHARC® Multiprocessor Systems Using VisualDSP++(EE-167)
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Multiprocessor (MMS) Memory Space
multiprocessor memory space divided into number address regions (this number processor specific) that correspond internal memory processors system. ADSP-TS101S's multiprocessor memory space appears Figure used other than special cases where data must pass through TigerSHARC® interface. Performing self-multiprocessor read access will SELF MPROC READ SYSTAT register error indication illegal access. Example shows source code where used access memory location another system. this case with accesses memory location ID1's internal memory.
Example
Code r0=0x02480000; //M0 Data
example address 0x2400000, which then added address corresponding ID1's internal memory (0x80000). Therefore, this will result read access from ID1's internal memory. Note: multiprocessor systems including SDRAM with ID=000 must present, since this performs initialization (MRS) SDRAM. Also, there issues related open drain pull-ups only enabled with ID=000. After reset, becomes master priority rotates round robin fashion, going from present master.
Figure ADSP-TS101S's Multiprocessor Memory Space.
Depending address range used, internal memory particular multiprocessor system will accessed source destination. Writes Broadcast region access memory DSPs multiprocessing system. instance, accessing memory location within address range 0x3000000 0x33FFFFF, equivalent accessing internal memory system with Note: TigerSHARC's® Internal space accessed multiprocessing space write transactions only. This, however, performed through external should
External Memory
ADSP-TS101S 6Mbits onchip SRAM memory that store both program data. However, some applications also require external memory devices. External memory widely used systems, implemented shared resource DSPs system, dedicated particular processor. very important keep mind that DSPs system must proper access mode type memory used hardware system. access mode
Introduction TigerSHARC® Multiprocessor Systems Using VisualDSP++(EE-167)
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programmed System Control (SYSCON) register. Default power up/reset settings SYSCON detailed TigerSHARC® Processor Hardware Reference. User defined settings must support access mode appropriate memory device(s) that user intends their hardware systems. SYSCON settings must same across devices sharing cluster connection. Note that SDRAM gluelessly supported ADSP-TS101S. with SYSCON register, SDRAM Configuration (SDRCON) register processors system must initialized same value. Once DSP's internal memory controller been configured, external memory accessed external bus. this project, SDRAM used external shared resource DSPs system. code shown example corresponds SDRCON register initialization, which, previously mentioned, must done DSPs sharing same external memory this case, ID1).
Example
Excerpt from ID1: SDRAM Init. 0x00005913;; SDRCON j11;; Enable SDRAM: ENA=1,CAS=2CL,pipedepth=0, page=512w,
Vector Interrupt (VIRPT)
Vector Interrupts used interprocessor communication between host between DSPs. This interrupt general-purpose interrupt another master's use. host master DSP) issue vector interrupt slave writing address interrupt service routine VIRPT register. When serviced, this high priority interrupt causes branch service routine that address.
Example
Extract from ID1: VIRPT Generation MMS_ID0 VIRPT_REG;; VIRPT_ISR_ID0 MMS_ID0;; j31]= xr0;;
example triggers vector interrupt writing address service routine served (labeled VIRPT_ISR_ID0) VIRPT register (0x2180730 0x180730 VIRPT address 0x2000000 ID0). Note: case external defined label used address (like this example, i.e. VIRPT_ISR_ID0), offset value serving interrupt (MMS_ID0) must subtracted vector address correctly. This just example inter-processor VIRPT interrupts used flags just indicate program execution completion systems.
Shared.asm contains variable definitions data that will placed external memory. Note: with lowest number (and therefore highest priority system) responsible initializing external data defined .ASM shared memory file during booting-up sequence.
Lock Semaphores
Semaphores useful synchronizing tasks performed system. semaphore flag, data memory location that accessed DSPs present system. critical tasks (i.e. should interrupted), when attempting read-modify-write operation
Introduction TigerSHARC® Multiprocessor Systems Using VisualDSP++(EE-167)
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semaphore, must have mastership duration operation. This achieved using DSP's lock feature, which retains mastership prevents other processors from simultaneously accessing semaphore. read-modify-write operation accomplished with following steps (example Request lock setting BUSLK BUSLK register. Wait mastership acquired (condition codes used). Read semaphore, write Example excerpt from ID0's code demonstrating Lock combination with Broadcast write:
Example
Excerpt code: BROADCAST write using Lock BUSLK j11;; Lock
must located same address each DSP. Once become master, performs broadcast write specified address every DSP, including itself. Lastly, BUSLK must cleared free after broadcast transfer finished.
Multiprocessor Data Transfers
Throughout code, several types external port (EP) data transfers have been implemented: Direct Memory Access (DMA) between ID1, from external memory (SDRAM), Core transfer from ID0, Broadcast Write DSPs system. TigerSHARC® includes channels, four which dedicated external memory devices: channels details DMAs different data transfers performed, please refer "EE-143 Understanding ADSP-TS101S TigerSHARC®" Controller chapter TigerSHARC® Processor Hardware Reference. Let's examine different types data transfers performed this specific project. Note that Broadcast Write already been discussed previous sections.
transfer from
BUS_MASTER: NBM, jump BUS_MASTER;; Check mastership DCS0 xr3:0;; MMS_Broadcast;; DCD0 yr3:0;; Perform Broadcast data transfer BUSLK j11;; Relinquish
While BUSLK set, determine acquired mastership executing conditional instruction with Master (NBM) condition code. become master, proceed with external read write. not, either clear BUSLK again later, simply wait until acquired. lock used combination with broadcast writes implement reflective semaphores multiprocessing system. reflective semaphore (i.e. located DSP's internal memory processor register)
This example shows transfer from internal memory internal memory ID1. this case, channel used transmit data stored tx_ID0 rx_ID1. this kind transmission, transfer control blocks (TCBs), source another destination, must
Introduction TigerSHARC® Multiprocessor Systems Using VisualDSP++(EE-167)
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Example shows loaded values into each using channel Note that value register xr2/yr2 irrelevant fact that 2-dimensional selected this particular example. soon both source destination TCBs loaded with values transfer starts. Once completed interrupt occurs _dma_ vector interrupt routine then run.
Example
Excerpt from ID0: DMA0 External Port transfer from tx_ID0;; xr0=index= 0x00100004;; count=0x10,modify=4 0x47000000;; mem,prio=norm, DCS0 xr3:0;; Source rx_ID1;; xr0=index= 0x00100004;; count=0x10,modify=4 0x87000000;; mem,prio=norm, DCD0 yr3:0;; Destination tx_ID1;; xr0=index= 0x00100004;; count=0x10,modify=4 0x47000000;; mem,prio=norm, DCS0 xr3:0;; Source shared_data+TAPS;; //xr0=index=SDRAM 0x00100004;; //count=0x10,modify=4 0x87000000;; //ext mem,prio=norm, DCD0 yr3:0;; Destination
from SDRAM
example this data transfer from internal memory this case from instead ID0) SDRAM. Again, same concepts apply, where source destination TCBs shown example Example
Excerpt from ID1: DMA0 External Port transfer from SDRAM
transfer from SDRAM
transfer data from internal memory SDRAM executed with minor alterations previous example. source loaded with same contents before (xR3:0) destination written with values registers yr3:0 where altered from rx_ID1 shared_data. this case, channel used data transfer replacing DCS0 DCD0 with DCS1 DCD1 respectively.
Example
Excerpt from ID0: DMA0 Port transfer from SDRAM DCS1 xr3:0;; Same before shared_data;; xr0=index= SDRAM DCD0 yr3:0;; Destination
source loaded with same contents before (xR3:0) with only variation that index points internal memory ID1, tx_ID1. destination written with values registers yr3:0 where points shared_data+TAPS. TAPS offset value used point second half buffer declared SDRAM prevent from overwriting already transferred data ID0. Once again, channel used.
Core transfer from
Core transfer different handling data where used. this case, Integer Arithmetic Logic Unit (IALU) used directly transfer data from internal memory internal memory ID0. example this shown below:
Example
Excerpt from ID1: Core transfer from using IALU tx_ID1;; Base address jB0;; index equals base TAPS;; buffer length
Note: writing active TCB, i.e. back-toback using same channel before current transfer completed, results illegal operation. error indication will flagged status register (DSTAT).
Introduction TigerSHARC® Multiprocessor Systems Using VisualDSP++(EE-167)
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rx_ID0;; Base register jB1;; index equals base TAPS;; buffer length TAPS;; write_ext: loop modifier loop counter CB[j0 j4];; read data from tx_ID1 CB[j1 xr0;; write data rx_ID0
false, will enter endless loop indicating that error occurred.
Multiprocessor Support
Debugger
NLC0E, jump write_ext;; keep looping until completion
data arrays declared, each DSP's internal memory. writes array stored through (tx_ID1 rx_ID0). IALU registers used access data buffers perform direct data transfer.
Some Performance Considerations
VisualDSP++ Multiprocessor Debugger provides user with full system evaluation using Emulator. Emulator allows code testing evaluation hardware platform. inter-processor communications well data transfers supported. debugger operations like load, reset provide user with capability testing system with full synchronization DSPs. Some debugger features are: Multiprocessor debug commands allow user download, reset, restart, step through code just like with single-processor commands, except that they work synchronously active DSPs selected group. Debugger provides Multiprocessor Status window. This window displays current status each system: Running, Halted, Unknown. contents each debugger window within emulation debugger session reflects selected DSP, i.e. window Focus. default, contents each window will change depending which focus. debugger supports Pinning windows (Memory, Registers, etc.) dedicating them specific system. This will allow user dedicate particular debugger window only display information from particular system, opposed having contents window change whenever processor selected Status window. debugger provides Multiprocessor Group window from which processors grouped into multiple, logical units upon which
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Core data transfers nice fast transferring words data since there need transfer control block kind. However, better choice when large amounts data need transferred since core utilized computational processing. Remember that transfers operate background freeing core.
Checking
This routine used check whether executable file generated gets loaded into correct system. ensures mismatch.
Example
Extract from ID1: Checking 0x3;; FEXT operand SYSTAT;; read SYSTAT FEXT R0;; value r1;; ID1? NAEQ, jump incorrect_ID;; false, stop enter endless loop
Basically, reads value from SYSTAT register compares with theoretical value this case, code been written ID1, makes sure been loaded into correct target that
Introduction TigerSHARC® Multiprocessor Systems Using VisualDSP++(EE-167)
commands applied. This window particularly useful when many processors present system user wishes control/debug subsets these processors together. pinning, processor status items Multiprocessor window, conjunction with single-processor debug commands debug individual processors session.
Figure Multiprocessor Debugger Support
VisualDSP Configurator
Debugger allows emulator targets. Circuit Emulator (ICE) development tool debugging programs running real time target system hardware. emulator reads executable files loads them into DSP. provides controlled environment observing, debugging, testing activities target system connecting directly target processor through JTAG interface. system emulation, SummitICEUniversal Emulator system used. first step, platform must configured
using VisualDSP Configurator. Configurator used describe user's hardware platform JTAG emulator. Once platform been described, emulator target session based upon following steps should followed when configuring platform: Open Visual Configurator. Create platform. Specify name, number type devices included part platform. These steps illustrated Figure Please aware Initial Reset Startup option, which appears Device Properties
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Introduction TigerSHARC® Multiprocessor Systems Using VisualDSP++(EE-167)
window shown Figure Enabling this option will perform complete reset selected device every time emulator session initiated. systems where some settings need preserved (i.e. SDRCON register) this option should cleared. Note: there also similar option debugger itself, reset before loading executable, which performs complete reset devices system upon downloading code DSPs. This option found under Settings/Target Options/.
Figure VisualDSP Configurator
Test Utility JTAG Scan Test
Before getting into actual system debugging, must tested make sure that been properly configured. Test Utility (Figure used this purpose. Open utility, select proper
emulator address, check continuous scan start testing. scan test will then performed output window would look follows after successfully completed scan test:
Introduction TigerSHARC® Multiprocessor Systems Using VisualDSP++(EE-167)
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Similarly, recommended procedure follows:
Figure VisualDSP Test Utility
power-down
Close VisualDSP++ IDDE. Disconnect from JTAG header target. Power-down target. Replace jumpers /TRST JTAG header target (for next power up).
case test does complete successfully, error message will displayed with possible solution problem. Here description some issues that should kept mind system design: multiprocessor system imperative that JTAG header buffered. This will keep signals clean avoid noise problems that occur with longer signal traces (ultimately resulting reliable emulator operation). scan chain, recommended more than eight physical devices (although, theoretically, devices that supported JTAG scan chain software about 50). recommendation more than eight physical devices mostly transmission line effects that appear long signal traces, based some field-collected empirical data. recommended power-up procedure target emulation system follows: Power with connected target. Power target with jumpers /TRST JTAG header. Remove jumpers /TRST from JTAG header target. Connect JTAG header target. Open VisualDSP++ IDDE.
Please refer "EE- Analog Devices JTAG Emulation Technical Reference (2.5)" more detailed description this topic.
System Emulation
that project been created emulator platform ready debugging, begin with hardware emulation.
Figure Load Multiprocessor Processor Window
First all, executable files (.DXE's) downloaded corresponding DSPs. emulation, Load Multiprocessor Confirmation window (Figure appears. This window enables user select which .DXE file loaded into which DSP. Once code been successfully loaded into each DSP, system fully evaluated using features previously described.
Introduction TigerSHARC® Multiprocessor Systems Using VisualDSP++(EE-167)
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After running code both DSPs user view contents data memory windows should able verify that data transfers between DSPs have completed successfully. Figure illustrates classical example some debugger windows that viewed when evaluating system. Running code targets (synchronously both DSPs independently), setting break points, viewing memory contents, system registers just some VisualDSP++ Multiprocessor debugger capabilities.
Figure VisualDSP++ Multiprocessor Session
Introduction TigerSHARC® Multiprocessor Systems Using VisualDSP++(EE-167)
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References
TigerSHARC® Processor Hardware Reference, First Edition, March 2003. Analog Devices Inc. VisualDSP++ Linker Utilities Manual TigerSHARC® DSPs, Analog Devices Inc. VisualDSP++ Emulation Tools Installation Guide Windows 95/98/NT/2000, Analog Devices Inc. Analog Devices JTAG Emulation Technical Reference (2.5) (EE-68), Analog Devices Inc. Understanding ADSP-TS101S TigerSHARC® (EE-143), Analog Devices Inc.
Document History
Version April 2003 Maikel Kokaly-Bannourah Description Updated trademark usage upgraded code example according VisualDSP++ release Initial Release
June 2002 Maikel Kokaly-Bannourah
Introduction TigerSHARC® Multiprocessor Systems Using VisualDSP++(EE-167)
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