Notes using Analog Devices' DSP, audio, video components from Computer

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Notes using Analog Devices' DSP, audio, video components from Computer Products Division Phone: (800) ANALOG-D (781) 461-3881, FAX: (781) 461-3010, EMAIL: dsp.support@analog.com
AD1819A VARIABLE SAMPLE RATE SUPPORT
Last Modified: 5/12/98
Sample rate changes take effect immediately after either register written.
Overview
This Engineer's Note will cover AD1819A's variable sample rate support. advantage AD1819A over other codecs that support sample rate between with precision. different sample rates used, either assigned four converter channels AD1819A. addition, sample rates multiplied constant factor 10/7 generation irrational sample rates used V.34 modems. variable sample rate support AD1819A eliminates burden digital re-sampling imposed controllers specification, without loss audio performance.
Miscellaneous Control Bits Register Register contains four bits which assign SRGs (Sample Rate Generators) each conversion channel, bits enable 10/7 multipliers irrational modem rates.
Name Description ARSR right sample rate generator select DRSR right sample rate generator select SRX8D7 multiply rate SRX10D7 multiply rate 10/7 ALSR left sample rate generator select DLSR left sample rate generator select
Other bits reserved used other purposes, this register should read, result modified necessary, then written back. ALSR, ARSR, DLSR, DRSR bits zero then corresponding converter channels assigned SRG0, sample rate register 78h. those bits ones then corresponding channels assigned SRG1, sample rate register 7Ah. default state these bits zero AD1819A, that change later parts. Hence, software should always these bits instead assuming they reset fixed value. SRX8D7 SRX10D7 bits then sample rate generated SRG1 multiplied constant factor 10/7, respectively. rate generated SRG0 unaffected these bits. result undefined both bits set. Care must taken ensure that neither base sample rate both bits clear) multiplied sample rate bits set) ever outside allowed range; this should problem V.34 irrational rates. Serial Configuration register Register contains enable requests, read-only bits request bits themselves.
Name Description DRRQ0 Master codec right request DRRQ1 Slave codec right request DRRQ2 Slave codec right request DLRQ0 Master codec left request DLRQ1 Slave codec left request
REGISTERS Four vendor-defined registers AD1819A control pair sample rate generators (SRGs). (78h 7Ah) contain sample rates generated. Another (76h) assigns sample rates each conversion channel, enables 10/7 multipliers modem support. last (74h) enables request bits, which required proper transfer data sample rates less than serial frame rate. Sample Rate registers Registers contain sample rates currently assigned each Behavior SRGs undefined sample rates less than (1B58h) greater than default rate (BB80h) used.
DLRQ2 DRQEN
Slave codec left request Enable requests serial frame
command issued.
Other bits reserved used other purposes, this register should read, result modified necessary, then written back. there only codec system then master codec; multi-codec systems covered elsewhere. request bits asserted whenever associated channel able accept data next serial frame. This information required because possible provide more samples channel than accept when channel running rate less than serial frame rate kHz. request deasserted then controller should send sample that channel next frame. DRQEN then AD1819A produces request bits different points input serial frame. Those points bottom half status address slot, status data slot. request bits status address slot compatible with recently released extensions. They active-low (send sample zero), output same order output slots corresponding channels.
Slot SDATA_IN Controls slot status address DLRQ0# DRRQ0# DLRQ1# DRRQ1# DLRQ2# DRRQ2#
DIFFERENCES BETWEEN AD1819A Many features variable sample rate extensions based features introduced Analog Devices AD1819A, there some differences with which systems using AD1819A must cope. First sample rate registers themselves. AD1819A's sample rate registers indices instead through 34h, there fixed mapping converter channels SRGs. Also, AD1819A relies user write sample rates outside acceptable range sample rate registers; codecs handle invalid settings forcing register nearest acceptable value. codecs require that (VRA, register 2Ah) before sample rates changed, while AD1819A's variable sample rate support always enabled. also enables request bits status address slot codecs, while AD1819A uses DRQEN register enable requests both status address status data slots. Future codecs from Analog Devices will comply with variable sample rate extensions, while retaining much compatibility with AD1819A possible.
SYNCHRONIZATION AUDIO DATA Some controllers applications require that stereo samples delivered (left, right) pairs. AD1819A will deliver samples requests pairs long some simple rules followed. ADCs will deliver samples pairs long both channels assigned same (ALSR ARSR register 76h) loopback mode disabled (LPBK register 20h). ADCs must powered down back again whenever ALSR ARSR changed LPBK cleared order guarantee that samples will delivered pairs. requests will issued pairs long both channels assigned same (DLSR DRSR register 76h), loopback mode Page
requests also produced status address data slots emulating register reads register 74h. Once DRQEN set, every input frame (except those following output frame containing read command) will contain status address slot contents register status data slot. This mode provided with controllers that cannot propagate data from half status address slot. preferable request bits from status address slot instead those from status data slot, because latter obscured whenever real register read EE-54
Notes using Analog Devices' DSP, audio, video components from Computer Products Division Phone: (800) ANALOG-D (781) 461-3881, FAX: (781) 461-3010, EMAIL: dsp.support@analog.com
disabled (LPBK register 20h), samples delivered pairs. DACs must powered down again whenever DLSR DRSR changed LPBK cleared order guarantee that requests will delivered pairs. Power cycling ADCs DACs unnecessary they powered down when changes made; altered settings will take effect when converters next powered
EE-54 Notes using Analog Devices' DSP, audio, video components from Computer Products Division Phone: (800) ANALOG-D (781) 461-3881, FAX: (781) 461-3010, EMAIL: dsp.support@analog.com
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