members High-Speed Microcontroller Family designed directly address 64

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Application Note Memory Expansion with High-Speed Microcontroller
members High-Speed Microcontroller Family designed directly address 64kB program data memory. Occasionally, however, application will require more memory than either available on-chip through 64kB memory map. High-Speed Microcontroller Family includes many features which make easy address program and/or data memory greater than 64kB. Bit-addressable ports allow single instruction modification control lines, which used bank switch page between multiple memory devices. ROMSIZE feature allows easy memory resizing devices with on-chip memory. This application note discusses expansion both program data memory. subdivided into three main categories: expanding program memory ROMless devices beyond 64kB, using ROMSIZE feature expand on-chip program memory beyond 64kB, expanding data memory. begins with introduction bank switching software support techniques.
BANK SWITCHING THEORY
Expanded memory access beyond 64kB most frequently done through bank switching. This technique uses more general purpose lines decode lines address more memory. single largecapacity memory device used, additional signals used directly address lines. several smaller capacity memory devices used, signals used chip selects. basic unit memory switched decode logic called bank page. example, line used switch between 64kB EPROMs, memory would consist 64kB pages. Probably biggest obstacle using paged memory scheme placement interrupt vector table. During most device operation, software perform orderly switch between pages. When interrupt occurs, however, device will immediately jump appropriate vector address, below 0070h. software control over bank configuration this point, device will attempt jump current bank seek vector table. There approaches solving this problem. simplest duplicate interrupt vector table each page. this way, interrupt vector table will available times, regardless current memory configuration. There number disadvantages this approach, however. inefficient program memory interrupt vector table (approximately bytes) often interrupt service routines, must duplicated every page. Also, some compilers directly support duplication data across pages, complicating program generation. more efficient approach reserve some lower portion memory, which includes interrupt vector table, that paged. This "common area" directly accessible from expanded bank without modification bank selection mechanism. time processor performs code fetch this common area, hardware forces memory access this area, regardless current page. Careful design will allow previous bank address saved, that device will return automatically when operation common memory complete. Interrupt service routine execution times reduced locating them
070899
APPLICATION NOTE
along with interrupt vector table common area located memory. Most examples this application note designate lower region memory common area.
SOFTWARE SUPPORT MEMORY EXPANSION
paged memory scheme work, necessary fragment code into pages provide means software switch between pages. Care must exercised when switching pages that instruction flow will disturbed. There main approaches this. first switch pages fly." This demonstrated simple page expansion example which follows. This approach causes program execution jump directly from expanded page another expanded page. must exercise caution that bank switch will occur location that corresponds start next instruction next bank. Failure correctly align instructions cause next opcode fetch occur middle multi-byte instruction, resulting complete loss program control. better approach change banks from location that will unaffected change. This most often common unpaged location memory, such reserved location where interrupt vector table located. access lower memory automatically switched into common memory hardware. This eliminates code alignment difficulties with simple page expansion above, need duplicate interrupt vectors and/or interrupt service routines each memory page. Many compilers linkers directly support bank switching, many them include library functions page switching. documentation accompanying your compiler will provide information concerning expanded memory support. Brief examples assembly language support listed after some examples below. Care must exercised multiple pages programmed into single EPROM. Many EPROM programmers calculate program offsets using address specified file, which lead misplaced code. example, suppose that paging scheme involves pages code mapped into program space from 8000h FFFFh. designer wished locate page 10000h EPROM, would normally select offset 10000h EPROM when loading file into programmer. addresses file begin 8000h, however, which device programmer would 10000h. This would inadvertently place page 18000h, which intended result. Various device programmers implement offsets different ways, designer advised consult documentation accompanying device programmer best solution.
ROMLESS PROGRAM EXPANSION
absence on-chip program memory makes expanding program memory DS80C320 relatively simple. Three approaches expanding program memory presented here. first involves expansion relatively small amounts memory duplicating vector tables overlapping pages. second example uses common bank interrupt vectors interrupt service routines, pages memory using several general purpose lines. last example uses latched address address large amounts memory without using additional general purpose lines.
Simple Page Expansion
This example shows simplest adding relatively small amounts program memory. single general purpose line used provide 128k bytes program memory. single 27C010 128k byte EPROM used, divided into overlapping memory blocks. general purpose line, P1.0 this case, used provide bank switch control. latched 74F74, which clocked rising edge PSEN signal. This synchronizes bank switch with memory cycle. This approach
APPLICATION NOTE
extrapolated even greater amounts memory using additional lines. hardware configuration this example shown Figure
SIMPLE PAGE EXPANSION EXAMPLE HARDWARE Figure
simplicity hardware comes cost some software complexity, however. This example uses banks, both which contain interrupt vector tables lower portion memory. This necessary because when device reset, P1.0 will high, forcing reset vector address 10000h. Also, interrupt occur while executing code from either page, interrupt vectors must available without software intervention. interrupt vector table consumes approximately bytes from locations 00000h 00070h, 10000h 10070h. Additional space required duplication interrupt service routines desired each page.
SIMPLE PAGE EXPANSION EXAMPLE MEMORY Figure
This approach most effective when page switching kept minimum, i.e., executing straight runs code. Code efficiency will improved interrupt routines (not just vectors) small enough
APPLICATION NOTE
duplicated each page well. Data tables strings accessed with MOVC instructions should located same page instruction. This approach directly modifies page without modifying program counter. This means that starting location page will same bank switch routine page. Consequently, instruction location between pages critical. Figure shows timing relationship between instruction bank select signal. this example, instruction located location 5A10h, first instruction page located 5A14h. port which controls bank selection will change during first cycle following instruction. 74F74 latch causes bank selection valid prefetch during execution second NOP. first instruction page must address following second NOP. There other ways modifying port pins, this scheme will work with cycle instructions such direct, direct, cycle instructions such SETB bit. There only requirements bank switching instructions. first instruction page must address following second NOP. Also, instruction proceeding instruction must MOVX. MOVX instruction timing variable because stretch cycles, could disturb instruction flow.
BANK SWITCHING TIMING DIAGRAM Figure
Common-Page Expansion Using
following examples common-block approach dealing with problem interrupt vector placement. This allows faster interrupt service times, simplifies code construction. Both examples employ paging scheme with pages 32kB each. Page mapped 0000h 7FFFh, common area contains interrupt vector table interrupt service routines. Address line determines whether common block, expanded pages addressed. This example shows address 512kB using general purpose lines port bank switching controls. Bank single 32kB page from 7FFFh. This common area will contain interrupt vectors commonly used subroutines. Expanded memory will contained
APPLICATION NOTE
pages 32kB mapped from 8000h FFFFh. Bank control provided general purpose pins. memory shown Figure
COMMON-PAGE EXPANSION MEMORY EXAMPLE MEMORY Figure
hardware configuration shown Figure Bank control provided P1.0-3, decoded gates, requiring only single package. When low, device forced access only lower 32kB memory. This removes need software intervention when accessing interrupt vector table memory. This example uses 27C040 512KB EPROM.
DS80C320 EXPANDED MEMORY EXAMPLE HARDWARE CONFIGURATION Figure
APPLICATION NOTE
following software example shows assembly language routine jump location bank using lines shown Figure Before calling bank switch subroutine, software pushes address bank number onto stack. then calls subroutine that pops bank address from stack places P1.0-3. stack then modified that subsequent instruction will return program location. This simple demonstration many possible ways effect bank-switch assembly code.
PROGRAM EXAMPLE: JUMPING BETWEEN BANKS USING
;Program BANKJMP1.ASM ;This program demonstrates possible jump between banks common;page memory expansion configuration using I/O. Four general purpose pins P1.0-3 used control external bank selection. ;Software pushes address bank, well bank address ;onto stack. subroutine BANKJUMP, located non-paged address, ;modifies page selection, then repositions stack pointer ;new address which previously pushed onto stack. then ;executed, resuming operation from address page. Note that ;BANKJUMP called from area program memory. ;Equate table BANKMASK 0F0h ;P1.3-0 used bank selection. NEWSUB_BANK ;Subroutine NEWSUB located page 03h. NEWSUB cseg cseg START: LJMP PUSH PUSH PUSH LJMP START 100H #0F0h #low NEWSUB #high NEWSUB #NEWSUB_BANK BANKJUMP 0F000h ;Address subroutine NEWSUB. ;compiler used, supply this ;automatically. ;Reset vector. ;Start program ;Default bank ;Low byte NEWSUB address. ;High byte NEWSUB address. ;Bank address NEWSUB.
;Call subroutine switch operation bank. This will transfer execution location NEWSUB bank NEWSUB_BANK. ;BANKJUMP This subroutine pulls jump page address stack. modifies P1.0-3, then modifies stack pointer point address. then Returns jump location. This subroutine must placed common, unpaged memory area. BANKJUMP: ;Disable interrupts. ;Get page address stack #BANKMASK ;and modify only P1.0-3 bank ;address. SETB ;Reenable interrupts. ;Stack pointer return ;address. Program will begin executing ;from bank.
APPLICATION NOTE
Common-Page Expansion Using Latched Data
drawback above design that requires lines bank controls. Some intensive applications able spare port pins bank switching. following example uses Lattice Semiconductor GAL26V12 programmable logic device (PLD) latch bank select signals, rather than using dedicated pins. This approach uses same memory previous example, with exception that data memory from FFE0h FFFFh accessible. These bytes inaccessible because through decoded, allowing smaller, lower cost used. Decoding more address lines would reduce amount inaccessible data memory, would require more complicated decoding mechanism. GAL26V12 performs bank switching function based write MOVX data memory. write data memory from FFE0h FFFFh decoded, lower four bits data written that address used configure bank switch select lines. hardware configuration shown Figure source file follows illustration. scans address selected range latches lower nibble data onto A15-A18 memory device. Addressing locations between 80000h will temporarily clear bank select lines forcing EPROM read from bank (0000h7FFFh). soon lower memory operation complete, accesses upper half memory (8000h-FFFFh) will automatically return previous bank because bank address still latched registered outputs PLD. Although variety PLDs suitable this application, device used must reset outputs power-up. This necessary because upon power-up device must able access reset vector located 0000h bank When selecting PLD, designer should aware that many standard programmable logic devices designed that their outputs high upon reset.
DS80C320 LATCHED ADDRESS MEMORY HARDWARE EXAMPLE Figure
following software example shows assembly language routine jump location bank using latched data shown Figure Before calling bank switch subroutine, software pushes address bank number onto stack. then calls subroutine that pops bank address
APPLICATION NOTE
from stack writes location FFFFh, where latched bank address. stack then modified that subsequent instruction will return program location.
PROGRAM EXAMPLE: JUMPING BETWEEN BANKS USING LATCHED ADDRESSING
;Program BANKJMP2.ASM ;This program demonstrates possible jump between banks common ;page memory expansion configuration using latched addressing. ;Software pushes address bank, well bank address ;onto stack. subroutine BANKJUMP, located non-paged address, ;modifies page selection, then repositions stack pointer ;new address which previously pushed onto stack. then ;executed, resuming operation from address page. Note that ;BANKJUMP called from area program memory. ;Equate table LATCH_ADR 0FFFFh ;Address bank select latch. NEWSUB_BANK ;Subroutine NEWSUB located page 03h. NEWSUB 0F000h ;Address subroutine NEWSUB. compiler used, supply this automatically. cseg ;Reset vector. LJMP START cseg START: PUSH PUSH PUSH LJMP 100H #low NEWSUB #high NEWSUB #NEWSUB_BANK BANKJUMP ;Start program ;Low byte NEWSUB address. ;High byte NEWSUB address. ;Bank address NEWSUB.
;Call subroutine switch operation bank.
;BANKJUMP This subroutine pulls jump page address stack. writes page address PLD, where latched page address. then causes execution address specified function that called this routine. This subroutine must placed common, unpaged memory area. BANKJUMP: ;Disable interrupts. point page address. ;Get page address stack. DPTR, #LATCH_ADR ;Write page address latch. MOVX @DPTR, SETB ;Restore interrupts. ;Stack pointer return address. Program will begin executing from bank.
source file GAL26V12 presented designer developing devices. file written CUPL language, easily modified work with other assemblers.
APPLICATION NOTE
PROGRAM EXAMPLE: PROGRAM FILE
Name MEM_EXP; Device g26v12; This CUPL file will program GAL26V16 bank switching latch address kbytes program memory. MOVX write addresses FFE0h through FFFFh will latch bank selection. access 0000h through 7FFFh program memory will clear bank select lines that operation only. This allows device jump interrupt vectors with intervention, return same bank when finished. DEFINITIONS: These definitions PLCC Input pins CLKIN; Clock input latches. A15; Microcontroller address lines address ecode. A14; A13; A12; A11; A10; Microcontroller data lines bank selection. WR_STROBE; Microcontroller write strobe Output pins CLKOUT;
A18_LATCH; A17_LATCH; A16_LATCH; A15_LATCH; MEMADR_18; MEMADR_17; MEMADR_16; MEMADR_15;
Qualified microcontroller write strobe. back into 26V12 input. This signal must assigned because requires product terms. Temporary latch memory signal. Temporary latch memory signal. Temporary latch memory signal. Temporary latch memory signal. Output memory device A18. Output memory device A17. Output memory device A16. Output memory device A15.
;PIN ;PIN Qualify write strobe detect valid bank latch write. BANK_SEL CLKOUT !WR_STROBE BANK_SEL BANK SELECT GENERATION A15_LATCH.D A15_LATCH.OEMUX ;Disable external expression this signal. MEMADR_15 A15_LATCH.Q BANK SELECT GENERATION A16_LATCH.D A16_LATCH.OEMUX ;Disable external expression this signal. MEMADR_16 A16_LATCH.Q BANK SELECT GENERATION A17_LATCH.D A17_LATCH.OEMUX ;Disable external expression this signal. MEMADR_17 A17_LATCH.Q BANK SELECT GENERATION A18_LATCH.D A18_LATCH.OEMUX ;Disable external expression this signal. MEMADR_18 A18_LATCH.Q
APPLICATION NOTE
USING ROMSIZE FEATURE
ROMSIZE feature allows software dynamically reconfigure program memory size, permitting portion program memory switched between off-chip. provides easy increase program memory 64kB plus on-chip memory. addition, simplifies task building bootloader external programmable memory, such FLASH, EEPROM, Nonvolatile SRAM SRAM). Using ROMSIZE feature very straightforward. Bits RMS2, RMS1, RMS0 (ROMSIZE.2-0) select maximum amount on-chip memory. ROMSIZE select bits Timed Access protected ensure maximum software reliability. program memory accesses outside range defined ROMSIZE register will automatically fetched externally ports External code fetches devices with ROMSIZE feature performed same members High-Speed Microcontroller Family. designer reminded that ports will used external memory access, they should used general purpose ports. modification ROMSIZE register must followed machine cycle delay, such executing instructions, before jumping address range. Interrupts must disabled during this operation, because jump interrupt vector during changing memory cause erratic results. procedure reconfigure amount on-chip memory follows: Jump location program memory that will unaffected change, Disable interrupts clearing (IE.7), Write Timed Access Register (TA;C7h) Write Timed Access Register (TA;C7h) Modify Size Select bits (RMS2-0), Delay machine cycles instructions), Enable interrupts setting (IE.7).
There number software considerations when using ROMSIZE feature switch between onand off-chip memory. Modification Size Select register must made from program memory location that will valid both before after on-chip memory configuration. Care must exercised when assembling compiling program that modules located correct starting address, including interrupt vector table. byte on-chip memory option selected, extra precautions must taken. necessary duplicate interrupt vector table off-chip memory when switching lower program memory from on-chip off-chip. general, applications will find most useful reduce on-chip memory smaller than 1kB. This will maximize addressable external memory range, while keeping interrupt vectors on-chip. option most useful when on-chip memory only used boot loader.
EXPANDING MEMORY BEYOND 64kB WITH ROMSIZE FEATURE
Addressing more than 64kB external memory con-junction with ROMSIZE feature done similar ROMless method. primary difference that ROMSIZE feature allows designer on-chip program memory "common" block. This simplifies construction external
APPLICATION NOTE
hardware, common block memory signal (the signal examples presented) does have decoded. designing with ROMSIZE feature incorporate on-chip memory into memory with most efficient memory utilization simplest decoding method. There many approaches this problem, only will presented here. This example uses 16kB on-chip memory, plus eight 48kB pages expanded memory located 27C040 512kB EPROM. This provides total program memory 400kB. interrupt vectors service routines contained on-chip memory fast access. Figure shows possible memory with DS87C520 incorporating 16kB on-chip EPROM. Note that program memory from 0000h 3FFFh each external page used. This greatly simplifies design memory decode, requiring external logic less line. Figure shows three lines directly decode uppoer address lines device. Software this configuration similar that presented previous examples. also possible ROMSIZE feature conjunction with latched bank address MOVX bus. Similar ROMless example, this approach does require dedicated pins bank switching. Because on-chip program memory allows simpler decode circuit, less expensive PLDs used.
ROMSIZE FEATURE COMMON-PAGE EXPANSION MEMORY Figure
APPLICATION NOTE
ROMSIZE FEATURE COMMON-PAGE EXPANSION Figure
Expanding amount data memory used microcontroller easiest form memory expansion. Because there possibility interfering with program execution, timing critical. General purpose lines connected directly address lines chip enables memory device(s). appropriate port directly modified access correct page prior memory operation. application requires available lines, then latched bank address scheme demonstrated above examples used.

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