December 1995 Mitsubishi Electric Corporation CONTACT MITSUBISHI
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Specifications (Ver. 2.0) MPEG2 MOTION ESTIMATION (M65727FP)
December 1995 Mitsubishi Electric Corporation
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CONTENTS
Outline Outline Characteristics
Listing Description Listing Description 2.2.1 Data Ports 2.2.2 System Control Pins 2.2.3 Input Pins Sync. Signals 2.2.4 Pins Specifying Operational Modes 2.2.5 Others Outline Functions Outline Block Configuration 3.2.1 Input Unit 3.2.2 Integer Unit 3.2.3 Motion Detection Unit 3.2.4 Half-Pel/Dual-Prime Unit 3.2.5 Output Unit Operation modes 3.3.1 Field/Frame/Field Dual-Prime/Frame Dual-Prime 3.3.2 Horizontal Search Range 3.3.3 Vertical Search Range 3.3.4 Search range expansion Vertical Direction 3.3.5 Half-Pel Precision/Integer-Pel Precision 3.3.6 External Frame Memory Data Format 3.3.7 Operation Modes Output Data 3.3.8 Operation Modes Dynamic Control Signals Operations Reset Operation Wait Operation Motion Estimation Operation 4.3.1 Search Window Image Input Field/Frame mode 4.3.2 Search Window Image Input Dual-Prime mode 4.3.3 Template Data Input 4.3.4 Output Request 4.3.5 Activation Execution Cycle 4.3.6 Dynamic Control Input 4.3.7 Number Cycles Needed (from Data Input Data Output)
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Others Macro Block Processing Missing Search Range Priority Order Distortion Equivalent Vector Detail Vector Search Range Formats External Frame Memory (Search Window Image Memory) Expansion Search Range Controlling Validity Search Range Operational Timing Treatment Final Mode Change during Processing
Electrical Characteristics Others Electrical Characteristics 6.1.1 Maximum Ratings 6.1.2 Operating Range 6.1.3 Electrical Characteristics 6.1.4 Switching Characteristics 6.1.5 Set-up Hold Times Package Thermal Management
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Outline Outline M65727 highly efficient motion estimation used estimate motion vectors real-time encoding dynamic images. M65727 used together with frame memory, M65721 (Controller LSI) M65722 (Pixel Processor LSI). operates under control M65721. M65727 accepts template macro block (MB) data inputs from M65721 accepts search window image data from frame memory. estimate motion vectors searching minimum value mean absolute error between template block data search window image data. outputs result M65721. M65721 M65722 able generate prediction image using above mentioned motion vector. M65727 designed that applicable MPEG2, international video compression standard.
[Main Specifications] Field Mode (per field) *Block size 16x16 16x8 (Upper), 16x8 (Lower) simultaneously *Search range Vertical direction: ±7.5(*A) ±15.5 pixel (Switchable) However, ±8.0(*A) ±16.0 used during expansion respectively Horizontal direction: ±7.5 ±15.5 ±31.5 ±63.5 ±127.5 pixel (Selectable) *Search methods Integer-pel precision exhaustive search Half-pel precision points around best integer-pel precision vector (Including integer precision location) *Evaluation function Full sampled mean absolute error *Execution cycle Dependent search range execution cycle mentioned here refers throw-in period processing time. (Horizontal ±7.5, vertical ±7.5) (550) cycles (Horizontal ±15.5, vertical ±7.5) (550) cycles (Horizontal ±7.5, vertical ±15.5) (806) cycles (Horizontal ±15.5, vertical ±15.5) (806) cycles *Search window image inputs When vertical ±7.5 searched: pixels (550) cycles When vertical ±15.5 searched: pixels (806) cycles *Processing capability 27MHz operation: Processing search range over horizontal ±7.5 vertical ±7.5 ITU-R image size possible. 40MHz operation: Processing search range over horizontal ±7.5 vertical ±15.5 ITU-R image size possible. mode vertical search range ±7.5 used only under 27MHz operation.
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Frame Mode (per frame) *Block size *Search range
16x16 16x8 (Top*), 16x8 (Bottom**) simultaneously Vertical direction: ±7.5(*A) ±15.5 pixel (Switchable) corresponds sets fields each ±3.5 pixel ±7.5 pixel location 16x8 blocks. However, ±8.0(*A) ±16.0 used during expansion respectively Horizontal direction: ±7.5 ±15.5 ±31.5 ±63.5 ±127.5 pixel (Selectable) *Search methods Integer-pel precision exhaustive search Half-pel precision points around best integer-pel precision vector (Including integer precision location) *Evaluation function Full sampled mean absolute error *Execution cycle Depends search range execution cycle mentioned here refers throw-in period processing time. (Horizontal ±7.5, vertical ±7.5) (550) cycles/ (Horizontal ±15.5, vertical ±7.5) (550) cycles (Horizontal ±7.5, vertical ±15.5) (806) cycles (Horizontal ±15.5, vertical ±15.5) (806) cycles Search window image inputs When vertical ±7.5 searched: pixels (550) cycles When vertical ±15.5 searched: pixels (806) cycles *Processing capability 27MHz operation: Processing search range over horizontal ±7.5 vertical ±7.5 ITU-R image size possible. 40MHz operation: Processing search range over horizontal ±7.5 vertical ±15.5 ITU-R image size possible. "Top" "Bottom" mentioned here indicate field parities. following explanation, frame with field side first line assumed. mode vertical search range ±7.5 used only under 27MHz operation.
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Field Dual-Prime Mode *Block size *Search range *Search method
16x16 Second field: horizontal ±0.5 pixel, vertical: ±0.5 pixel Take average with first field data (half-pel generated needed) estimate points over second field (including specified point) *Evaluation function Full sampled mean absolute error *Execution cycle execution cycle mentioned here refers throw-in period processing time. (550) cycles *Search window image inputs First field: (18x24) pixel (550) cycles Second field: (18x24) pixel (550) cycles *Processing capability 27MHz operation: Processing search range over horizontal ±7.5 vertical ±7.5 ITU-R image size possible.
Frame Dual Prime Mode *Block size *Search range *Search method
16x8 Second field: horizontal ±0.5 pixel, vertical: ±0.5 pixel Take average with first field data (half-pel generated needed) estimate points over second field (including specified point) only minimum evaluation value, also points stored output. *Execution cycle execution cycle mentioned here refers throw-in period processing time. (550) cycles *Search window image inputs First field: (18x16) pixel (550) cycles Second field: (18x16) pixel (550) cycles *Processing capability 27MHz operation: Processing search range over horizontal ±7.5 vertical ±7.5 ITU-R image size possible. ***: Frame Dual-Prime Mode supports part Dual-Prime prediction specified MPEG2.
Items common modes *Maximum operating frequency 40.5MHz (24.6ns) *Two input ports: Port Search window image data, Port Template data, *Output port output port
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Characteristics M65727 following characteristics. *Highly efficient parallel architecture high speed processing data transfer, which eliminates bottleneck. *Supports prediction modes MPEG2, Field prediction, Frame prediction, Field Dual-Prime prediction Frame Dual-Prime prediction. *For Field Mode Frame Mode, possible simultaneous vector search over 16x16 16x8 blocks. *Implementing cost image compression hardware possible using DRAM frame memory DRAM interface. *Estimates half-pel precision vectors chip. *The exhaustive search method used over integer-pel precision vectors search range. Evaluation function full sampled mean absolute error. *The M65727's scalable architecture allows wider search range with multiple-chip configuration. When expanding horizontal search range, possible common search window image data into chips.
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Explanation Pins List Pins Table shows list pins M65727. Table List M65727 Pins Remarks SEARCH WINDOW IMAGE DATA INPUT TEMPLATE DATA INPUT RESULTS OUTPUT CLOCK INPUT RESET CLOCK ENABLE DSWI INPUT DATA ENABLE DMBI INPUT DATA ENABLE OUTPUT ENABLE DSWI INPUT SYNC SIGNAL DMBI INPUT SYNC SIGNAL PROCESS EXECUTION SYNC SIGNAL DYNAMIC CONTROL SYNC SIGNAL OUTPUT REQUEST SIGNAL SPECIFIES OPERATION MODE FIELD, FRAME, FIELD DUAL-PRIME, FRAME DUAL-PRIME HORIZONTAL SEARCH RANGE ±7.5, ±15.5, ±31.5, ±63.5, ±127.5 VERTICAL SEARCH RANGE ±7.5, ±15.5 VERTICAL SEARCH RANGE EXTENSION VECTOR PRECISION FRAME MEMORY FORMAT DYNAMIC CONTROL INPUT TEST POWER
names DSWI [31:0] DMBI [7:0] DOUT [7:0] CLKI RESETC DENSWC DENMBC SSYNC MSYNC ESYNC DSYNC OREQC MODE [1:0]
Number Pins
Type
HSIZE [2:0] VSIZE EXTND [1:0] HLFPL FMFMT DCNT [3:0] TEST [6:0]
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Explanation Pins Functions uses M65727 pins explained below. Refer "2.1 List Pins" configuration terminals attributes. term Execution cycle used this explanation refers means that above cycle capable vector detection within search range (-8) horizontally using integer precision. When horizontal search area greater than equal ±15, integer precision operation requires multiple execution cycles. 2.2.1 Data Ports DSWI This wide search window image data input port. search window image input processed parallel with arithmetic operation. Therefore, data inputted will used next execution cycle. This wide template input port. template input processed parallel with arithmetic operation. Therefore, data inputted will used next execution cycle. This wide output port, during field frame mode, receives output request, OREQC, outputs following information following order. horizontal motion vector, vertical motion vector, minimum distortion, distortion vector (0,0), half-pel indication code During field dual-prime mode, M65727 outputs minimum distortion indication code. During frame dual-prime mode, outputs minimum distortion, indication code distortions correspond estimation points.
DMBI
DOUT
2.2.2 System Control Pins CLKI RESETC Clock input. RESET pin. Hardware reset. Asserted low. registers reset RESET. Before normal operation, M657272 requires RESET. Asserted low. This enables input clock. This signal sampled upedge CLKI. next clock cycle valid when this signal asserted. invalid clock cycle called "wait cycle". chip designed static CMOS circuits internal data will destroyed during wait cycles.
DENSWC This enables DSWI port. This signal asserted low. Data accepted during not-active cycles. DENMBC This enables DMBI port. This signal asserted low. Data accepted during not-active cycles. This output enable pin. This signal asserted low. controls tri-state DOUT port. DOUT port.
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2.2.3 Sync Signal Input Pins SSYNC MSYNC ESYNC DSYNC This sync signal DSWI port. asserted low. This signal must asserted when leading data DSWI inputted This sync signal DMBI port. asserted low. This signal must asserted when leading data DMBI inputted This sync signal block level pipeline. When this signal asserted, execution cycle (550 cycles) activated. asserted low. This sync signal DCNT port. must asserted when dynamic control signal inputted. DCNT content dynamic control signal. This signal asserted low. This used request output. M65727 starts output from DOUT port after this signal asserted. This signal asserted low.
OREQC
2.2.4 Pins Specifying Operational Modes MODE This sets mode M65727. following four modes specified. Field mode, Frame mode, Field Dual-Prime mode, Frame Dual-Prime mode This specifies horizontal search range. following five types range specified. 000: ±7.5, 001: ±15.5, 010: ±31.5, 011: ±63.5, 100: ±127.5, 101~ 111: reserved This specifies vertical search range. specified. ±7.5, ±15.5 following types range
HSIZE
VSIZE EXTND
This specifies vertical search range expansion. When expansion modes selected, vertical search range ±8.0 ±16.0. possible expand vertical search range using multiple chips. Depending modes, order priority regarding vectors with same distortions different. non-expansion, reserved, upper-range expansion, lower-range expansion This switches between half-pel precision search mode integer-pel precision search mode. Integer-pel precision search, half-pel precision search Switches between external memory image) formats. Field format, Frame format This dynamic control input. (Dynamic control means control which differs each execution cycle.) following required. Control valid invalid search range (SKILL) Leading pixel location search window image vertical direction when dual-prime mode (DVSPO) central position search window image used dual-prime mode (DCNTR)
HLFPL FMFMT DCNT
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above control signals inputted within execution cycle prearranged sequence assuming DSYNC repeatedly. control information used next execution cycle. 2.2.5 Others TEST Used testing M65727 released users. Power supply Grounding
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Outline Functions Outline M65727 configured shown Fig. 3.11. main components Input Unit, Integer-pel Unit, Motion detection Unit, Half-pel Dual-Prime Unit, Output Unit. When Field/Frame mode selected, search window image data template data inputted Input Unit from their respective input ports. data used source data Integer-pel Unit after order changed. Then, mean absolute error calculated each cycle Integer-pel Unit result given Motion detection Unit best integer-pel precision motion vectors estimated. Then, Half-pel Unit, best half-pel precision motion vectors estimated. results output from Output Unit. When Field/Frame Dual-Prime mode selected, template data search window image data first field second field sent Input Unit from their respective input ports become source data Dual-Prime Unit. Then, motion vector estimation conducted Dual-Prime Unit results output from Output Unit. functions each unit outlined below.
Block Configuration 3.2.1 Input Unit function Input Unit output search window image data template data Integer-pel Unit Dual-Prime Unit with necessary sequence timing. Having this block enables user input comparatively freely needed search window image data, using sync signal (SSYNC) data enable signal (DENSWC), without regard motion estimation sequence. Similarly, necessary template data inputted fairly freely using sync signal (MSYNC) data enable signal (DENMBC). search window image data inputted from highest line towards lowest line scanning left right. output sequence, other hand, starts from leftmost column rightmost column scans bottom. input output sequence search window image data DualPrime from highest line lowest line scanning from left right. search window image data inputted vertical continuous pixels using input port. Input Unit outputs pixel cycle parallel-serial conversion. 3.2.2 Integer-pel Unit function this block calculate mean absolute error using template data search window image data coming from Input Unit. Integer-pel Unit composed processing elements arranged parallel, allowing high speed processing data evaluated. Three sets calculated mean absolute error (corresponding 16x16 block sets 16x8 block) given Motion detection Unit. Three sets search window image data template data that correspond three sets vectors transferred from integer-pel Unit Half-pel Unit.
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3.2.3 Motion detection Unit function this block select vest motion vector integer-pel precision comparing 16-bit mean absolute error coming from Integer-pel Unit. addition, this block stores distortion vector (0,0). case when distortions multiple motion vectors same, most suitable motion vector determined according order priority. output data depends modes. When integer-pel precision search mode specified during Field/Frame mode, following items output Output Unit. They three sets best integer-pel precision motion vectors, distortion each, distortion each vector (0,0). half-pel precision search mode specified when Field/Frame mode, three sets best integer-pel precision motion vectors distortion each vector (0,0) output Output Unit. And, distortions each integer-pel precision vector output Half-pel Unit. 3.2.4 Half-Pel Dual-Prime Unit This Unit calculates, during Field/Frame mode, mean absolute errors half-pel precision vectors detects minimum distortions using partial search window image data around best integer-pel precision vectors. search window image consists 18x18 pixels sets 18x10 pixels around three sets integer-pel precision motion vectors detected Motion detection Unit. Eight kinds interpolated images generated half-pel interpolation filter. This image matched against template data given from integer-pel Unit minimum distortions detected from above results. During Field/Frame Dual-Prime mode, detects best from template data, first search window image data second search window image data. first second search window image consist 18x18 pixel (10) each. interpolated image from first search window generated according central position information (Displacement based pixel from 16x16 pixels contained 18x18 (10) pixels). Similarly, nine sets interpolated images generated through interpolated filter from second search window. Then, nine sets averaging images first second images obtained. Next, block matching between template data conducted best obtained. case Frame Dual-Prime mode, only minimum evaluation value, evaluated values displacement output. 3.2.5 Output Unit This interface circuit related Output Port, DOUT. Necessary data comes from Motion detection Unit Half-pel Dual-Prime Unit output through DOUT sync with output request signal, OREQC.
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Operational Modes M65727 following operational modes which switched externally. outlines operational modes M65727.
This chapter
3.3.1 Field Frame Field Dual-Prime Frame Dual-Prime M65727 capable modes, namely Field mode Frame mode Field Dual-Prime mode Frame Dual-Prime mode, work with prediction mode MPEG2. These modes specified shown below using MODE pins. They must specified before chip operation fixed during operation. Field mode Frame mode Field Dual-Prime mode Frame Dual-Prime mode Field mode detects three sets motion vectors simultaneously which work with 16x16 block, 16x8 (upper) block, 16x8 (lower) block. Frame mode detects three sets motion vectors simultaneously which work with 16x16 block, 16x8 (top) block, 16x8 (bottom) block. Field Dual-Prime Frame Dual-Prime mode detect dmv. 3.3.2 Search Range Horizontal Direction search range horizontal direction selected from ±7.5 ±15.5 ±31.5 63.5/ ±127.5. number cycles needed motion vector estimation increases proportion size horizontal search range. When ±15.5 larger specified horizontal search range, expected that multiple chips with interleaving manner used. Refer Chapter number chips needed when horizontal search range ±15.5 more. horizontal search range specified shown below using HSIZE pins. horizontal search range must specified before chip goes into operation should fixed during operation. 000: ±7.5, 001: ±15.5, 010: ±31.5, 011: ±63.5, 100: ±127.5, 111: Reserved 3.3.3 Search Range Vertical Direction vertical search range selected from ±7.5 ±15.5. This range detects minimum execution cycle (550 806) vertical expansion mode, search range will ±8.0 ±16.0. Chapter number chips needed vertical expansion. vertical search range specified shown below using VSIZE pin. This must done before chip operation should fixed during operation. ±7.5, ±15.5 vertical search range ±7.5 used only under 27MHz operation.
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3.3.4 Search range expansion Vertical direction non-expansion mode vertical search range ±7.5 ±15.5 explained above. this time, order priority vectors, which have same distortions, gives highest priority vector (0,0). When search range expansion mode vertical direction specified, range becomes ±8.0 16.0. becomes possible expand vertical search range using multiple chips. There modes vertical expansion mode, upper-range expansion lower-range expansion. difference between priority order distortion equivalent vectors. specified upper-range, vector +16) will have highest priority. specified lower-range, vector -16) will have highest priority. order priority vectors. number chips needed vertical search range expansion. This mode specified EXTND shown below. This mode must specified before chip goes into operation should fixed during operation. non-expansion, reserved, upper-range expansion (Expansion), lower-range expansion (Expansion) 3.3.5 Half-Pel Precision/Integer-Pel Precision motion vector searched M65727 integer-pel precision during integer-pel precision mode. case half-pel precision mode, half-pel precision vector detected using interpolated search window image. order output data shown Table (See 3.3.7). above modes have different outputs. This mode specified HLFPL shown below. This mode should specified before chip operation should stay fixed. Integer-Pel Precision mode, Half-Pel Precision mode 3.3.6 External Frame Memory Data Format M65727 capable selecting external frame memory image) format only when Frame mode This format specified FMFMT shown below. other modes, only field format used. details formats. This mode must specified prior chip operation should fixed during operation. Field format Frame format 3.3.7 Operation Modes Output Data Data output from M65727 differs according operational modes. During Field Frame mode, three sets data group, group 16x16 groups 16x8, output sequence. Outputs from half-pel precision mode integer precision search mode different. When Field mode data group 16x16 block first output. data group 16x8 (upper) block output next data group 16x8 (lower) output last. takes cycles. When Frame mode data group 16x16 block output first. data group 16x8 (top) output next. 16x8 (bottom) block output last. takes cycles. Table shows data outputs during Field/Frame mode order they output. case Field Dual-Prime mode, Dual-Prime vector specifying code distortion output order shown Table takes cycles output data.
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When Frame Dual-Prime mode used, Dual-Prime vector specifying code, distortion, distortions each displacement point output order shown Table takes cycles output data. integer-pel precision motion vector outputs motion vector corresponding 16x16 block even 16x8 block. Therefore, during Frame Estimation Mode, vertical component motion vector 16x8 block must changed outside. When multiple chips used expand vertical search range, vertical components motion vectors must changed blocks. Fig. 3.3.7-1 shows correspondence between 16x8 block vectors. Table Operational modes Integer-pel precision search Half-pel precision search Output sequence Motion vector horizontal Integer precision motion vector component horizontal component Motion vector vertical Integer precision motion vector component vertical component Minimum evaluation value (upper 8bits) Minimum evaluation value (upper 8bits) Minimum evaluation value (lower 8bits) Minimum evaluation value (lower 8bits) evaluation value (upper 8bits) evaluation value (upper 8bits) evaluation value (lower 8bits) evaluation value (lower 8bits) output Half-pel indication code Note Note Note motion vector binary number complement. output after expanded bits. Upper bits evaluation value first output lower bits output next natural binary Half-pel indication code specified lower bits shown below. output.
0000: 1010: 1001: 0110: 0101: 0010: 0001: 1000: 0100: Most suitable integer-pel precision motion vector Upper-left direction Half-pel integer-pel precision vector Upper-right direction Half-pel integer-pel precision vector Lower-left direction Half-pel integer-pel precision vector Lower-right direction Half-pel integer-pel precision vector Left direction Half-pel integer-pel precision vector Right direction Half-pel integer-pel precision vector Upper direction Half-pel integer-pel precision vector Lower direction Half-pel integer-pel precision vector
upper bits
(0.0, 0.0) (-0.5, -0.5) (+0.5, -0.5) (-0.5, +0.5) (+0.5, +0.5) (-0.5, +0.0) (+0.5, +0.0) (+0.0, -0.5) (+0.0, +0.5)
Note
(0,0) evaluation value evaluation value corresponding no-motion. When specifying upper range expansion, evaluation point +16) used position; when specifying lower range expansion, evaluation point -16) used position.
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Table Relationship between Field Dual-Prime Estimation Mode Output Data Output sequence Minimum evaluation value (Upper 8bits) Minimum evaluation value (Lower 8bits) indication code Table Relationship between Frame Dual-Prime Estimation Mode Output Data
Output sequence Minimum evaluation value (Upper) Output sequence Left evaluation value (Upper) Left evaluation value (Lower) Right evaluation value (Upper) Right evaluation value (Lower) Left lower evaluation value (Upper) Left lower evaluation value (Lower) Lower evaluation value (Upper) Lower evaluation value (Lower) Lower right evaluation value (Upper) Lower right evaluation value (Lower)
Minimum evaluation value (Lower) indication code Center evaluation value (Upper) Center evaluation value (Lower) Left upper evaluation value (Upper) Left upper evaluation value (Lower) Upper evaluation value (Upper) Upper evaluation value (Lower) Right upper evaluation value (Upper) Right upper evaluation value (Lower)
Note Note
evaluated values output using natural binary number. output lower bits output next.
First, upper bits
indication code specified using lower bits shown below. upper bits output. 0000: center point vector optimum (+0.0, +0.0) 1010: Upper left from center point vector (-0.5, -0.5) 1001: Upper right from center point vector (+0.5, -0.5) 0110: Lower left from center point vector (-0.5, +0.5) 0101: Lower right from center point vector (+0.5, +0.5) 0010: Left center point vector (-0.5, +0.0) 0001: Right center point vector (+0.5, +0.0) 1000: Upper direction from center point vector (+0.0, -0.5) 0100: Lower direction from center point vector (+0.0, +0.5)
3.3.8 Operational Modes Dynamic Control Signals (for each processing cycle) M65727 controls which need change every execution cycle. These controls differ according operational modes shown below. They input chip through DCNT pins when DSYNC asserted. assertion needed each information write into chip. Therefore, when mode needs multiple control information, DSYNC must asserted multiple times. DSYNC asserted low.
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*Valid Invalid control search range (Search Window Kill: SKILL) This used Field/Frame/Field Dual-Prime/Frame Dual-Prime modes shows whether they valid invalid with regard motion estimation range during next execution cycle. When horizontal search range ±15.5 more, necessary give valid/invalid information search range multiple times within processing time processing cycle 2,4,8 (550/806 cycles)). range vector which invalidated SKILL differs according modes (Field, Frame, DualPrime, horizontal search range, etc.). detail search invalidation control. DCNT assigned follows:
DCNT [3]: DCNT [2]: DCNT [1]: DCNT [0]: Upper direction invalid Lower direction invalid Left direction invalid Right direction invalid Valid Valid Valid Valid Invalid (Search end) Invalid (Search bottom end) Invalid (Search left end) Invalid (Search right end)
*Position leading image vertical direction first search window data Dual-Prime (DVSPO1) This used Field/Frame Dual-Prime mode. DVSPO1 indicates first pixel word first search window data. timing entering above controls, they input during same execution cycle when first search window input used during next execution cycle. DCNT assigned follows: DCNT [3:0] 0000: leading pixel DSWI [31:24] DCNT [3:0] 0001: leading pixel DSWI [23:16] DCNT [3:0] 0010: leading pixel DSWI [15:8] DCNT [3:0] 0011: leading pixel DSWI [7:0] *Position leading image vertical direction second search window data Dual-Prime (DVSPO2) This used Field/Frame Dual-Prime mode. DVSPO2 indicates first pixel word first search window data. timing entering above controls, they input during same execution cycle when first search window input used during next execution cycle. DCNT assigned follows: DCNT [3:0] 0000: leading pixel DSWI [31:24] DCNT [3:0] 0001: leading pixel DSWI [23:16] DCNT [3:0] 0010: leading pixel DSWI [15:8] DCNT [3:0] 0011: leading pixel DSWI *The center position first search window data Dual-Prime (DCNTR1) This setting used Field/Frame Dual-Prime mode. indicates center position first search window data used Dual-Prime (0.5 pixel unit displacement from 16x16 position within 18x18(10) field data). input same time when first search window image input used calculation next execution cycle.
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DCNT assigned follows: DCNT [3:0] 0000: displacement DCNT [3:0] 1010: Upper left direction DCNT [3:0] 1001: Upper right direction DCNT [3:0] 0110: Lower left direction DCNT [3:0] 0101: Lower right direction DCNT [3:0] 0010: Left direction DCNT [3:0] 0001: Right direction DCNT [3:0] 1000: Upper direction DCNT [3:0] 0100: Lower direction
(+0.0, +0.0) (-0.5, -0.5) (+0.5, -0.5) (-0.5, +0.5) (+0.5, +0.5) (-0.5, +0.0) (+0.5, +0.0) (+0.0, -0.5) (+0.0, +0.5)
center position second search window data Dual-Prime (DCNTR2) This setting used Field/Frame Dual-Prime mode. indicates center position second search window data used Dual-Prime (0.5 pixel unit displacement from 16x16 position within 18x18(10) field data). input same time when first search window image input used calculation next execution cycle. DCNT assigned follows: DCNT [3:0] 0000: displacement (+0.0, +0.0) DCNT [3:0] 1010: Upper left direction (-0.5, -0.5) DCNT [3:0] 1001: Upper right direction (+0.5, -0.5) DCNT [3:0] 0110: Lower left direction (-0.5, +0.5) DCNT [3:0] 0101: Lower right direction (+0.5, +0.5) DCNT [3:0] 0010: Left direction (-0.5, +0.0) DCNT [3:0] 0001: Right direction (+0.5, +0.0) DCNT [3:0] 1000: Upper direction (+0.0, -0.5) DCNT [3:0] 0100: Lower direction (+0.0, +0.5) *The sequence dynamic control inputs when Field/Frame Dual-Prime mode used dynamic control information input following sequence when Field/Frame Dual-Prime mode used. Valid/invalid control search range (SKILL) Leading pixel position first search window data (DVSPO1) Leading pixel position second search window data (DVSPO2) center position first search window data (DCNTR1) center position first search window data (DCNTR2)
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Operations Reset Operation When RESET request signal (RESETC) asserted logical "L", M65727 goes into RESET cycle. This RESET cycle continues cycles after RESET request signal negated. synchronized reset. sampled when clock rises. prohibited activation normal operation during RESET cycle. When using M65727, necessary execute this RESET operation before starting normal operation. RESETC signal must asserted over cycles. addition, there should least cycle space before ESYNC asserted order start normal operation. Fig. 4.1-1 shows RESET operation. WAIT Operation M65727 goes into WAIT cycle stops next cycle when clock enable signal(CEC) negated logical "H". values registers M65727 held that operations will able resume when clock enable signal asserted. clock enable signal sampled when clock rises. Fig. 4.2-1 shows WAIT operation. Motion Detection Operation order activate motion estimation operation, which normal M65727 operation, necessary, during Field/frame mode, input search window image data, template data, dynamic control input, addition requesting output activating execution cycle. case Field/Frame Dual-Prime mode, necessary input search window image data, input template data, request output, activate processing cycle, input dynamic control. Each operation will explained below. 4.3.1 Search Window Image Input Field/Frame mode data input M65727 during Field/Frame mode search window image data template data. search window image input performed parallel with independent motion estimation operation. search window image input starts cycle proceeding cycle where sync signal SSYNC asserted. When vertical search range ±7.5 used, DENSWC must asserted cycles during data input. When vertical search range ±15.5 used, DENSWC must asserted cycles. valid cycle refers cycle whose input data specified valid data enable specifying signal, DENSWC, search window port. Specifying this data enable allows wait data transfer using faster frame memory (SRAM). lower cost implementation when DRAM used frame memory, wait states useful allow slower data transfer. Search window image input order raster scan starting from upper left screen. Four vertical adjacent pixels input simultaneously using DSWI. data input must completed within execution cycle least cycles more space needed between ESYNC SSYNC. long this limitation obeyed, search window image input performed parallel with input template data actual arithmetic operation motion estimation.
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Fig. 4.3.1-1 shows input operation search window image. 4.3.2 Search Window Image Input Dual-Prime mode search window image Dual-Prime input parallel independent motion estimation operation. search window image input Dual-Prime starts cycle proceeding cycle which sync signal SSYNC asserted. M65727 uses valid cycles first search window when Field Dual-Prime mode After first search window complete SSYNC asserted begin input second search window. When Frame Dual-Prime estimation Mode used, there will valid cycles first search window, also valid cycles second search window. valid cycle means cycle whose input data specified valid DENSWC. search window image input data used Dual-Prime input order according raster scan starting from upper left screen. Four vertical adjacent pixels input simultaneously using DSWI. data input must completed within execution cycle least cycles more space needed between ESYNC SSYNC. long this limitation obeyed, search window image input Dual-Prime parallel with input template data actual operation motion estimation. Fig. 4.3.2-1 shows search window image data input operation used Dual-Prime. 4.3.3 Template Data Input Inputting template data performed independent parallel with motion estimation operation. Excluding Frame Dual-Prime mode, template data M65727 requires pixels macro block. case Frame Dual-Prime Estimation Mode, template includes pixels, but, pixels which last pixels dummy pixels) needed. Inputting template data starts cycle proceeding cycle which sync signal MSYNC asserted continues valid cycles. valid cycle refers cycle whose input data specified valid data enable specifying signal, DENMBC. possible, using this data enable specification, wait data transfer using SRAM frame memory. lower cost implementation when DRAM used frame memory, wait states useful allow slower data transfer. template data input scanning from upper left-hand corner vertical direction. data input must completed within execution cycle least cycles more space needed between ESYNC MSYNC. long this limitation obeyed, template input parallel with actual arithmetic operation motion estimation search window image input. Fig. 4.3.3-1 shows input operation template data.
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4.3.4 Output Request M65727 capable outputting result operation independently parallel with arithmetic operation motion estimation. output data output asserting OREQC, output request signal. output data becomes invalid when RESET cycle occurs before during motion estimation operation, when ESYNC signal asserted with space less than minimum number execution cycle (550 cycles) before output data becomes valid. Moreover, space between ESYNC OREQC must least cycles. output port uses tri-state output. This activated asserting OEC, output enable signal. Fig. 4.3.4-1 shows output operation. 4.3.5 Activation Execution Cycle execution cycle M65727 activated ESYNC, execution sync signal. minimum number cycles execution cycle depends vertical search range. When vertical search range ±7.5, required. When ±15.5, required. necessary assert ESYNC using interval greater than above minimum cycle. necessary input search window image data, template data, dynamic control information within execution cycle activated SYNC signal. allowed input above across ESYNC's. Fig. 4.3.5-1 shows execution cycle activated. 4.3.6 Dynamic Control Input M65727 allows control information input independent parallel arithmetic operation motion estimation. dynamic control information input repeated assertion DSYNC control data input must completed within execution cycle least cycles more space needed between ESYNC DSYNC. long this limitation obeyed, dynamic control information input parallel with search window image data actual operation motion estimation operation. Fig. 4.3.6-1 shows dynamic control input operation. 4.3.7 Number Cycles Needed (from Data Input Data Output) number cycles needed depends operating modes. minimum number cycles needed execution cycle (from assertion ESYNC assertion next ESYNC) depends vertical search range. When vertical search range ±7.5, cycles needed; when ±15.5, cycles needed. When Field/Frame Dual-Prime mode used, minimum cycles will cycles.
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number cycles needed various modes shown below. Field/Frame mode, horizontal search range ±7.5: execution cycles Field/Frame mode, horizontal search range ±15.5: execution cycles Field/Frame mode, horizontal search range ±31.5: execution cycles Field/Frame mode, horizontal search range ±63.5: execution cycles Field/Frame mode, horizontal search range ±127.5: execution cycles Field Dual-Prime mode: execution cycles Frame Dual-Prime mode: execution cycles
Others Macro Block Processing Missing Search Range M65727 conducts special processing when there some missing search range macro block being processed when portion search range needs making invalid. M65727 requires indicate, each execution cycle, whether range being searched valid invalid from outside. information concerning whether range being searched valid invalid (SKILL) input chip from DCNT when DSYNC asserted. However, meaning valid invalid given SKILL information differs according modes. *SKILL Information Field/Field mode case when SKILL information indicates that upper direction search range invalid (Search Top), M65727 invalidate following vectors. [integer-pel precision vector] vector, whose vertical component negative, invalidated. [half-pel precision vector] When vector, whose vertical component zero, selected best integer-pel precision vector, half-pel vector, whose vertical component negative, invalidated. SKILL information specifies that down direction search range invalid (Search Bottom), M65727 invalidates following vectors. [integer-pel precision vector] vector, whose vertical component positive, invalidated. [half-pel precision vector] When vector, whose vertical component zero, selected best integer-pel precision vector, half-pel vector, whose vertical component positive, invalidated. SKILL information specifies that both bottom directions search range invalid same time, (Search Bottom), M65727 invalidates following vectors. [integer-pel precision vector] vector, whose vertical component positive negative, invalidated. [half-pel precision vector] half-pel vector, whose vertical component positive negative, invalidated. result, selected motion vector zero vertical component.
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When left direction among search range specified invalid (Search Left) SKILL information when horizontal search range ±7.5, M65727 invalidates following vectors. [integer-pel precision vector] vector, whose horizontal component negative, invalidated. [half-pel precision vector] When vector, whose horizontal component zero, selected best integer-pel precision vector, half-pel vector, whose horizontal component negative, invalidated. case when SKILL information specifies right direction among search range invalid (Search Right) when horizontal search range ±7.5, M65727 invalidates following vectors. [integer-pel precision vector] vector, whose horizontal component positive, invalidated. [half-pel precision vector] When vector, whose horizontal component zero, selected best integer-pel precision vector, half-pel vector, whose horizontal component positive, invalidated. Moreover, both left right directions among search range made invalid same time SKILL information (Search Left Right) when horizontal search range is±7.5, M65727 invalidates following vectors. [integer-pel precision vector] vector, whose horizontal component positive negative, invalidated. [half-pel precision vector] half-pel vector, whose horizontal component positive negative, invalidated. result, selected motion vector zero horizontal component. Therefore, search top, search down, search left, search right specified same time during horizontal search range ±7.5, only vector selected. When using ±15.5 more horizontal search range, SKILL information specifies that left direction among search range invalid (Search Left), M65727 invalidates following vectors. [integer-pel precision vector] vector invalidated. [half-pel precision vector] When vector, whose horizontal position most left search range current execution cycle, selected best integer-pel precision vector, half-pel vector, whose horizontal component negative, invalidated. When SKILL information specifies that right direction among search range invalid(search right) using ±15.5 more horizontal search range, M65727 invalidates following vectors.
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[integer-pel precision vector] vector, whose horizontal position isn't most left search range current execution cycle invalidated. [half-pel precision vector] When vector, whose horizontal position most left search range current execution cycle, selected best integer-pel precision vector, half-pel vector, whose horizontal component positive, invalidated. When horizontal search range ±15.5 more, prohibited specify search left search right same time except specifying invalid (See below). When horizontal search range ±15.5 more, search range made invalid(All invalid) (DCNT [3:0]: 1111) SKILL information, M65727 will make motion vector said search range invalid. possible limit range combining above mentioned SKILL information. *SKILL information used Field/Frame Dual-Prime mode When direction search range made invalid SKILL information (Search Top), M65727 invalidates Dual-Prime vector whose vertical component negative. When down direction among search range specified invalid SKILL information (Search Down), M65727 makes Dual-Prime vector search range invalid vertical component positive. When left direction among search range made invalid SKILL information (Search Left), M65727 invalidates Dual-Prime vector search range horizontal component negative. SKILL information specifies that right direction among search range invalid (Search Right), M65727 invalidates Dual-Prime vector search range whose horizontal component positive. Priority Order Distortion Equivalent Vector there multiple motion vectors which gives minimum distortion, necessary determine final motion vector giving them priority order. M65727 decided following priority order according non-expansion expansion upper range expansion lower range. *Priority order distortion equivalent vector non-expansion During non-expansion mode, distortion equivalent vector priority order given following equation with Vector (0,0) highest priority location. smaller value higher priority. *Priority order distortion equivalent vector expansion upper During expansion upper range mode, distortion equivalent vector uses Vector +8/+16) location priority uses priority order given following equation. (-Y+16) smaller value higher priority.
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Priority order distortion equivalent vector expansion lower During expansion lower range mode, distortion equivalent vector uses Vector -8/-16) location priority uses priority order given following equation. (Y+16) smaller value (X,Y), higher priority. Each mode vectors having same priority. However, among them, motion vector horizontal direction close negative infinity same, side whose dynamic vector vertical direction closer negative infinity priority. Fig. 5.2-1 shows order priority distortion equivalent vector. Detail Vector Search Range case non-expansion mode, motion vector search range M65727 ±7.5/±15.5 displacement vertical direction. When integer precision search mode specified, search range ±7/±15. When integer precision search mode specified, horizontal search ranges become follows: ±15.5 ±15.0, ±31.5 ±31.0, ±63.5 ±63.0, ±127.5 ±127.0 Formats External Frame Memory (Search Window Image Memory) external frame memory (Search window image memory) used M65727 formats. field format other frame format. Field format indicates state which field images stored succession. word bits) stores pixels lined succession vertically field. Frame format indicates that frame images stored succession. Within word bits), four continuous pixels stored vertically within frame. (Field pixels different parity alternately stored.) necessary that boundary pixels stored word must agree with boundary macro block matter which format used. format external frame memory depends mode follows: *Field mode Field format only *Frame mode Field format frame format *Field Dual-Prime mode Field format only *Frame Dual-Prime mode Field format only Expansion Search Range Controlling Validity Search Range M65727 chip capable searching ±7.5 pixels horizontal direction ±7.5/±15.5 vertical direction. Fig. 5.5-1 shows controlling conditions necessary chip operation. When horizontal search range expanded (±15.5 ±127.5), following number chips needed. ±15.5: chips ±31.5: chips ±63.5: chips ±127.5: chips Fig. 5.5-2 shows conditions needed search range control when horizontal search range expanded.
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number chips needed expanded vertical search range (±16/±32 more) shown below. allowed number chips expanded vertical search range. When ±7.5 specified chip vertical search range, ±16.0: chips ±32.0: chips ±64.0: chips When ±15.5 specified chip vertical search range, ±32.0: chips ±64.0: chips ±128.0: chips Fig. 5.5-3 shows conditions needed control expanded vertical search range. Fig. 5.5-4 shows relation between output vertical vector real vertical vector. When both horizontal vertical ranges expanded, product number chips needed above search ranges becomes number chips needed. Operational Timing Data (Control) sent M65727 must done within pre-determined execution cycles. data (Control) performed during different execution cycles operations M65727 guaranteed. Fig. 5.6-1 shows operational timing M65727. Treatment Final M65727 designed that processes successive horizontally. special treatment required final (when horizontal search range expansion multi-chip, each final processed each M65727 requires special treatment). special treatment means that user must input every control data M65727 extra (dummy) successive will processing until out-put final finished. Mode Change during Processing sequence mode change during processing shows below. Finish output necessary previous mode Change operation mode mode pins Reset M65727 Input control data operation mode
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Electrical Characteristics Others Electrical Characteristics 6.1.1 Maximum Ratings +70°C) Parameters Topr Tstg Description Supply Voltage Input Voltage Output Voltage Power Dissipation Power Dissipation Operating Temperature Storage Temperature Test Condition Value -0.3V +4.0V -0.3V VDD+0.3V -0.3V VDD+0.3V 1.75W 2.1W +70°C -40°C +125°C Units
27MHz 40.5MHz
6.1.2 Operating Range +70°C) Value Typ.
Parameters Description Test Condition Min. Supply Voltage 3.15 Ground Voltage Input HIGH Voltage CLKI Vddx0.8 Others Input Voltage CLKI Others
Max. 3.45 Vddx0.2
Units
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6.1.3 Electrical Characteristics (Vdd 3.3±0.15V, +70°C) Value Typ.
Max. IOZH IOZL ICCd ICCs
Description Output HIGH Voltage Output Voltage Input Leakage Current
Output OFF(Hi-Z) Current
Supply Current (Operating) Supply Current (Static)
Test Condition -4mA +4mA Vdd-0.1V Vss+0.1V Vdd-0.1V Vss+0.1V 40.5MHz
Min.
Units
6.1.4 Switching Characteristics (Vdd 3.3±0.15V, +70°C) Value Typ.
Parameters tPLH tPHL tPLZ tPHZ tPZL tPZH
Description Clock Data Output Disable Time Enable Time
Test Condition
Min.
Max.
Units
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6.1.5 Set-up Hold Times (Vdd 3.3±0.15V, +70°C) Value Typ.
Parameters tc(CLK) tr(CLK) tf(CLK) twh(CLK) twl(CLK) tsu(D) th(D) ts(C) th(C)
Description Input Clock Cycle Clock Rise Time Clock Fall Time Clock HIGH Pulse Width Clock Pulse Width Data Set-up Time Relative Clock Data Hold Time Relative Clock Control Set-up Time Relative Clock Control Hold Time Relative Clock
Test Condition
Min. 24.6
0.45 0.45
Max. 0.55 0.55
Units
Fig. 6.1.5-1 shows timing diagram each parameter. Package M65727 housed plastic 152-pin 28mm 28mm body HQFP. Fig. 6.2-1 shows overview package, fig. 6.2-2 table 6.2-1 show configuration. Thermal Management M65727 designed operate 27MHz 40.5MHz. When 27MHz operation, thermal management required (The M65727 operate still air.). But, when 40.5MHz, some thermal management required. required thermal management follows: Forced cooling 0.5m/s Forced cooling heat sink (for example: Aluminum table 28mm 28mm 2mm)
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Fig. 3.1-1 Overall
Search Window Image Dual-Prime
Configuration
M65727
DSWI[31:0]
Integer-pel Unit
Half-pel /Dual-Prime Unit
Input Unit
DMBI[7:0] Motion Detection Unit
DOUT[7:0] Output Unit
Clock Generator Control Unit
DSWI: DMBI: DOUT: MAE:
Search window input Template input Output port Mean absolute difference Motion vector
Fig. 3.3.7-1 Correspondence between blocks vertival vector output
1chip ±7.5 vector 16x16 t_-4 b_-4 t_-3 b_-3 t_-2 b_-2 t_-1 b_-1 t_+1 b_+1 t_+2 b_+2 t_+3 b_+3 t_+4 bottom b_-4 t_-3 b_-3 t_-2 b_-2 t_-1 b_-1 t_+1 b_+1 t_+2 b_+2 t_+3 b_+3 t_+4 b_+4
1chip ±15.5 vector 16x16 t_-8 b_-8 t_-7 b_-7 t_-6 b_-6 t_-5 b_-5 t_-4 b_-4 t_-3 b_-3 t_-2 b_-2 t_-1 b_-1 t_+1 b_+1 t_+2 b_+2 t_+3 b_+3 t_+4 b_+4 t_+5 b_+5 t_+6 b_+6 t_+7 b_+7 t_+8 bottom b_-8 t_-7 b_-7 t_-6 b_-6 t_-5 b_-5 t_-4 b_-4 t_-3 b_-3 t_-2 b_-2 t_-1 b_-1 t_+1 b_+1 t_+2 b_+2 t_+3 b_+3 t_+4 b_+4 t_+5 b_+5 t_+6 b_+6 t_+7 b_+7 t_+8 b_+8
Fig. 5.5-4c Correspondence between blocks vertival vector output chips expansion when vertival search range ±15.5 2-chips ±32.0 vector t_-16 b_-16 t_-15 b_-15 t_-14 b_-14 t_-13 b_-13 t_-12 b_-12 t_-11 b_-11 t_-10 b_-10 t_-9 b_-9 t_-8 b_-8 t_-7 b_-7 t_-6 b_-6 t_-5 b_-5 t_-4 b_-4 t_-3 b_-3 t_-2 b_-2 t_-1 b_-1 b_-16 t_-15 b_-15 t_-14 b_-14 t_-13 b_-13 t_-12 b_-12 t_-11 b_-11 t_-10 b_-10 t_-9 b_-9 t_-8 b_-8 t_-7 b_-7 t_-6 b_-6 t_-5 b_-5 t_-4 b_-4 t_-3 b_-3 t_-2 b_-2 t_-1 b_-1 t_+1 b_+1 t_+2 b_+2 t_+3 b_+3 t_+4 b_+4 t_+5 b_+5 t_+6 b_+6 t_+7 b_+7 t_+8 b_+8 t_+9 b_+9 t_+10 b_+10 t_+11 b_+11 t_+12 b_+12 t_+13 b_+13 t_+14 b_+14 t_+15 b_+15 t_+16 t_+1 b_+1 t_+2 b_+2 t_+3 b_+3 t_+4 b_+4 t_+5 b_+5 t_+6 b_+6 t_+7 b_+7 t_+8 b_+8 t_+9 b_+9 t_+10 b_+10 t_+11 b_+11 t_+12 b_+12 t_+13 b_+13 t_+14 b_+14 t_+15 b_+15 t_+16 b_+16 16*16 ME#1 bottom 16*16 bottom ME#2
Fig. 5.5-4d Correspondence between blocks vertival vector output chips expansion when vertival search range ±15.5
4-chips ±64.0 ME#1 bottom b_-32 t_-31 b_-31 t_-30 b_-30 t_-29 b_-29 t_-28 b_-28 t_-27 b_-27 t_-26 b_-26 t_-25 b_-25 t_-24 b_-24 t_-23 b_-23 t_-22 b_-22 t_-21 b_-21 t_-20 b_-20 t_-19 b_-19 t_-18 b_-18 t_-17 b_-17 t_-16 b_-16 t_-16 b_-16 t_-15 b_-15 t_-14 b_-14 t_-13 b_-13 t_-12 b_-12 t_-11 b_-11 t_-10 b_-10 t_-9 b_-9 t_-8 b_-8 t_-7 b_-7 t_-6 b_-6 t_-5 b_-5 t_-4 b_-4 t_-3 b_-3 t_-2 b_-2 t_-1 b_-1 b_-16 t_-15 b_-15 t_-14 b_-14 t_-13 b_-13 t_-12 b_-12 t_-11 b_-11 t_-10 b_-10 t_-9 b_-9 t_-8 b_-8 t_-7 b_-7 t_-6 b_-6 t_-5 b_-5 t_-4 b_-4 t_-3 b_-3 t_-2 b_-2 t_-1 b_-1 t_+1 b_+1 t_+2 b_+2 t_+3 b_+3 t_+4 b_+4 t_+5 b_+5 t_+6 b_+6 t_+7 b_+7 t_+8 b_+8 t_+9 b_+9 t_+10 b_+10 t_+11 b_+11 t_+12 b_+12 t_+13 b_+13 t_+14 b_+14 t_+15 b_+15 t_+16 t_+1 b_+1 t_+2 b_+2 t_+3 b_+3 t_+4 b_+4 t_+5 b_+5 t_+6 b_+6 t_+7 b_+7 t_+8 b_+8 t_+9 b_+9 t_+10 b_+10 t_+11 b_+11 t_+12 b_+12 t_+13 b_+13 t_+14 b_+14 t_+15 b_+15 t_+16 b_+16 16*16 bottom 16*16 botom t_-32 b_-32 t_-31 b_-31 t_-30 b_-30 t_-29 b_-29 t_-28 b_-28 t_-27 b_-27 t_-26 b_-26 t_-25 b_-25 t_-24 b_-24 t_-23 b_-23 t_-22 b_-22 t_-21 b_-21 t_-20 b_-20 t_-19 b_-19 t_-18 b_-18 t_-17 b_-17 t_-16 ME#2 ME#3 16*16 ME#4 t_+16 b_+16 t_+17 b_+17 t_+18 b_+18 t_+19 b_+19 t_+20 b_+20 t_+21 b_+21 t_+22 b_+22 t_+23 b_+23 t_+24 b_+24 t_+25 b_+25 t_+26 b_+26 t_+27 b_+27 t_+28 b_+28 t_+29 b_+29 t_+30 b_+30 t_+31 b_+31 t_+32 bottom b_+16 t_+17 b_+17 t_+18 b_+18 t_+19 b_+19 t_+20 b_+20 t_+21 b_+21 t_+22 b_+22 t_+23 b_+23 t_+24 b_+24 t_+25 b_+25 t_+26 b_+26 t_+27 b_+27 t_+28 b_+28 t_+29 b_+29 t_+30 b_+30 t_+31 b_+31 t_+32 b_+32
vector
16*16
Fig. 5.5-4a Correspondence between blocks vertival vector output chips expansion when vertival search range ±7.5 2-chips ±16.0 vector t_-8 b_-8 t_-7 b_-7 t_-6 b_-6 t_-5 b_-5 t_-4 b_-4 t_-3 b_-3 t_-2 b_-2 t_-1 b_-1 b_-8 t_-7 b_-7 t_-6 b_-6 t_-5 b_-5 t_-4 b_-4 t_-3 b_-3 t_-2 b_-2 t_-1 b_-1 t_+1 b_+1 t_+2 b_+2 t_+3 b_+3 t_+4 b_+4 t_+5 b_+5 t_+6 b_+6 t_+7 b_+7 t_+8 t_+1 b_+1 t_+2 b_+2 t_+3 b_+3 t_+4 b_+4 t_+5 b_+5 t_+6 b_+6 t_+7 b_+7 t_+8 b_+8 16*16 ME#1 bottom 16*16 bottom ME#2
Fig. 5.5-4b Correspondence between blocks vertival vector output chips expansion when vertival search range ±7.5
4-chips ±32.0 ME#1 bottom b_-16 t_-15 b_-15 t_-14 b_-14 t_-13 b_-13 t_-12 b_-12 t_-11 b_-11 t_-10 b_-10 t_-9 b_-9 t_-8 b_-8 t_-8 b_-8 t_-7 b_-7 t_-6 b_-6 t_-5 b_-5 t_-4 b_-4 t_-3 b_-3 t_-2 b_-2 t_-1 b_-1 b_-8 t_-7 b_-7 t_-6 b_-6 t_-5 b_-5 t_-4 b_-4 t_-3 b_-3 t_-2 b_-2 t_-1 b_-1 t_+1 b_+1 t_+2 b_+2 t_+3 b_+3 t_+4 b_+4 t_+5 b_+5 t_+6 b_+6 t_+7 b_+7 t_+8 t_+1 b_+1 t_+2 b_+2 t_+3 b_+3 t_+4 b_+4 t_+5 b_+5 t_+6 b_+6 t_+7 b_+7 t_+8 b_+8 16*16 bottom 16*16 bottom 16*16 t_-16 b_-16 t_-15 b_-15 t_-14 b_-14 t_-13 b_-13 t_-12 b_-12 t_-11 b_-11 t_-10 b_-10 t_-9 b_-9 t_-8 ME#2 ME#3 ME#4 t_+8 b_+8 t_+9 b_+9 t_+10 b_+10 t_+11 b_+11 t_+12 b_+12 t_+13 b_+13 t_+14 b_+14 t_+15 b_+15 t_+16 bottom b_+8 t_+9 b_+9 t_+10 b_+10 t_+11 b_+11 t_+12 b_+12 t_+13 b_+13 t_+14 b_+14 t_+15 b_+15 t_+16 b_+16
vector
16*16
CLKI
RESETC
Reset cycles
Sample point
Fig. 4.1-1 Reset operation
CLKI
Wait cycle
Wait cycles
Sample point
Fig. 4.2-1 Wait operation
Fig. 5.2-1a order priority distortion equivarent vector non-expansion mode
smaller value, higer priority. P(X,Y)
Fig. 5.2-1c order priority distortion equivarent vector lower-range expansion mode
smaller value, higer priority. P(X,Y)
Fig. 5.2-1b order priority distortion equivarent vector upper-range expansion mode
smaller value, higer priority. P(X,Y)
Fig. 5.5-1a Horizontal search range control chip
used estimate vectors points). However, invalidated.
position Left edge Normal Right edge
Search-Left valid Search-Right
Fig. 5.5-2a
used estimate vectors points). used estimate vectors points).
Horizontal
However, invalidated.
search range control 2-chips
position Left edge Normal Right edge invalid valid valid
Search-Left valid Search-Right
Fig. 5.5-2b
Horizontal
search range control 4-chips
used estimate vectors points). used estimate vectors points). used estimate vectors points). used estimate vectors points).
However, invalidated.
position
Left edge Left edge Normal Right edge Right edge
invalid invalid valid valid valid
invalid Search-Left valid valid valid
Search-Left valid valid valid Search-Right
valid valid valid Search-Right invalid
Fig. 5.5-2c
Horizontal
search range control 8-chips
used estimate vectors -49. used estimate vectors -33. used estimate vectors -17. used estimate vectors used estimate vectors +15. used estimate vectors +31. used estimate vectors +47. used estimate vectors +63. invalid Search-Left Search-Left valid valid valid valid valid valid invalid invalid Search-Left valid valid valid valid valid valid Search-Left valid valid valid valid valid valid valid Search-Right valid valid valid valid valid valid valid Search-Right invalid valid valid valid valid valid valid Search-Right invalid invalid valid valid valid valid valid Search-Right invalid invalid invalid
position
Left edge Left edge Left edge Left edge Normal Right edge Right edge Right edge Right edge
invalid invalid invalid invalid valid valid valid valid valid
invalid invalid invalid Search-Left valid valid valid valid valid
Fig. 5.5-1b Vertical search range control 1-chip
chip estimates vectors -7.5 +7.5 non-expansion mode.
chip estimates vectors -8.0 +8.0 vertical expansion mode.
ME#1
chip estimates vectors -15.5 +15.5 non-expansion mode. chip estimates vectors -16.0 +16.0 vertical expansion mode.
ME#1
position edge Normal Bottom edge
ME#1 Search-Top valid Search-Bottom
Fig. 5.5-1c Vertical search range control 1-chip
t_-8 b_-8
t_-4 b_-4
t_-4 b_-4
t_+8 b_+8
t_+4 b_+4 t_+4 b_+4 t_+4 b_+4
t_+4 b_+4
t_+8 b_+8
t_+4 b_+4
t_+4 b_+4
t_+8 b_+8
Fig. 5.5-2d Horizontal search range control 16-chips
-128 -113-112
-97-96
+111
+127
+111 +112 +127
-128
-112
SW10 used estimates vectors +15. SW10 SW11 used estimates vectors +31. SW11 SW12 used estimates vectors +47. SW12 SW13 used estimates vectors +63. SW13 SW14 used estimates vectors +79. SW14 SW15 used estimates vectors +95. SW15 SW16 used estimates vectors +111. SW16 SW17 used estimates vectors +112 +127. However, -128 invalidated.
invalid invalid invalid invalid invalid Search-L valid valid valid valid valid valid valid valid valid valid valid invalid invalid invalid invalid Search-L valid valid valid valid valid valid valid valid valid valid valid valid invalid invalid invalid Search-L valid valid valid valid valid valid valid valid valid valid valid valid valid invalid invalid Search-L valid valid valid valid valid valid valid valid valid valid valid valid valid valid invalid Search-L valid valid valid valid valid valid valid valid valid valid valid valid valid valid valid Search-L valid valid valid valid valid valid valid valid valid valid valid valid valid valid valid Search-R
SW10
SW11
SW12
SW13
SW14
SW15
SW16
SW17
used estimates vectors -128 -113. used estimates vectors -112 -97. used estimates vectors -81. used estimates vectors -65. used estimates vectors -49. used estimates vectors -33. used estimates vectors -17. used estimates vectors
position
SW10 SW11 SW12 SW13 SW14 SW15 SW16 valid valid valid valid valid valid valid valid valid valid valid valid valid valid valid Search-R invalid valid valid valid valid valid valid valid valid valid valid valid valid valid valid Search-R invalid invalid valid valid valid valid valid valid valid valid valid valid valid valid valid Search-R invalid invalid invalid valid valid valid valid valid valid valid valid valid valid valid valid Search-R invalid invalid invalid invalid valid valid valid valid valid valid valid valid valid valid valid Search-R invalid invalid invalid invalid invalid valid valid valid valid valid valid valid valid valid valid Search-R invalid invalid invalid invalid invalid invalid valid valid valid valid valid valid valid valid valid Search-R invalid invalid invalid invalid invalid invalid invalid
Left edge Left edge Left edge Left edge Left edge Left edge Left edge Left edge Normal Right edge Right edge Right edge Right edge Right edge Right edge Right edge Right edge
invalid invalid invalid invalid invalid invalid invalid invalid valid valid valid valid valid valid valid valid valid
invalid invalid invalid invalid invalid invalid invalid Search-L valid valid valid valid valid valid valid valid
invalid invalid invalid invalid invalid invalid Search-L valid valid valid valid valid valid valid valid valid valid
Fig. 5.5-3c Vertical search range control 2-chips
t_-8 b_-8
t_-4 b_-4
t_-4 b_-4
t_-8 b_-8 t_+4 b_+4
t_-4 b_-4
t_-4 b_-4
t_+4 b_+4
t_-4 b_-4
t_+8 b_+8
t_+4 b_+4
t_-4 b_-4 t_+4 b_+4
ME#1
t_+4 b_+4
t_+8 b_+8
t_+4 b_+4
ME#2
Fig. 5.5-3d Vertical search range control 2-chips chips operated expansion mode. ME#1 estimates vectors -32.0 0.0. ME#2 estimates vectors +32.0.
total search range -32.0 +32.0
ME#1
ME#2
position edge edge Normal Bottom edge Bottom edge
ME#1 invalid Search-Top valid valid valid
ME#2 valid valid valid Search-Bottom invalid
Fig. 5.5-3f Vertical search range control 2-chips
t_-16 b_-16 t_-8 b_-8
t_-12 b_-12
t_-4 b_-4
t_-8 b_-8
t_-16 b_-16
t_-8 b_-8
t_-4 b_-4
t_-4 b_-4 t_+4 b_+4
t_-8 b_-8 t_+8 b_+8
t_-8 b_-8
t_-4 b_-4 t_+4 b_+4
t_+4 b_+4
t_-4 b_-4
t_+8 b_+8
t_+8 b_+8
ME#1
t_+4 b_+4
t_-8 b_-8
t_-4 b_-4 t_+4 b_+4
t_+8 b_+8 t_+16 b_+16 t_+8 b_+8
t_+12 b_+12
t_+4 b_+4
t_+16 b_+16
t_+8 b_+8
ME#2
Fig. 5.6-1a Operation timing 1-chip (vertical search range ±7.5)
nSW1
execution cycle Nom. Nom. nSW1 nSW2 nSW3 nSW4 nMB1 nMB2 nMB3 nSW1 nSW2 nSW3 nMB1 nMB2
input
input
D-cont. input
array input
processing
Search-Top, Search-Bottom, Search-Left, Search-Right, Nom. valid
Fig. 5.6-1b Operation timing 1-chip (vertical search range ±15.5)
nSW1
execution cycle Nom. Nom. nSW1 nSW2 nSW3 nSW4 nMB1 nMB2 nMB3 nSW1 nSW2 nSW3 nMB1 nMB2
input
input
D-cont. input
array input
processing
cont.
processing
Output
Search-Top, Search-Bottom, Search-Left, Search-Right, Nom. valid
Fig. 5.6-1c Operation timing horizontal 2-chips expansion (vertical search range ±15.5)
execution cycle
Search-Top, Search-Bottom, Search-Left, Search-Right, Nom. valid, Inv. invalid
ME#1 input input D-cont. input Inv. array input processing cont. processing Output Nom. Nom. Nom. Inv. Nom. Inv.
Inv.
nSW1
nSW2 nMB2 nSW1
nSW3 nSW2 nMB2
nSW4 nMB4 Inv. nSW3 nMB2
nSW5 nSW4 nMB4 Inv.
nSW6 nMB6 Nom. nSW5 nMB4 nMB2
ME#2 input input D-cont. input array input processing cont. processing Output Inv. Inv. Nom.
Nom.
nSW1 nMB1 Inv.
nSW2 nSW1 nMB1 Inv.
nSW3 nMB3 nSW2 nMB1
nSW4 nSW3 nMB3
nSW5 nMB5 Nom. nSW4 nMB3 nMB1
nSW6 Nom. nSW5 nMB3 Nom. nMB1
tc(CLK) twh(CLK) twl(CLK)
tf(CLK)
tr(CLK)
CLKI
tsu(D)
th(D)
DATA(*)
tsu(C)
th(C)
CONTROL(*)
tpLH tpHL
DOUT<7:0>
DATA DSWI<31:0>, DMBI<7:0> CONTROL Input Pins without DSWI, DMBI, CLKI,
1.3V
1.3V
tPLZ
DOUT<7:0>
tPHZ
tPZL tPZH
Fig. 6.1.5-1 Timing Diagram
TEST<4> TEST<3> TEST<2> TEST<1> TEST<0> DSWI<31> DSWI<30> DSWI<29> DSWI<28> DSWI<27> DSWI<26> DSWI<25> DSWI<24> DSWI<23> DSWI<22> DSWI<21> DSWI<20> DSWI<19> DSWI<18> DSWI<17> DSWI<16>
DCNT<0> DCNT<1> DCNT<2> DCNT<3> DMBI<0> DMBI<1> DMBI<2> DMBI<3> DMBI<4> DMBI<5> DMBI<6> DMBI<7> RESETC OREQC MSYNC ESYNC SSYNC DSYNC
Fig. 6.2-2 Configuration M65727FP
Table 6.2-1 Configuration M65727FP
number name number name number name number name
TEST<4> TEST<3> TEST<2> TEST<1> TEST<0> DSWI<31> DSWI<30> DSWI<29> DSWI<28> DSWI<27> DSWI<26> DSWI<25> DSWI<24> DSWI<23> DSWI<22> DSWI<21> DSWI<20> DSWI<19> DSWI<18> DSWI<17> DSWI<16>
DSWI<15> DSWI<14> DSWI<13> DSWI<12> DSWI<11> DSWI<10> DSWI<9> DSWI<8> DSWI<7> DSWI<6> DSWI<5> DSWI<4> DSWI<3> DSWI<2> DSWI<1> DSWI<0> DOUT<7> DOUT<6> DOUT<5> DOUT<4> DOUT<3> DOUT<2> DOUT<1> DOUT<0>
DSYNC SSYNC ESYNC MSYNC OREQC RESETC DMBI<7> DMBI<6> DMBI<5> DMBI<4> DMBI<3> DMBI<2> DMBI<1> DMBI<0> DCNT<3> DCNT<2> DCNT<1> DCNT<0>
DENMBC DENSWC FMFMT HLFPL EXTND<1> EXTND<0> HSIZE<2> HSIZE<1> HSIZE<0> CLKI MODE<1> MODE<0> VSIZE TEST<6> TEST<5>
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