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Configuring Keil PK51 Tools Support 24-Bit Contiguous Addressing Mode
performance 8-bit microcontrollers continues advance, does application complexity into which these microcontrollers embedded. These applications naturally demand larger amounts program data memory. satisfy this demand, many Dallas Semiconductor microcontroller products incorporate user-selectable extended addressing modes. these extended addressing modes, contiguous addressing mode, capable supporting contiguous (flat) program/data memory ranges 16MB. This application note demonstrates configure KeilPK51 Version 6.11 later tools support contiguous addressing mode illustrates might modify files settings address example DS80C390 memory configuration, which provided. While example focuses DS80C390 microcontroller, ideas concepts discussed easily adaptable other devices that support extended addressing, including DS80C400, DS5240, DS5250.
Contiguous Addressing Mode Requires Tool Support
Dallas Semiconductor microcontrollers that support contiguous addressing mode also support traditional 16-bit 8051 addressing mode extended 24-bit (SFR-facilitated) paged mode. extended 24-bit addressing modes, contiguous mode provides greater application benefit therefore, only fully supported Keil tools. Hence, contiguous mode operation discussed hereafter. support extended contiguous addressing mode, some basic chip-hardware controls enhancements implemented: full 24-bit program counter, full 24-bit data pointers, bits selectively enable higher order address lines, program/data memory chip enables, contiguous addressing mode itself. When contiguous mode enabled, allow direct access full address range, cycle and/or operand byte count several operations (ACALL, LCALL, AJMP, LJMP, RET, RETI, DPTR, #data24) increased from that standard 8051. Detailed information about contiguous mode-modified instructions found User's Guide that corresponds with your Dallas Semiconductor microcontroller Since modified instructions, many cases, must coded with additional address byte, since program/data memory extend well beyond 64kB, 8051 development tools must explicitly configured support contiguous addressing mode generate executable program code that capable reaching extended memory ranges. Keil's tools (PK51 Version 6.11 up), which support extended 8051 variants, easily configured correctly produce code executable contiguous addressing mode.
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µVision2 Project Options Select Device Target
When creating project, prompted select from µVision2 device database. Checkboxes provided "Select Device Target-CPU" dialog selecting LX51 linker place BL51 AX51 assembler place A51. contiguous mode, both these boxes should checked, shown below. Both these boxes have been checked DS80C390 example project (Figure
Figure SELECTION EXTENDED LINKER (LX51) ASSEMBLER (AX51)
Enable these options dialog box: Project Select Device Target
(Note: AX51 checkbox visible until LX51 checkbox been checked)
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Startup Initialization Code
linker automatically uses default startup (startup.a51) init (init.a51) files from \c51\lib directory project when none have been included individual project directory. startup init codes executed after each system reset responsible following basic operations: Clearing data memory (idata, xdata, pdata) defined start, length file constants Initializing re-entrant stack pointer given memory model (small, large, compact) Initializing global variables Jump main()
default startup.a51 file does contain code necessary establish memory chip-enable boundaries configure on-chip microcontroller hardware into contiguous addressing mode. This means that default file capable accessing/initializing memory bytes that might want initialize before proceeding main(). solve this problem, startup file should copied into individual project directory customized.
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Customizing Startup File DS80C390
START390.A51 file provided Keil Software already adds some settings specific DS80C390 chip, used starting point minimize changes required your DS80C390 project rolling. define extended contiguous memory specific your hardware within START390.A51 file, code added properly define writes) desired chip-enable output pins memory sizes attached those chip-enable pins. Example code associated constants accomplish this memory definition given below. This code, along with code that invokes contiguous addressing mode, should executed startup file before attempts access extended memory areas. Additionally, xdata initialization loop should allow intialization xdata beyond normal 64kB boundary. START390.A51 file provided Keil Software currently provides this extension xdata initialization loop.
DS80C390 Chip Specific Constants P4CNT.5-3 defines maximum addressable memory PCEx signal P4CNT5_3 000B 000B 32kB (A15-A0 enabled) 100B 128kB (A16-A0 enabled) 101B 256kB (A17-A0 enabled) 110B 512kB (A18-A0 enabled) 111B (A19-A0 enabled) other invalid selection P4CNT.2-0 define which signals enable P4CNT2_0 000B 000B none 100B enable 101B enable CE0, 110B enable CE0, CE1, 111B enable CE0, CE1, CE2, other invalid selection P5CNT.2-0 define which PCEx signals enable P5CNT2_0 000B 000B none 100B enable PCE0 101B enable PCE0, PCE1 110B enable PCE0, PCE1, PCE2 111B enable PCE0, PCE1, PCE2, PCE3 other invalid selection Code which makes DS80C390 chip specific constants TA,#0xAA Enable access P4CNT TA,#0x55 P4CNT_VAL (P4CNT5_3 (P4CNT2_0) address (Axx) enables P4CNT,#P4CNT_VAL TA,#0xAA Enable access P5CNT TA,#0x55 P5CNT,#P5CNT2_0 PCEx enables
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Customizing INIT.A51 File DS80C390
allow initialization global far- memory variables within contiguous addressing mode, following directives must included init.a51 file. customized init.a51 file should then added last file your target project source files.
Memory Support application contains variables memory space that initialized, need following define XBANK when variables should initialized $set (XBANK Dallas 390/400/5240 Contiguous Mode using Dallas Contiguous Mode need following define DS390 when runs Dallas Contiguous Mode $set (DS390
µVision2 Project Options Options Target
project options target target dialog box, "code size" selection should made from list options. contiguous mode options available: "contiguous mode: 512kb program" "contiguous mode:16mb program." When using contiguous mode with less than 512kb program code, select "contiguous mode: 512kb program" size option that tools optimally generate 19-bit acall ajmp instructions. your program size between 512kb 16mb, select "contiguous mode: 16mb program" size that 24-bit lcall ljmp instructions generated. "code size" selection configures tools, including debugger simulator, extended contiguous addressing mode. Please remember, however, that proper startup code sequence must still included your project order chip hardware configured correctly. DS80C390 CPU, same Project Options Target Target dialog also contains checkbox locate on-chip SRAM locatio 0xF000-0xFFFF. This checkbox should only checked IDM1:0 bits contained MCON used define this specific address range on-chip range. IDM1:0 bits define SRAM address range elsewhere, checkbox should used. Instead, correct location SRAM should specified "Off-chip Xdata memory RAM" start size fields, alternatively User class entry Project Options Target LX51 Locate dialog box. order linker recognize memory definitions specified Project Options Target Target dialog box, "Use Memory Layout from Target Dialog" checkbox Project Options Target LX51 Locate dialog must checked. These methods defining specific HDATA address ranges shown figures below. Please remember, again, that this definition Keil toolset that proper startup code sequence must included your project order chip hardware configured correctly.
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Figure ON-CHIP SRAM ADDRESS RANGE SPECIFIED "START," "SIZE" PROJECT OPTIONS TARGET TARGET DIALOG
On-chip SRAM location specified Start, Size fields. On-chip XRAM Checkbox, which checked. Note: Project Options Target LX51 Locate: Memory Layout from Target Dialog checkbox must also checked.
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Figure ON-CHIP SRAM ADDRESS MANUALLY SPECIFIED PROJECT OPTIONS TARGET LX51 LOCATE DIALOG
Internal SRAM manually defined User class. Note that this definition addition those defined Target dialog box.
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Additional Extended Memory Spaces Types
addition memory classes classic 8051 CPU, extended 8051 tool chain adds three additional memory classes (see list below). These memory classes fully described Keil's Assembler/Utilities User's Guide (A51.pdf), Chapter Architecture Overview, Extended 8051 Variants. CLASS HCONST HDATA ECODE MEMORY TYPE const program code ALLOWS ADDRESSING Complete CODE space C:0-C:0xFFFFFF constant variables Complete XDATA space X:0-C:0xFFFFFF variables Complete CODE space program code
following example shows "far" "const far" memory types: char farray[0x300]; //this variable HDATA space const char ctext[] "This string ECODE space"; "far" memory type support checkbox (shown Figure should checked intend const memory types.
Function Pointers
Since contiguous addressing mode supports 16MB program space, longer possible code function pointers. need generic pointer when define function pointer.
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Example DS80C390 Memory Configuration
demonstrate utility startup file constants we've introduced those which were already present Keil's START390.A51 file, propose example memory configuration DS80C390 microcontroller. Suppose that wish allow external code space connecting 512k memory device each chip-enable signals also want have 1.5MB external data memory achieve this connecting three 512k memories, each peripheral chip-enable signals PCE0 PCE1 PCE2 Shown below diagram interconnect program/data memory determined thus far.
Figure EXAMPLE DS80C390 PROGRAM/DATA MEMORY INTERFACE
P1.6/A6 P1.5/A5 P1.4/A4 P1.3/A3 P1.2/A2 P1.1/A1 P1.0/A0 AD0/D0 AD1/D1 AD2/D2 AD3/D3 AD4/D4 AD5/D5 AD6/D6
512k FLASH PROGRAM MEMORY D0-D7 A0-A7 A8-A15 A16-A18
512k FLASH PROGRAM MEMORY D0-D7 A0-A7 A8-A15 A16-A18
P1.7/A7 RSTOL P3.0/RXD0 P3.1/TXD0 P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1/CLKO P3.6/WR\ P3.7/RD\ P5.7/PCE3 P5.6/PCE2 P5.5/PCE1
DS80C390
AD7/D7 PSEN\ P2.7\A15 P2.6\A14 P2.5\A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8 P4.0/CE0 P4.1/CE1
512k DATA MEMORY D0-D7 A0-A7 A8-A15 A16-A18
512k DATA MEMORY D0-D7 A0-A7 A8-A15 A16-A18
512k DATA MEMORY D0-D7 A0-A7 A8-A15 A16-A18
P5.4/PCE0 P5.3/C1TX P5.2/C1RX P5.1/C0RX P5.0/C0TX XTAL2 XTAL1 MUX\ P4.7/A19 P4.6/A18 P4.5/A17 P4.4/A16 P4.3/CE3 P4.2/CE2
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Figure EXTERNAL PROGRAM/DATA MEMORY (INTERNAL SRAM STILL DEFAULT ADDRESSES)
PROGRAM MEMORY DATA MEMORY 17FFFFh
PCE2
=512k 100000h 0FFFFFh
0FFFFFh
=512k
PCE1
=512k 00FFFFh 080000h 07FFFFh INTERNAL SRAM (1kB stack) INTERNAL 512-byte SRAM (CAN0, CAN1) 000000h
080000h 07FFFFh
PCE0
=512k
00F000h 00EFFFh
=512k
000000h
00EE00h
case DS80C390, must also consider on-chip memory that present how/where this memory should into memory map. DS80C390 contains following internal memory: 256-byte RAMs that used data, message center memory CAN2.0B controllers that used data, stack, program that used data, program
logical address ranges these internal RAMs controlled settings configured within startup file, resulting startup file further tailored toward DS80C390-based projects. Once again, START390.A51 file provided Keil already includes constants code assign location function this internal SRAM. this example, will 256-byte RAMs support activity, will dedicated stack memory, will exclusively MOVX data space. also decide define logical addresses internal range (400000h-4011FFh) such that does interfere overlap external data memory (000000h-0FFFFFh). Shown below memory that been updated reflect assignments DS80C390 internal memory.
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Figure COMBINED INTERNAL, EXTERNAL PROGRAM/DATA MEMORY
PROGRAM MEMORY DATA MEMORY
INTERNAL 512-byte SRAM (CAN0, CAN1) INTE RNAL SRAM (1kB stack)
4011FFh
401000h 400FFFh
400000h
17FFFFh
PCE2
=512k 100000h 0FFFFFh
0FFFFFh
=512k
PCE1
=512k 080000h 07FFFFh
080000h 07FFFFh
=512k
PCE0
=512k 000000h
000000h
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Assigning Values Startup File Constants
Once we've decided desired memory configuration, assign appropriate values startup file constants. Shown below assignments constants from original START390.A51 file those which we've added, allowing effect example DS80C390 memory earlier specified.
P4CNT5_3 P4CNT2_0 P5CNT2_0 110B 101B 110B stack on-chip XDATA space on-chip SRAM location X:0x400000 X:400FFF CAN0 X:0x401000 X:0x4010FF CAN1 X:0x401100 X:0x4011FF 110B 512kB (A18-A0 enabled) 101B enable CE0, 110B enable PCE0, PCE1, PCE2
Testing Correct Memory Access Startup File Definition
means evaluate startup file settings, create very simple program (shown below) that uses FVAR FCVAR macros access XDATA ECODE memory. This code easily modified serve template generating accesses specific memory locations order confirm proper hardware initialization address/chip-enable generation.
#include <REG390.H> #include <absacc.h> void main (void) while FCVAR (unsigned char, 0x07ffff); last address under FCVAR (unsigned char, 0x080000); first address under FVAR (unsigned char, 0x07ffff); last address under PCE0 FVAR (unsigned char, 0x080000); first address under PCE1 FVAR (unsigned char, 0x0fffff); last address under PCE1 FVAR (unsigned char, 0x100000); first address under PCE2 //-// FVAR macro generates call (return addr pushed onto hardware stack), following read puts LSByte return address into //-ACC FVAR(unsigned char, 0x400000); first addr internal XRAM (stack)
Results
Using above program, following signal sequence oscillocope images (Figures corresponding desired program/data memory interface. CHIP-ENABLE ACCESS
accesses with PSEN\ access with PSEN\ PCE0 access with PCE1 access with PCE1 access with PCE2 access with
ACTIVITY
Program fetches from 512kB MOVC read 07FFFFH MOVC read 080000H MOVX access 07FFFFH MOVX access 080000H MOVX access 0FFFFFH MOVX access 100000H MOVX operation 400000H accesses internal XRAM verified viewing contents inside simulator
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Figure PROGRAM MEMORY ACCESSES USING
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Figure DATA MEMORY ACCESSES USING
PCE0 PCE1 PCE2
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