74HC/HCT4015 Dual 4-bit serial-in/parallel-out shift register Pro

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74HC/HCT4015 Dual 4-bit serial-in/parallel-out shift register Pro

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IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications IC06 74HC/HCT/HCU/HCMOS Logic Package Information IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4015 Dual 4-bit serial-in/parallel-out shift register
Product specification File under Integrated Circuits, IC06 December 1990
Philips Semiconductors
Product specification
Dual 4-bit serial-in/parallel-out shift register
FEATURES Output capability: standard category: GENERAL DESCRIPTION 74HC/HCT4015 high-speed Si-gate CMOS devices compatible with "4015" "4000B" series. They specified compliance with JEDEC standard
74HC/HCT4015
74HC/HCT4015 dual edge-triggered 4-bit static shift registers (serial-to-parallel converters). Each shift register serial data input 2D), clock input (1CP 2CP), four fully buffered parallel outputs (1Q0 2Q3) overriding asynchronous master reset (1MR 2MR). Information present shifted first register position, data register shifted position right LOW-to-HIGH transition nCP. HIGH clears register forces LOW, independent
QUICK REFERENCE DATA Tamb TYPICAL SYMBOL tPHL/ tPLH fmax Notes used determine dynamic power dissipation µW): VCC2 VCC2 where: input frequency output frequency VCC2 outputs output load capacitance supply voltage condition condition ORDERING INFORMATION "74HC/HCT/HCU/HCMOS Logic Package Information". PARAMETER propagation delay maximum clock frequency input capacitance power dissipation capacitance register notes CONDITIONS UNIT
December 1990
Philips Semiconductors
Product specification
Dual 4-bit serial-in/parallel-out shift register
DESCRIPTION SYMBOL 1MR, 1CP, NAME FUNCTION flip-flop outputs asynchronous master reset inputs (active HIGH) serial data inputs ground clock inputs (LOW-to-HIGH, edge-triggered) flip-flop outputs positive supply voltage
74HC/HCT4015
Fig.1 configuration.
Fig.2 Logic symbol.
Fig.3 logic symbol.
December 1990
Philips Semiconductors
Product specification
Dual 4-bit serial-in/parallel-out shift register
74HC/HCT4015
Fig.5 Fig.4 Functional diagram.
Logic diagram (one 4-bit serial-in/parallel-out shift register).
FUNCTION TABLE INPUTS Notes HIGH voltage level voltage level don't care LOW-to-HIGH clock transition HIGH-to-LOW clock transition number clock pulse transitions either HIGH APPLICATIONS Serial-to-parallel converter Buffer stores General purpose register OUTPUTS
change
December 1990
Philips Semiconductors
Product specification
Dual 4-bit serial-in/parallel-out shift register
CHARACTERISTICS 74HC characteristics "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard category: CHARACTERISTICS 74HC Tamb (°C) 74HC SYMBOL PARAMETER min. tPHL/ tPLH propagation delay propagation delay output transition time typ. max. min. max. +125 min. max.
74HC/HCT4015
TEST CONDITIONS UNIT WAVEFORMS Fig.6
tPHL
Fig.7
tTHL/ tTLH
Fig.6
clock pulse width HIGH master reset pulse width HIGH removal time set-up time hold time maximum clock pulse frequency
Fig.6
Fig.7
trem
Fig.7
Fig.8
Fig.8
fmax
Fig.6
December 1990
Philips Semiconductors
Product specification
Dual 4-bit serial-in/parallel-out shift register
CHARACTERISTICS 74HCT characteristics "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard category: Note types
74HC/HCT4015
value additional quiescent supply current (ICC) unit load given family specifications. determine input, multiply this value unit load coefficient shown table below.
INPUT
UNIT LOAD COEFFICIENT 0.30 1.50 1.50
CHARACTERISTICS 74HCT Tamb (°C) 74HCT
SYMBOL
TEST CONDITIONS
PARAMETER
+125
UNIT
WAVEFORMS
min. typ. max. min. max. min. max. tPHL/ tPLH tPHL tTHL/ tTLH trem fmax propagation delay propagation delay output transition time clock pulse width HIGH master reset pulse width HIGH removal time set-up time hold time maximum clock pulse frequency Fig.6 Fig.7 Fig.6 Fig.6 Fig.7 Fig.7 Fig.8 Fig.8 Fig.6
December 1990
Philips Semiconductors
Product specification
Dual 4-bit serial-in/parallel-out shift register
WAVEFORMS
74HC/HCT4015
50%; VCC. HCT:
Fig.6
Waveforms showing clock (nCP) output (nQn) propagation delays, clock pulse width, output transition times maximum clock frequency.
50%; VCC. HCT:
Fig.7
Waveforms showing master reset (nMR) pulse width, master reset output (nQn) propagation delay master reset clock (nCP) removal time.
shaded areas indicate when input permitted change predictable output performance. 50%; VCC. HCT:
Fig.8 Waveforms showing data set-up hold times inputs.
December 1990
Philips Semiconductors
Product specification
Dual 4-bit serial-in/parallel-out shift register
PACKAGE OUTLINES "74HC/HCT/HCU/HCMOS Logic Package Outlines".
74HC/HCT4015
December 1990

74HC/HCT4015 Dual 4-bit serial-in/parallel-out shift register Pro

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