PC/100 SDRAM Specification Supporting based 4Mx16 SDRAM, LVTTL, 2/4-Ba
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4Mx64 SDRAM Unbuffered DIMM R-Series
PC/100 SDRAM Specification Supporting based 4Mx16 SDRAM, LVTTL, 2/4-Banks 4K/8KRefresh HYM7V65400A/ HYM7V65401A/ HYM7V65430A/ HYM7V65431A
HYM7V65400A/ 65401A/ 65430A/ 65431A R-Series high speed 3.3-Volt synchronous dynamic Modules composed four 4Mx16 Synchronous DRAMs 54-pin TSOPII 8-pin TSSOP E2PROM 168-pin glass-epoxy printed circuit board. 0.33µF 0.1µF decoupling capacitors each SDRAM mounted module. HYM7V65400A/ 65401A/ 65430A/ 65431A R-Series gold plated socket type Dual In-line Memory Modules suitable easy interchange addition bytes memory. addresses, data control inputs latched rising edge master clock input. data paths internally pipelined achieve very high bandwidths.
FEATURES
1.375" (34.93mm) Height 168-Pin Unbuffered DIMM with Single Sided 0.33µF 0.1µF decoupling capacitors adopted Serial Presence Detect with Serial E2PROM Meets other JEDEC specifications Single 3.3V±0.3V power supply device pins LVTTL compatible 4096 refresh cycles every 64ms 8192 refresh cycles every 128ms Fully synchronous inputs referenced positive edge system clock Dual Quad internal banks with single pulsed /RAS Auto precharge/precharge banks flag Possible assert random column address every clock cycle Interleaved auto refresh mode Programmable burst lengths sequences 1,2,4,8,full page Sequential type 1,2,4,8 Interleave type Programmable /CAS latency clocks Support clock suspend/power down mode CKE0 Data mask function Mode register programming Burst termination command Self refresh provides minimum power, full internal refresh control
ORDERING INFORMATION
Part HYM7V65400ATRG 8/10P/10S HYM7V65401ATRG 8/10P/10S HYM7V65430ATRG 8/10P/10S HYM7V65431ATRG 8/10P/10S Max. Frequency 125/ 100/ 125/ 100/ 125/ 100/ 125/ 100/ SDRAM Bank Banks Banks Banks Banks Ref. Package TSOPII TSOPII TSOPII TSOPII Plating Gold Gold Gold Gold
BASED COMPONENTS
Module Part HYM7V65400ATRG HYM7V65401ATRG Based Comp. Part HY57V651610ATC HY57V651620ATC Module Part HYM7V65430ATRG HYM7V65431ATRG Based Comp. Part HY57V641610ATC HY57V641620ATC
This document general product description subject change without notice. Hyundai Electronics does assume responsibility circuits described. patent licenses implied. Apr. 1998
HYM7V65400A/ HYM7V65401A/ HYM7V65430A/ HYM7V65431A R-Series
Name CK0-CK3 Type INPUT Description System Clock Input; other inputs except registered SDRAM rising edge CLK. Clock Enable; Controls internal clock signal when deactivated, SDRAM will either states among power down, suspend, self refresh. Chip select; Functions command mask(NOP). address strobe Column address strobe Write Enable Data Input Output Mask Data Input Output; Include inputs, outputs, Hi-z state. Power Supplies; 3.3V±0.3V Ground Serial Address Data Input Output. Serial Clock Addresses Serial E2PROM Socket Presence.
CKE0 /S0, /RAS /CAS DQM0-7 DQ0-DQ63 SA0-SA2
INPUT INPUT INPUT INPUT INPUT INPUT INPUT/ OUTPUT SUPPLY SUPPLY INPUT/ OUTPUT INPUT INPUT
HYM7V65400A/HYM7V65430A R-Series 2Bank 4Mx16 SDRAM Based Name Type INPUT Description Bank select address inputs; Select dual banks during both /RAS /CAS activity. Address Inputs; A0-A7; addresses A10; Precharge flag, A8-A12; addresses only.
A0-A12
INPUT
HYM7V65401A/HYM7V65431A R-Series 4Bank 4Mx16 SDRAM Based Name BA0, Type INPUT Description Bank address inputs; Select quad banks during both /RAS /CAS activity. Address Inputs; A0-A7; addresses A10; Precharge flag, A8-A11; addresses only.
A0-A11
INPUT
HYM7V65400A/ HYM7V65401A/ HYM7V65430A/ HYM7V65431A R-Series
NAME
NAME DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQM0 DQM1 A10(AP) NAME DQM2 DQM3 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 NAME DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 /CAS DQM4 DQM5 /RAS *CK1 NAME CKE0 DQM6 DQM7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 *CK3
Note used HYM7V65401A/HYM7V65431A R-Series Bank 4Mx16 Based used HYM7V65400A/HYM7V65430A R-Series Bank 4Mx16 Based connected with termination Refer block diagram
HYM7V65400A/ HYM7V65401A/ HYM7V65430A/ HYM7V65431A R-Series
BLOCK DIAGRAM
Note serial resistor values Ohms. padding capacitance termination CK1/3 10pF.
HYM7V65400A/ HYM7V65401A/ HYM7V65430A/ HYM7V65431A R-Series
SERIAL PRESENCE DETECT
BYTE NUMBER FUNCTION DESCRIBED
HYM7V65400A/HYM7V65430A R-Series; Banks
FUNCTION -10P -10S VALUE -10P -10S NOTE
BYTE0 BYTE1 BYTE2 BYTE3 BYTE4 BYTE5 BYTE6 BYTE7 BYTE8 BYTE9 BYTE10 BYTE11 BYTE12 BYTE13 BYTE14 BYTE15 BYTE16 BYTE17 BYTE18 BYTE19 BYTE20 BYTE21
Bytes Written into Serial Memory Module Manufacturer Total Bytes Memory Device Fundamental Memory Type Addresses This Assembly Column Addresses This Assembly Module Banks This Assembly Data Width This Assembly Data Width This Assembly (Continued) Voltage Interface Standard This Assembly SDRAM Cycle Time /CAS Latency=3 Access Time from Clock /CAS Latency=3 DIMM Configuration Type Refresh Rate/Type Primary SDRAM Width Error Checking SDRAM Width Minimum Clock Delay Back Back Random Column Address Burst Lengths Supported Banks SDRAM Device Latency Latency Write Latency SDRAM Module Attributes
Bytes Bytes SDRAM Banks; Bank Bits LVTTL 10ns None 15.625µs
Self Refresh Supported
10ns
None tCCD=1 Latency 1,2,4,8,Full Page Banks /CAS Latency=2,3 Latency=0 Latency=0 Neither Buffered Registered +/-10% voltage tolerance, Burst read, Precharge all, Auto precharge 10ns 10ns 12ns 20ns 20ns 20ns 16ns 20ns 20ns 20ns 20ns 20ns 48ns 50ns 50ns 32MB
BYTE22 BYTE23 BYTE24 BYTE25 BYTE26 BYTE27 BYTE28 BYTE29 BYTE30 BYTE31 BYTE32 BYTE33 BYTE34 BYTE35
SDRAM Module Attributes, General SDRAM Cycle Time /CAS Latency=2 Access Time from Clock /CAS Latency=2 SDRAM Cycle Time /CAS Latency=1 Access Time from Clock /CAS Latency=1 Minimum Precharge Time (tRP) Minimum Active Active Delay (tRRD) Minimum /RAS /CAS Delay (tRCD) Minimum /RAS Pulse width (tRAS) Module Bank Density Command Address signal input setup time (tAS) Command Address signal input hold time (tAH) Data signal input setup time (tDS) Data signal input hold time (tDH)
HYM7V65400A/ HYM7V65401A/ HYM7V65430A/ HYM7V65431A R-Series
SERIAL PRESENCE DETECT
BYTE NUMBER FUNCTION DESCRIBED
HYM7V65400A/HYM7V65430A R-Series; Banks: Continued
FUNCTION -10P -10S VALUE -10P -10S NOTE
BYTE36 BYTE62 BYTE63 BYTE64 BYTE65 BYTE72 BYTE73 BYTE74 BYTE75 BYTE76 BYTE77 BYTE78
Superset Information(May used future) Revision Checksum Byte 0-62 Manufacturer JEDEC Code .Manufacturer JEDEC Code Manufacturing Location Manufacturer' Part Number (SDRAM) Manufacturer' Part Number (3.3V) Manufacturer' Part Number (Data Width) .Manufacturer' Part Number (Data Width) Manufacturer' Part Number (Memory Depth) Manufacturer' Part Number (Refresh)
Intel 1.2A Hyundai JEDEC Unused (Korea) (United States) (Europe) Ref.) Ref.) Blank Blank
BYTE79 Manufacturer' Part Number Internal Banks) BYTE80 Manufacturer' Part Number (Generation) BYTE81 Manufacturer' Part Number (TSOPII Mounted) BYTE82 Manufacturer' Part Number Unbuffered) BYTE83 Manufacturer' Part Number (Plating Type Gold) BYTE84 Manufacturer' Part Number (Hyphen) BYTE85 Manufacturer' Part Number (Min. Cycle Time) BYTE86 .Manufacturer' Part Number (Min. Cycle Time) BYTE87 .Manufacturer' Part Number (Min. Cycle Time) BYTE88 Manufacturer' Part Number Blanks BYTE91 Revision Code Components Process Code BYTE92 .Revision Code Process Code BYTE93 Manufacturing Date Work Week BYTE94 .Manufacturing Date Year BYTE95 Assembly Serial Number BYTE99 Manufacturer Specific Data (May used None -125 Future) BYTE126 System Frequency support 100MHz BYTE127 Intel Specification details 100MHz Support Note BYTE128 Unused storage locations -256 Note: bank address excluded. interleaved type, burst lengths supported fixed dependent. Refer Intel 1.2A specifications. adopted. ASCII adopted. CLK0,2 connected DIMM, junction temp, CL=2(3) support supporting Intel defined Concurrent Auto Precharge.
HYM7V65400A/ HYM7V65401A/ HYM7V65430A/ HYM7V65431A R-Series
II-1 SERIAL PRESENCE DETECT
BYTE NUMBER FUNCTION DESCRIBED
HYM7V65401A/HYM7V65431A R-Series; Banks
FUNCTION -10P -10S VALUE -10P -10S NOTE
BYTE0 BYTE1 BYTE2 BYTE3 BYTE4 BYTE5 BYTE6 BYTE7 BYTE8 BYTE9 BYTE10 BYTE11 BYTE12 BYTE13 BYTE14 BYTE15 BYTE16 BYTE17 BYTE18 BYTE19 BYTE20 BYTE21
Bytes Written into Serial Memory Module Manufacturer Total Bytes Memory Device Fundamental Memory Type Addresses This Assembly Column Addresses This Assembly Module Banks This Assembly Data Width This Assembly Data Width This Assembly (Continued) Voltage Interface Standard This Assembly SDRAM Cycle Time /CAS Latency=3 Access Time from Clock /CAS Latency=3 DIMM Configuration Type Refresh Rate/Type Primary SDRAM Width Error Checking SDRAM Width Minimum Clock Delay Back Back Random Column Address Burst Lengths Supported Banks SDRAM Device Latency Latency Write Latency SDRAM Module Attributes
Bytes Bytes SDRAM Banks; Bank Bits LVTTL 10ns None 15.625µs
Self Refresh Supported
10ns
None tCCD=1 Latency 1,2,4,8,Full Page Banks /CAS Latency=2,3 Latency=0 Latency=0 Neither Buffered Registered +/-10% voltage tolerance, Burst read, Precharge all, Auto precharge 10ns 10ns 12ns 20ns 20ns 20ns 16ns 20ns 20ns 20ns 20ns 20ns 48ns 50ns 50ns 32MB
BYTE22 BYTE23 BYTE24 BYTE25 BYTE26 BYTE27 BYTE28 BYTE29 BYTE30 BYTE31 BYTE32 BYTE33 BYTE34 BYTE35
SDRAM Module Attributes, General SDRAM Cycle Time /CAS Latency=2 Access Time from Clock /CAS Latency=2 SDRAM Cycle Time /CAS Latency=1 Access Time from Clock /CAS Latency=1 Minimum Precharge Time (tRP) Minimum Active Active Delay (tRRD) Minimum /RAS /CAS Delay (tRCD) Minimum /RAS Pulse width (tRAS) Module Bank Density Command Address signal input setup time (tAS) Command Address signal input hold time (tAH) Data signal input setup time (tDS) Data signal input hold time (tDH)
HYM7V65400A/ HYM7V65401A/ HYM7V65430A/ HYM7V65431A R-Series
II-2 SERIAL PRESENCE DETECT
BYTE NUMBER FUNCTION DESCRIBED
HYM7V65401A/HYM7V65431A R-Series; Banks: Continued
FUNCTION -10P -10S VALUE -10P -10S NOTE
BYTE36 BYTE62 BYTE63 BYTE64 BYTE65 BYTE72 BYTE73 BYTE74 BYTE75 BYTE76 BYTE77 BYTE78
Superset Information(May used future) Revision Checksum Byte 0-62 Manufacturer JEDEC Code .Manufacturer JEDEC Code Manufacturing Location Manufacturer' Part Number (SDRAM) Manufacturer' Part Number (3.3V) Manufacturer' Part Number (Data Width) .Manufacturer' Part Number (Data Width) Manufacturer' Part Number (Memory Depth) Manufacturer' Part Number (Refresh)
Intel 1.2A Hyundai JEDEC Unused (Korea) (United States) (Europe) Ref.) Ref.) Blank Blank
BYTE79 Manufacturer' Part Number Internal Banks) BYTE80 Manufacturer' Part Number (Generation) BYTE81 Manufacturer' Part Number (TSOPII Mounted) BYTE82 Manufacturer' Part Number Unbuffered) BYTE83 Manufacturer' Part Number (Plating Type Gold) BYTE84 Manufacturer' Part Number (Hyphen) BYTE85 Manufacturer' Part Number (Min. Cycle Time) BYTE86 .Manufacturer' Part Number (Min. Cycle Time) BYTE87 .Manufacturer' Part Number (Min. Cycle Time) BYTE88 Manufacturer' Part Number Blanks BYTE91 Revision Code Components Process Code BYTE92 .Revision Code Process Code BYTE93 Manufacturing Date Work Week BYTE94 .Manufacturing Date Year BYTE95 Assembly Serial Number BYTE99 Manufacturer Specific Data (May used None -125 Future) BYTE126 System Frequency support 100MHz BYTE127 Intel Specification details 100MHz Support Note BYTE128 Unused storage locations -256 Note: bank address excluded. interleaved type, burst lengths supported fixed dependent. Refer Intel 1.2A specifications. adopted. ASCII adopted. CLK0,2 connected DIMM, junction temp, CL=2(3) support supporting Intel defined Concurrent Auto Precharge.
HYM7V65400A/ HYM7V65401A/ HYM7V65430A/ HYM7V65431A R-Series
ABSOLUTE MAXIMUM RATINGS
Symbol TSTG VIN, VOUT Parameter Ambient Temperature Storage Temperature Voltage relative Voltage relative Short Circuit Output Current Power Dissipation Rating -1.0 -1.0 Unit °Csec
TSOLDER Soldering TemperatureTime 26010 Note Operation above Absolute Maximum Ratings adversely affect device reliability.
RECOMMENDED OPERATING CONDITIONS*
Symbol VCC, VCCQ Parameter Power Supply Voltage Power Supply Voltage Input High Voltage Min. Typ. Max.
(TA=0°C 70°C) Unit Note
Input Voltage -0.3 Note VIH(max)=4.6V pulse width 10ns acceptable. VIL(min)=-1.5V pulse width 10ns acceptable.
RECOMMENDED OPERATING CONDITIONS* (TA=0°C 70°C, VCC=3.3V±10%, VSS=0V)
Symbol Vtrip Voutref Parameter Input High/Low Level Voltage Input Timing Measurement Reference Level Voltage Input Rise/Fall Time Output Reference Voltage Value 2.4/0.4 Unit Note
Output Load Capacitance Access Time Measurement Note Output load measure access times equivalent gates capacitance(50pF).
Note
Output
Output Load Circuit
Rt=250 50pF Vtt=1.4V
Output Load Circuit
Output 50pF
HYM7V65400A/ HYM7V65401A/ HYM7V65430A/ HYM7V65431A R-Series
CHARACTERISTICS(I)
Symbol Parameter Input Leakage Current Output Leakage Current Output Voltage Output High Voltage Test Condition VI=0 3.6V, other pins undertest=0V DOUT disabled, VO=0 3.6V IOL=4.0mA IOH=-4.0mA
(TA=0°C 70°C, VCC=3.3V±10%, VSS=0V) Min. Max. Unit
CHARACTERISTICS(II)
Parameter Operating current Precharge Standby Current Power Down Mode Symbol ICC1 ICC2P ICC2PS ICC2N
(TA=0°C 70°C, VCC=3.3V±10%, VSS=0V) Test Condition Burst Length=1, bank active tRAStRAS(min), tRPtRP(min), IO=0mA CKEVIL(max), tCK=15ns CKEVIL(max), tCK= -10P -10S Max. Unit Note
CKEVIL(min), VIL(min), tCK=15ns Precharge Standby Current Power Down Mode ICC2NS Active Standby Current Power Down Mode ICC3P ICC3PS ICC3N Input signals chaged time during 30ns. other pinsVDD-0.2V 0.2V CKEVIL(min), tCK= Input signals stable CKEVIL(max), tCK=15ns CKEVIL(max), tCK= CKEVIL(min), VIL(min), tCK=15ns Active Standby Current Power Down Mode Input signals chaged time during 30ns. other pinsVDD-0.2V 0.2V CKEVIL(min), tCK= Input signals stable CL=3 -10P -10S CL=2 -10P -10S Auto Refresh Current ICC5 tRRCtRRC(min), banks active
ICC3NS
Burst Mode Operating Current
tCK(min), ICC4 tRAStRAS(min), IO=0mA banks active
Self Refresh Current ICC6 CKE0.2V Note ICC1 ICC4 depend output loading cycle rates. Specified values measured with output open. Minimum tRRC(Refresh /RAS cycle time)=96ns
HYM7V65400A/ HYM7V65401A/ HYM7V65430A/ HYM7V65431A R-Series
CHARACTERISTICS
-10P -10S Unit Note CL=3 tCK3 System clock cycle time 1000 1000 1000 CL=2 tCK2 Clock high pulse width tCHW Clock pulse width tCLW CL=3 tAC3 Access time from clock CL=2 tAC2 Data-Out hold time Data-Input setup time Data-Input hold time Address setup time Address hold time setup time tCKS hold time tCKH Command setup time Command hold time data output Z-time tOLZ CL=3 tOHZ3 data output high Z-time CL=2 tOHZ2 Note Assumed input rise fall time 1ns. longer than 1ns, transient time compensation should considered. i.e., [(tR+tF)/2-1]ns should added parameter. clock rising time longer than 1ns, (tR/2-0.5)ns should added parameter. Parameter Symbol
CHARACTERISTICS
-10P Operation /RAS cycle time Auto Refresh tRRC /RAS /CAS delay tRCD /RAS active time tRAS 100K 100K /RAS precharge time /RAS /RAS bank active delay tRRD /CAS /CAS delay tCCD Write command data-in delay tWTL Data-in precharge command tDPL Data-in active command tDAL data-out Hi-Z tDQZ data-in mask tDQM command tMRD Precharge data CL=3 tPROZ3 output Hi-Z CL=2 tPROZ2 Power down exit time tPDE Self refresh exit time tSRE Refresh time tREF Note command given tRRC after self refresh exit. Parameter Symbol
-10S 100K
Unit
Note
HYM7V65400A/ HYM7V65401A/ HYM7V65430A/ HYM7V65431A R-Series
CAPACITANCE
Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 COUT Parameter Input Capacitance Input Capacitance Input Capacitance Input Capacitance Input Capacitance Input Capacitance Output Capacitance A0-A11/12, BA0/BA1 /RAS, /CAS, /S0, CK0, CKE0 DQM0-DQM7 DQ0-DQ63
(TA=25°C, f=1MHz) Typ. Max. Unit
MODULE OPERATING OPTION TABLE
HYM7V65400/401/430/431ATFG-8 /CAS Latency 125MHz 100MHz 83MHz 66MHz 3CLKs 2CLKs 2CLKs 2CLKs tRCD 3CLKs 2CLKs 2CLKs 2CLKs tRAS 6CLKs 5CLKs 4CLKs 4CLKs 9CLKs 7CLKs 6CLKs 5CLKs 3CLKs 2CLKs 2CLKs 2CLKs
HYM7V65400/401/430/431ATFG-10P /CAS Latency 100MHz 83MHz 66MHz 50MHz 2CLKs 2CLKs 2CLKs 2CLKs tRCD 2CLKs 2CLKs 2CLKs 1CLKs tRAS 5CLKs 5CLKs 4CLKs 3CLKs 7CLKs 6CLKs 5CLKs 4CLKs 2CLKs 2CLKs 2CLKs 1CLKs
HYM7V65400/401/430/431ATFG-10S /CAS Latency 100MHz 83MHz 66MHz 50MHz 3CLKs 2CLKs 2CLKs 2CLKs tRCD 2CLKs 2CLKs 2CLKs 1CLKs tRAS 5CLKs 5CLKs 4CLKs 3CLKs 7CLKs 6CLKs 5CLKs 4CLKs 2CLKs 2CLKs 2CLKs 1CLKs
HYM7V65400A/ HYM7V65401A/ HYM7V65430A/ HYM7V65431A R-Series
COMMAND TRUTH TABLE
Command Mode Register Operation Bank Active Read Read with Autoprecharge Write Write with Autoprecharge Precharge baknks Precharge selected bank Burst Stop Auto Refresh Entry Self Refresh Exit Precharge Entry Power down Exit Clock Suspend Entry Exit CKEn-1 CKEn /RAS /CAS ADDR A10/ Note
code
(V=Valid, X=Don' care, H=Logic High, L=Logic Low)
Note: code Operand Code. ADDR, A10/AP, Program keys (@MRS) 2.MRS issued only both banks precharge state. command issued after 2CLK cycles MRS. Auto refresh functions same refresh DRAM automatical precharge without precharge command meant Auto" Auto/self refresh issued only both banks precharge state. Bank select address. "Low" read, write, active precharge, Bank selected. "High" read, write, active precharge, Bank selected. A10/AP "High" precharge, ignored both banks selected. During burst read write with auto precharge, read/write command issued. Another bank read/write command issued after burst. active associated bank issued after burst. Burst stop command valid every burst length. sampled positive going edge masks data-in very (write Latency makes Hi-Z state data-out 2CLK cycles after. (Read latency
HYM7V65400A/ HYM7V65401A/ HYM7V65430A/ HYM7V65431A R-Series
PACKAGE DIMENSION
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