based 4Mx16 SDRAM, LVTTL, 2/4-Banks 4K/8K-Refresh HYM7V64400/ HYM7V644
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4Mx64 SDRAM DIMM Q-Series
based 4Mx16 SDRAM, LVTTL, 2/4-Banks 4K/8K-Refresh HYM7V64400/ HYM7V64401/ HYM7V64430/ HYM7V64431
HYM7V64400/ 64401/ 64430/ 64431 Q-Series high speed 3.3-Volt synchronous dynamic Modules composed four 4Mx16 Synchronous DRAMs 54-pin TSOPII 8-pin TSSOP E2PROM 144-pin Dual glass-epoxy printed circuit board. 0.22µF 0.0022µF decoupling capacitors each SDRAM mounted module. HYM7V64400/ 64401/ 64430/ 64431 Q-Series gold plated socket type Dual In-line Memory Modules suitable easy interchange addition bytes memory. addresses, data control inputs latched rising edge master clock input. data paths internally pipelined achieve very high bandwidths.
FEATURES
144-Pin Unbuffered DIMM Serial Presence Detect with Serial E2PROM Meets other JEDEC specifications Single 3.3V±0.3V power supply device pins LVTTL compatible 4096 refresh cycles every 64ms 8192 refresh cycles every 128ms Fully synchronous inputs referenced positive edge system clock Dual Quad internal banks with single pulsed /RAS Auto precharge/precharge banks flag Possible assert random column address every clock cycle Interleaved auto refresh mode Programmable burst lengths sequences 1,2,4,8,full page Sequential type 1,2,4,8 Interleave type Programmable /CAS latency 1,2,3 clocks Support clock suspend/power down mode CKE0 Data mask function Mode register programming Burst termination command Self refresh provides minimum power, full internal refresh control
ORDERING INFORMATION
Part HYM7V64400TQG 10/12/15 HYM7V64401TQG 10/12/15 HYM7V64430TQG 10/12/15 HYM7V64431TQG 10/12/15 Max. Frequency 100/ 100/ 100/ 100/ SDRAM Bank Banks Banks Banks Banks Refresh Package TSOP TSOP TSOP TSOP Plating Gold Gold Gold Gold
This document general product description subject change without notice. Hyundai Electronics does assume responsibility circuits described. patent licenses implied. Apr. 1998
HYM7V64400/ HYM7V64401/ HYM7V64430/ HYM7V64431 Q-Series
Name CK0, Type INPUT Description System Clock Input; other inputs except registered SDRAM rising edge CLK. Clock Enable; Controls internal clock signal when deactivated, SDRAM will either states among power down, suspend, self refresh. Chip select; Functions command mask(NOP). address strobe; functional truth table 4Mx16 Data Sheets details. Column address strobe; functional truth table 4Mx16 Data Sheets details. Write Enable; functional truth table 4Mx16 Data Sheets details. Data Input Output Mask Data Input Output; Include inputs, outputs, Hi-z state. Power Supplies; 3.3V±0.3V Ground Serial Address Data Input Output. Serial Clock
CKE0 /RAS /CAS DQM0-7 DQ0-DQ63
INPUT INPUT INPUT INPUT INPUT INPUT INPUT/ OUTPUT SUPPLY SUPPLY INPUT/ OUTPUT INPUT
HYM7V64400/HYM7V64430 Q-Series 2Bank 4Mx16 SDRAM Based Name Type INPUT Description Bank select address inputs; Select dual banks during both /RAS /CAS activity. Address Inputs; A0-A7; addresses, A0-A13; Opcode mode register set, A10; Precharge flag, A8-A12; addresses only.
A0-A12
INPUT
HYM7V64401/HYM7V64431 Q-Series 4Bank 4Mx16 SDRAM Based Name BA0, Type INPUT Description Bank address inputs; Select quad banks during both /RAS /CAS activity. Address Inputs; A0-A7; addresses, A0-A13; Opcode mode register set, A10; Precharge flag, A8-A11; addresses only.
A0-A11
INPUT
HYM7V64400/ HYM7V64401/ HYM7V64430/ HYM7V64431 Q-Series
NAME
NAME DQM0 DQM1 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 /RAS NAME DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQM4 DQM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 CKE0 /CAS *A12 NAME DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 A10(AP) DQM2 DQM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 NAME *CK1 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 *BA1 DQM6 DQM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
Note used HYM7V64401/HYM7V64431 Q-Series Bank 4Mx16 Based used HYM7V64400/HYM7V64430 Q-Series Bank 4Mx16 Based connected with termination Refer block diagram
HYM7V64400/ HYM7V64401/ HYM7V64430/ HYM7V64431 Q-Series
BLOCK DIAGRAM
Note padding capacitance termination 10pF.
HYM7V64400/ HYM7V64401/ HYM7V64430/ HYM7V64431 Q-Series
SERIAL PRESENCE DETECT
BYTE NUMBER FUNCTION DESCRIBED
HYM7V64400/HYM7V64430 Q-Series; Banks FUNCTION VALUE NOTE
BYTE0 BYTE1 BYTE2 BYTE3 BYTE4 BYTE5 BYTE6 BYTE7 BYTE8 BYTE9
Bytes Written into Serial Memory Module Manufacturer Total Bytes Memory Device Fundamental Memory Type Addresses This Assembly Column Addresses This Assembly Module Banks This Assembly Data Width This Assembly Data Width This Assembly(Continued) Voltage Interface Standard This Assembly SDRAM Cycle Time
/CAS Latency=3
Bytes Bytes SDRAM Banks; Bank Bits LVTTL tCLK 10ns 12ns 15ns 10ns None 15.625µs
Self Refresh Supported
BYTE10
SDRAM Access Time from Clock
/CAS Latency=3, @Cycle Time=10ns /CAS Latency=3, @Cycle Time=12ns /CAS Latency=3, @Cycle Time=15ns
BYTE11 BYTE12 BYTE13 BYTE14 BYTE15 BYTE16 BYTE17 BYTE18 BYTE19 BYTE20 BYTE21 BYTE22 BYTE23
DIMM Configuration Type Refresh Rate/Type Primary SDRAM Width Error Checking SDRAM Width Minimum Clock Delay Back Back Random Column Address Burst Lengths Supported Banks SDRAM Device Bank 4Mx16 Based Latency Latency Write Latency SDRAM Module Attributes Neither Buffered Registered SDRAM Module Attributes General Burst read, Precharge All, Auto Precharge SDRAM Cycle Time
/CAS Latency=2
None tCCD=1 Latency 1,2,4,8,Full Page Banks /CAS Latency=1,2,3 Latency=0 Latency=0 tCLK 12ns 15ns 15ns
HYM7V64400/ HYM7V64401/ HYM7V64430/ HYM7V64431 Q-Series
SERIAL PRESENCE DETECT
BYTE NUMBER
HYM7V64400/HYM7V64430 Q-Series; Banks: Continued FUNCTION VALUE NOTE
FUNCTION DESCRIBED
BYTE24
SDRAM Access Time from Clock
/CAS Latency=2, @Cycle Time=12ns /CAS Latency=2, @Cycle Time=15ns /CAS Latency=2, @Cycle Time=15ns
BYTE25
SDRAM Cycle Time
/CAS Latency=1
BYTE26
SDRAM Access Time from Clock
/CAS Latency=1, @Cycle Time=30ns /CAS Latency=1, @Cycle Time=30ns /CAS Latency=1, @Cycle Time=30ns
BYTE27
Minimum Pre-charge Time
@/CAS Latency=3, @Cycle Time=10ns @/CAS Latency=3, @Cycle Time=12ns @/CAS Latency=3, @Cycle Time=15ns
BYTE28
Minimum Active Active Delay
@/CAS Latency=3, @Cycle Time=10ns @/CAS Latency=3, @Cycle Time=12ns @/CAS Latency=3, @Cycle Time=15ns
BYTE29
Minimum /RAS /CAS Delay
@/CAS Latency=3, @Cycle Time=10ns @/CAS Latency=3, @Cycle Time=12ns @/CAS Latency=3, @Cycle Time=15ns
BYTE30
Minimum /RAS Pulse width
@/CAS Latency=3, @Cycle Time=10ns @/CAS Latency=3, @Cycle Time=12ns @/CAS Latency=3, @Cycle Time=15ns
BYTE31 BYTE32-61 BYTE62 BYTE63
Module Bank Density Superset Information (May Used Future) Revision Checksum Byte 0-62
@/CAS Latency=3, @Cycle Time=10ns @/CAS Latency=3, @Cycle Time=12ns @/CAS Latency=3, @Cycle Time=15ns
10ns tCLK 30ns 30ns 30ns 24ns 24ns 24ns 30ns 36ns 45ns tRRD 30ns 24ns 30ns tRCD 30ns 36ns 45ns tRAS 50ns 48ns 45ns 32MB Decimal Decimal Decimal Undefined
Undefined
BYTE64-127 Manufacturer Information BYTE128-255 Unused Storage Locations Note bank address excluded. interleaved type. burst lengths supported 1,2,4,8. case (A): 10ns, (B): 12ns, (C): 15ns part. above data changed, JEDEC standard modified.
HYM7V64400/ HYM7V64401/ HYM7V64430/ HYM7V64431 Q-Series
II-1 SERIAL PRESENCE DETECT
BYTE NUMBER FUNCTION DESCRIBED
HYM7V64401/HYM7V64431 Q-Series; Banks FUNCTION VALUE NOTE
BYTE0 BYTE1 BYTE2 BYTE3 BYTE4 BYTE5 BYTE6 BYTE7 BYTE8 BYTE9
Bytes Written into Serial Memory Module Manufacturer Total Bytes Memory Device Fundamental Memory Type Addresses This Assembly Column Addresses This Assembly Module Banks This Assembly Data Width This Assembly Data Width This Assembly(Continued) Voltage Interface Standard This Assembly SDRAM Cycle Time
/CAS Latency=3
Bytes Bytes SDRAM Banks; Bank Bits LVTTL tCLK 10ns 12ns 15ns 10ns None 15.625µs
Self Refresh Supported
BYTE10
SDRAM Access Time from Clock
/CAS Latency=3, @Cycle Time=10ns /CAS Latency=3, @Cycle Time=12ns /CAS Latency=3, @Cycle Time=15ns
BYTE11 BYTE12 BYTE13 BYTE14 BYTE15 BYTE16 BYTE17 BYTE18 BYTE19 BYTE20 BYTE21 BYTE22 BYTE23
DIMM Configuration Type Refresh Rate/Type Primary SDRAM Width Error Checking SDRAM Width Minimum Clock Delay Back Back Random Column Address Burst Lengths Supported Banks SDRAM Device Bank 4Mx16 Based Latency Latency Write Latency SDRAM Module Attributes Neither Buffered Registered SDRAM Module Attributes General Burst read, Precharge All, Auto Precharge SDRAM Cycle Time
/CAS Latency=2
None tCCD=1 Latency 1,2,4,8,Full Page Banks /CAS Latency=1,2,3 Latency=0 Latency=0 tCLK 12ns 15ns 15ns
HYM7V64400/ HYM7V64401/ HYM7V64430/ HYM7V64431 Q-Series
II-2 SERIAL PRESENCE DETECT
BYTE NUMBER
HYM7V64401/HYM7V64431 Q-Series; Banks: Continued FUNCTION VALUE NOTE
FUNCTION DESCRIBED
BYTE24
SDRAM Access Time from Clock
/CAS Latency=2, @Cycle Time=12ns /CAS Latency=2, @Cycle Time=15ns /CAS Latency=2, @Cycle Time=15ns
BYTE25
SDRAM Cycle Time
/CAS Latency=1
BYTE26
SDRAM Access Time from Clock
/CAS Latency=1, @Cycle Time=30ns /CAS Latency=1, @Cycle Time=30ns /CAS Latency=1, @Cycle Time=30ns
BYTE27
Minimum Pre-charge Time
@/CAS Latency=3, @Cycle Time=10ns @/CAS Latency=3, @Cycle Time=12ns @/CAS Latency=3, @Cycle Time=15ns
BYTE28
Minimum Active Active Delay
@/CAS Latency=3, @Cycle Time=10ns @/CAS Latency=3, @Cycle Time=12ns @/CAS Latency=3, @Cycle Time=15ns
BYTE29
Minimum /RAS /CAS Delay
@/CAS Latency=3, @Cycle Time=10ns @/CAS Latency=3, @Cycle Time=12ns @/CAS Latency=3, @Cycle Time=15ns
BYTE30
Minimum /RAS Pulse width
@/CAS Latency=3, @Cycle Time=10ns @/CAS Latency=3, @Cycle Time=12ns @/CAS Latency=3, @Cycle Time=15ns
Module Bank Density Superset Information (May Used Future) BYTE62 Revision BYTE63 Checksum Byte 0-62 @/CAS Latency=3, @Cycle Time=10ns Decimal @/CAS Latency=3, @Cycle Time=12ns Decimal @/CAS Latency=3, @Cycle Time=15ns Decimal BYTE64-127 Manufacturer Information BYTE128-255 Unused Storage Locations Undefined Note bank address excluded. interleaved type. burst lengths supported 1,2,4,8. case (A): 10ns, (B): 12ns, (C): 15ns part. above data changed, JEDEC standard modified.
BYTE31 BYTE32-61
10ns tCLK 30ns 30ns 30ns 24ns 24ns 24ns 30ns 36ns 45ns tRRD 30ns 24ns 30ns tRCD 30ns 36ns 45ns tRAS 50ns 48ns 45ns 32MB
Undefined
HYM7V64400/ HYM7V64401/ HYM7V64430/ HYM7V64431 Q-Series
ABSOLUTE MAXIMUM RATINGS
Symbol TSTG VIN, VOUT Parameter Ambient Temperature Storage Temperature Voltage relative Voltage relative Short Circuit Output Current Power Dissipation Rating -1.0 -1.0 Unit °Csec
TSOLDER Soldering TemperatureTime 26010 Note Operation above Absolute Maximum Ratings adversely affect device reliability.
RECOMMENDED OPERATING CONDITIONS*
Symbol Parameter Power Supply Voltage Power Supply Voltage Input High Voltage Input Voltage Min. -0.3 Typ. Max.
(TA=0°C 70°C) Unit LVTTL LVTTL Note
RECOMMENDED OPERATING CONDITIONS* (TA=0°C 70°C, VCC=3.3V±10%, VSS=0V)
Symbol Vtrip Voutref Parameter Input High/Low Level Voltage Input Timing Measurement Reference Level Voltage Input Rise/Fall Time Output Reference Voltage Value 2.4/0.4 Unit LVTTL Note LVTTL LVTTL
Output Load Capacitance Access Time Measurement Note Note Output load measure access times equivalent gates capacitance(50pF).
Note
Output
Output Load Circuit
Rt=500 50pF Vtt=1.4V Output
Output Load Circuit
Z0=50
50pF
Vtt=1.4V
HYM7V64400/ HYM7V64401/ HYM7V64430/ HYM7V64431 Q-Series
CHARACTERISTICS(I)
Symbol Parameter Input Leakage Current Output Leakage Current Output Voltage Output High Voltage Test Condition VI=0 3.6V, other pins undertest=0V DOUT disabled, VO=0 3.6V IO=2.0mA IO=-2.0mA
(TA=0°C 70°C, VCC=3.3V±10%, VSS=0V) Min. Max. Unit LVTTL LVTTL Note
CHARACTERISTICS(II)
Symbol ICC1 Parameter Operating current Precharge Standby Current Power Down Mode Precharge Standby Current Power Down Mode Active Standby Current Power Down Mode Active Standby Current Power Down Mode Operating Current (Burst Mode)
(TA=0°C 70°C, VCC=3.3V±10%, VSS=0V) Test Condition Burst Length=1, bank active tRAStRAS(min), tRPtRP(min), IO=0mA CKEVIL(max) CKEVIH(min), other pinsVCC-0.2V 0.2V CKEVIL(max), banks active CKEVIH(min), other pinsVCC-0.2V 0.2V banks active tCLKtCLK(min), tRAStRAS(min), IO=0mA, /CAS Latency=3 tRCtRC(min), banks active (8K/128ms) tRCtRC(min), Four banks active (4K/64ms) 10ns 12ns 15ns 10ns 12ns 15ns 10ns 12ns 15ns 10ns 12ns 15ns Max. Unit Note Note
ICC2P ICC2N
LVTTL1
ICC3P ICC3N
LVTTL1
ICC4
Note
Note
ICC5
Refresh Current
Note
ICC6
Self Refresh Current
CKE0.2V
Note depends number each pins transition. assumed there transition measure this current. ICC1 depends output loads cycle rates. Specified values obtained with output open. addition this ICC1 measured condition that addresses changed only time during tCLK(Min.)
HYM7V64400/ HYM7V64401/ HYM7V64430/ HYM7V64431 Q-Series
CHARACTERISTICS
Synchronous Characteristics(I)
100MHz 83MHz 66MHz (10ns) (12ns) (15ns) /CAS Latency Frequency Clock Cycle Time tRCD tRAS tRRD tDPL tDAL tSRE 8K/128ms, 4K/64ms Refresh Cycle Parameter Unit Latency CLK(s) CLK(s) CLK(s) CLK(s) CLK(s) CLK(s) CLK(s) CLK(s) Cycles
Asynchronous 50ns Part Characteristic Note tRRD -Bank Active Active Command tDPL -DIN Precharge Command tDAL -DIN Active(Ref.) Command (After Write with Autoprecharge) tSRE -Self Refresh Exit Time
Synchronous Characteristics(II)
Symbol Parameter /CAS Lat.=3 tOLZ tOHZ tCKS tCKH tPDE
Min. Max. Min. Max. Min. Max. /CAS Lat.=2 /CAS Lat.=1
Unit
Note
Access Time from High Level Width Level Width Data-out Hold Time
Data-out Low-Impedance Time Data-out High-Impedance Time Data-in Set-up Time Data-in Hold Time Address Set-up Time Address Hold Time Set-up Time Hold Time Command Set-up Time Command Hold Time Power Down Exit Set-up Time
HYM7V64400/ HYM7V64401/ HYM7V64430/ HYM7V64431 Q-Series
Latency
Symbol tCKED tDQMOZ tDQMIM tWTL Parameter Suspend Power Down Mode Entry Data Output Hi-z Data Input Mask Write Command Data Input Valid /CAS Latency=1 tPROZ Precharge Command Data Output Hi-z /CAS Latency=2 /CAS Latency=3 tMRD tCCD tPPD Mode Register Command Min. Column Address Column Address Delay Min. Precharge Precharge Time Latency
Note voltages referenced VSS(Ground). initial pause 100µS required after power-on followed Power Sequence Auto Refresh before proper device operation achieved. measurements assume tT=1ns. Reference level measuring timing input signals 1.40V LVTTL Transition times measured between VIL. access time measured 1.40V LVTTL
CAPACITANCE
Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 COUT Parameter Input Capacitance Input Capacitance Input Capacitance Input Capacitance Input Capacitance Input Capacitance Output Capacitance A0-A11/12, BA0/BA1 /RAS, /CAS, CKE0 DQM0-DQM7 DQ0-DQ63
(TA=25°C, f=1MHz) Typ. Max. Unit
HYM7V64400/ HYM7V64401/ HYM7V64430/ HYM7V64431 Q-Series
PROGRAMMABLE MODE REGISTER
MODE REGISTER SET(WRITE)
/CAS Latency
Burst Length
Burst Type Sequential (Wrap round, Binary-up) Interleave (Wrap round)
/CAS Latency Reserved Reserved Reserved Reserved Reserved
Burst Length Reserved Reserved Reserved Full page1
Note Full page burst supports only sequential type.
TEST MODE
Address Refresh Counter Test
Note Test Mode Used test counter Auto Refresh. Exit test mode using Precharge banks.
HYM7V64400/ HYM7V64401/ HYM7V64430/ HYM7V64431 Q-Series
BURST LENGTH SEQUENCE
Burst Length
Initial Address Sequential 0,1,2,3 1,2,3,0 2,3,0,1 3,0,1,2 0,1,2,3,4,5,6,7 1,2,3,4,5,6,7,0 2,3,4,5,6,7,0,1 3,4,5,6,7,0,1,2 4,5,6,7,0,1,2,3 5,6,7,0,1,2,3,4 6,7,0,1,2,3,4,5 7,0,1,2,3,4,5,6 0,1,2,3,4,.,m 1,2,3,4,5,.,0 m,0,1,2,3,.,m-1
Burst Type Interleave 0,1,2,3 1,0,3,2 2,3,0,1 3,2,1,0 0,1,2,3,4,5,6,7 1,0,3,2,5,4,7,6 2,3,0,1,6,7,4,5 3,2,1,0,7,6,5,4 4,5,6,7,0,1,2,3 5,4,7,6,1,0,3,2 6,7,4,5,2,3,0,1 7,6,5,4,3,2,1,0
Full page
Note
supported
Table Address sequence different burst lengths Note 2Mbit 2banks 16I/O Initial addresses: A7-A0, Page length: 1024, m=1023 1Mbit 4banks 16I/O Initial addresses: A7-A0, Page length: 1024, m=1023
HYM7V64400/ HYM7V64401/ HYM7V64430/ HYM7V64431 Q-Series
PACKAGE DIMENSION
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