APPLICATION NOTE AN-68 This application note describes hassles in

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APPLICATION NOTE AN-68 This application note describes hassles in

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DUAL-PORT SRAM SIMPLIFIES PC-TO-TMS320 INTERFACE
APPLICATION NOTE AN-68
This application note describes hassles interface between PC-style backplane TMS320C30 chip dualport static RAM. interface provides extremely simple means downloading cross-compiled code well sample data sets debugging high speed TMS320 based system real time. This example also shows easily interprocessor communications hardware implemented simple insertion dual-port SRAM between chip general purpose processor standard system. system like this would typically standard data input/output ordering, would pass complete data sets chip intense calculation. Similar architectures often used graphics image processing, where entire image manipulated single data set, transform calculations (i.e. FFTs) sonar radar processing. Certain systems even this scheme several times with numerous chips order processing speeds proportional number chips system.
System Objective
design presented here TMS320C30 Software Development Board. This board portion system which helps TMS320C30 programmer download debug code from similar computer. order support special hardware needs TMS320C30 programmer, expansion connector allows memory added chips primary bus, while target connector provides fully buffered version chips expansion allow connection special purpose hardware. Most TMS320C30s status signals also routed expansion make them available hardware being debugged. majority control software PC-resident, provided magnetic media. This includes such tools assembler, compilers, download debug routines. EPROM array primary TMS320 provides host processor with commands allow load software development boards RAMs, clear breakpoints, examine preset internal status, load store values individual memory locations. these controlled hosts sending command TMS320, which interprets that command takes appropriate action. high speed static attached each chips buses: expansion bus, primary bus. expansion SRAM would typically used store data operated upon,
primary would used store code which would debugged using this board. Both these SRAMs zero wait-state (25ns access times 33MHz) allow real-time debugging benchmarks performed. Since TMS320s expansion only supports addressing locations, bank select signal used switch between upper lower halves this ports memory. This signal software-controlled from processors expansion bus. design goal this system move data into DSPs dedicated memory without taking inordinate amount time hardware. standard memory were shared between host chip, multiplexing logic would need inserted between each processor RAMs address, data, control lines. This logic would find itself right critical timing path memories primary expansion buses, would make zero wait-state operation nearly unachievable. additional headache would have been finding room board large amount multiplexing logic required. Should design have used simpler method passing data back forth between processors either UART single byte-wide buffer, developer would have endured long delays during download other communication functions software either side port performed massive amounts handshaking pass even smallest data sets. became obvious early design cycle that simplest method performing fast host communication would large highspeed true dual-port static perform interprocessor communications. dual-port would allow both host chip transfer data packets, rather than individual bits bytes, thus accelerating downloading. selected dual-port device would have which provided some means signalling that data packets were ready handed back forth between processors. IDT71342 chosen because speed, depth bytes), simplicity interface, ability perform interprocessor communications through eight internal semaphore flags (see Appendix: Dual-Port Semaphores). using IDT71342, designers could single chip implement byte high speed block transfers between host TMS320, signal completion transfer without additional hardware. Although 45ns access time dual-port used this system does support zero-wait data transfers maximum speeds, data transfers critical path sort software this system used debug. true zero wait-state system could have been
MARCH 1999
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©1999 Integrated Device Technology, Inc. 2694/4
Dual-Port Simplifies PC-to-TMS320 Interface
Application Note AN-68
TARGET CONNECTOR
TIOA0-12 TIOD0-31 PALS, CONTROL, STATUS LOGIC
IDT71342
XD0-7 SD0-7 CIOD0-31
TMS320C30
CD0-31 DD0-31
LEFT SIDE
RIGHT SIDE
PRIMARY
EPROM SRAM
EXPANSION
EXPANSION
BA0-31
realized designers used 25ns dual-port. Figure shows block diagram complete system. full schematic system shown Figure
IDT71342 dual-port uses interface which similar standard single-port byte wide static RAM. Each ports (left right) uses separate control, address, pins. Address inputs multiplexed with data I/O. control interface consists three pins either side: read/write (R/W), output enable (OE), chip enable (CE). pins also operate conjunction with semaphore select (SEM), which imitates functionality chip enable pin, rather than allowing reads writes memory array, this routes read write control eight on-chip semaphore flags. Write cycles controlled simultaneous application logic both inputs side SRAM, either signal used control timing write cycle. signal held timing pulse pin, called controlled write cycle(figure Write cycles where stays while pulsed called controlled write cycles (figure offering both methods communication, IDTs dual-port SRAMs easily connected between systems with greatly differing interface specifications. interesting point about this design that while host side dual-port uses controlled write cycle, writes side dual-port using controlled write cycle.
Interfacing Dual-Port SRAM
XA0-19 SA0-19
SRAM
BIOA0-11 CIOA0-12
CA0-31
2694
Figure TMS320C30 Software Development Board Block Diagram
this design, control signals routed nearly directly from backplane IDT71342s pins. signal functions timing backplane ideal match with those dual-port RAM. However, decision made memory array into space memory space, while semaphores were mapped into space, which forced MEMW signals ORed before driving them into IDT71342s input. Likewise MEMR signals ORed before driving them into IDT71342s input. dual-ports chip enable (CE) driven indirectly address decoder consisting eight comparator 74ALS521 which compares output 74LS377 register with addresses A12-A19. 74LS377 mapped register that allows dual-port SRAM mapped into 4K-byte region main memory space. resident control register board allows dual-port memory disabled, which state power-up reset. semaphore enable (SEM) driven 20L8 which decodes addresses from Bus. This decoder determines whether host accessing memory space MEMR, MEMW, IOR, signals, enables semaphores during access proper address (A0-A9) applied inputs PAL. also uses MEMW signals generate controlled write cycle, while using decoded addresses drive inputs.
Interface
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Dual-Port Simplifies PC-to-TMS320 Interface
Application Note AN-68
Symbol WRITE CYCLE
Parameter
Write Cycle Time Chip Enable End-of-Write Address Valid End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time Data Valid End-of-Write Output High-Z Time Data Hold Time Write Enable Output High-Z Output Active from End-of-Write
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ADDRESS
DATAOUT
DATAIN
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Figure Timing Waveform Write Cycle Controlled Timing(1,5,8).
NOTES: must HIGH during address transitions. write occurs during overlap (tEW tWP) either VIL. measured from earlier going HIGH end-of-write cycle. During this period, pins output state, input signals must applied. transition occurs simultaneously with after transition, outputs remain High-impedance state. Timing depends which enable signal R/W) asserted last. This parameter guaranteed device characterization, production tested. Transition measured +500mV from steady state with Output Test Load (Figure during controlled write cycle, write pulse width must larger (tWZ tDW) allow drivers turn data placed required tDW. HIGH during controlled write cycle, this requirement does apply write pulse short specified tWP. access SRAM, =VIL VIH. access semaphore, VIL. Either condition must valid entire time.
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Dual-Port Simplifies PC-to-TMS320 Interface
Application Note AN-68
ADDRESS
tAS(5)
DATAIN
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Figure Timing Waveform Write Cycle Controlled timing(1,4).
NOTES: must HIGH during address transitions. write occurs during overlap (tEW tWP) either VIL. measured from earlier going HIGH end-of-write cycle. transition occurs simultaneously with after transition, outputs remain High-impedance state. Timing depends which enable signal R/W) asserted last. access SRAM, =VIL VIH. access semaphore, VIL. Either condition must valid entire time.
data address pins IDT71342 isolated from backplane with buffers. detail dual-port interface shown Figure reader should note that several considerations increased complexity this interface. this design involved dedicated host processor rather than general purpose need buffering would probably have been drastically reduced. both byte SRAM semaphores been mapped into memory space host, ORing
would have been required MEMW, MEMR, IOW, signals. Finally, very complex address decoder imple-mented this system allow IDT71342s mapped anywhere within memory space. using more straightforward fixed-address scheme, logic complexity could significantly reduced. conceivable that entire interface including address decoding could have been handled with single
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Dual-Port Simplifies PC-to-TMS320 Interface
Application Note AN-68
74ALS623
IDT71342S45
1/07L 1/06L 1/05L 1/04L 1/03L 1/02L 1/01L 1/00L
PC-STYLE BACKPLANE
74ALS541
A11L A10L
74ALS541
MEMW MEMR
74AS08
R/WL
PAL20L8-15
I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 SEML
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Figure IDT71342 Dual-Port Interface (Left-Hand Side Dual-Port).
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Dual-Port Simplifies PC-to-TMS320 Interface
Application Note AN-68
IDT71342S35
IO7-R IO7R IO6R IO6R IO5-R IO5R IO4-R IO4R IO3-R IO3R IO2-R IO2R IO1-R IO1R IO0-R IO0R
74AS244
74AS244
XA10 XA11 XA12
A10R A11R
IOSTRB XR/W
74AS04
OE-R R/W-L R/WR
PAL20L8-15
I/O5 I/O1 I/O2 I/O3 I/O4 I/O6
74AS32
SEMR SEM-R CE-R
74AS32
TIORDY (from target connector)
74AS11
74ALS74
MSTRB XRDY
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Figure TMS320C30 IDT71342 Dual-Port Interface (Right-Hand Side Dual-Port).
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Dual-Port Simplifies PC-to-TMS320 Interface
Application Note AN-68
TMS320C30 Interface
TMS320 interfaces dual-port SRAM through strobe expansion bus. same used interface static memory strobe signal. These strobes signify different ranges chips internal address map. detailed diagram TMS320 IDT71342 interface shown Figure interface, address lines buffered between processor dual-port SRAM, however light loading data removes need data buffering this side. only devices connected data pins are: dual-port SRAM, chip, static RAM, status latch, transceiver. address needed buffering since eight chips, well dual-port, PAL, address buffer attached these pins. TMS320s expansion uses strobe activate cycle, level distinguish read cycles from write cycles. this design, expansion read/write (XR/W) output TMS320 connected directly IDT71342 dual-port drive read/write (R/W) input, simply inverted drive output enable (OE) input. This inverter truly necessary, since dual-port places data outputs into highimpedence state automatically upon application write (LOW) level input. this side could have been permanently tied active (grounded). 20L8 used control chip enable (CE) input this side dual-port SRAM. This signal decoding DSPs expansion address bits XA0-XA12. used this interface product terms allow combination strobe with decoded address, buffered strobe (BIOSTRB) been externally ANDed with decoded address output from before being into dual-port. semaphore select handled same way, different address decoding used from same PAL, strobe ANDed through different gate into semaphore (SEM) input dual-port. Both these signals disabled writing control register. TMS320C30 writes dual-port SRAM implementing controlled write cycle. inputs driven two-input gates. inputs each these gates represents decoded address output from 20L8 PAL, while second input driven buffered version strobe. only other qualifying input read/write (R/W) input, which directly driven expansion read/
write (XR/W) signal TMS320. When chip writes dualport, address read/write signals output first, followed strobe. Since IOSTRB used gate signal, timing meets criteria controlled write cycle. expansion ready (XRDY) input TMS320, which tells that expansion cycle complete, combination decoded address range from clock delay from TMS320s (clock/2) output. This signal required systems using slower dual-port RAMs, necessary systems where faster dual-ports used. system designer choses 25ns faster part 33MHz TMS320C30 system, XRDY input generated immediately upon accessing dual-port RAM. gating used here generates single wait-state strobe within address range IDT71342. This logic could removed faster IDT71342 were used. IOSTRB output from TMS320, decodes dual-ported address, strobe decoded address combined second gates Fig. This gates output into XRDY gate extend expansion cycle. next rising edge IOSTRB clocked into flip flop. This flip flops output connected first gate disables IOSTRB from reaching second gate. This turn allows XRDY input TMS320 active, allows cycle end. single wait-state more than compensates 45ns address access time dual-port used this application. Other signals called target ready (TIORDY) from target connector, MSTRB signal from chip itself also signal expansion ready state. Since MSTRB signal used only control accesses expansion zero wait-state RAM, ORed directly back XRDY input through 74AS11 gate shown.
Conclusion
TMS320C30 Software Development Board shows simplicity designing interface between TMS320 chip using IDT71342 dual-port RAM. dual-port serves reduce component count, increase interprocessor communications throughput, simplify design. Designers should able follow example given here profitably dual-port SRAMs handle communications similar dual processor system.
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Dual-Port Simplifies PC-to-TMS320 Interface
Application Note AN-68
Appendix Dual-Port Semaphores
Eight extra address locations IDT71342 dual-port dedicated binary semaphore flags. These flags allow either TMS320 host processor claim privilege over other processor functions defined programmers software. example, semaphore used inhibit TMS320C30 from accessing portion dual-port SRAM, some other shared resource. dual-port SRAM features fast access time, both ports completely independent each other. This means that activity left port slows access time right port. Both ports identical function standard static RAMs read from, written same time with only possible conflict arising from simultaneous writing simultaneous READ/WRITE nonsemaphore location. Semaphores protected against such ambiguous situations used system program avoid conflicts non-semaphore portion dual-port SRAM. Multiple processor sytems like TMS320C30 Software Development Board benefit from performance increase using these semaphores, which provide lockout mechanism without requiring complex programming. Software handshaking between processors offers maximum system flexibility permitting shared resources allocated varying configurations. IDT71342 does semaphore flags control resources through hardware, thus allowing programmer determine each flags meaning.
Semaphore Flags Work
semaphore logic eight latches which independent dual-port SRAM. These latches used pass flag, token, from processor other indicate that shared resource use. semaphores provide hardware assist assignment called Token Passing Allocation. this method, state semaphore latch used token indicating that shared resource use. TMS320 wants this resource, requests token writing zero into latch. TMS320 then verifies success writing latch reading successful, proceeds assume control over shared resource. successful writing zero into latch, determines that latch first, posession token, using
shared resource. TMS320 then either repeatedly inquire status semaphore requested, remove request that semaphore writing into location. TMS320 then perform another task occasionally attempt gain control token test sequence. Once relinquished token, TMS320 succeed gaining control shared resource. semaphore flags active low. token requested writing zero into semaphore location, released when same processor writes into that location. eight semaphore flags reside within IDT71342 seperate memory space from dual-port RAM. This address space accessed placing input (which used chip select semaphore flags), using other control pins (Address, R/W) they would used accessing standard static SRAM. Each flags unique address which accessed either side through address pins When accessing semaphores, none other address pins effect. When writing semaphore, only data used. level written into unused semaphore location, that flag will zero that side other (see Table That location only modified side showing zero. When written into same location from same side, flag will both sides (unless semaphore request from other side pending) then written both sides. fact that side which able write zero into semaphore subsequently locks writes from other side what makes semaphore flags useful interprocessor communications. zero written into same location from other side will stored semaphore request latch that side until semaphore freed first side. When semaphore flag read, value spread into data bits, that flag reads data bits flag containing zero reads zeros. read value latched into sides output register when that sides semaphore select (SEM) output enable (OE) signals active. This serves disallow semaphore from changing state middle read cycle write cycle from other side. Because this latch, repeated read semaphore test loop must cause either signal (SEM inactive, output will never change. This concern TMS320C30 Software Development Board, since either accesses other memory locations between semaphore accesses inactivate both these signals relatively long period matter tight loop used interrogate device.
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Dual-Port Simplifies PC-to-TMS320 Interface
Application Note AN-68
FUNCTION action writes semaphore TMS320 writes semaphore writes semaphore writes semaphore TMS320 writes semaphore writes semaphore TMS320 writes semaphore TMS320 writes semaphore writes semaphore writes semaphore
D0-D7 LEFT
TM320 D0-D7 RIGHT
STATUS Semaphore free semaphore token change. TMS320 write access semaphore TMS320 obtains semaphore token change. write access semaphore. obtains semaphore token Semaphore free TMS320 semaphore token Semaphore free semaphore token Semaphore free
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Table Example Semaphore Procurement Sequence
sequence WRITE/READ must used acquire semaphore order guarantee that system level contention will occur. processor requests access shared resources attempting write zero into semaphore location. semaphore already use, semaphore request latch will contain zero, semaphore flag will appear one, fact which processor will verify subsequent read (see Table example, assume writes zero left port free semaphore location. subsequent read, will verify that written successfully that location will assume control over resource question. Meanwhile, TMS320 attempts write zero same semaphore flag, will fail, will verified fact that will read from that semaphore during subsequent read cycle. sequence READ/WRITE been used instead, contention problems could have occurred during between read write cycles. important note that failed semaphore request must followed either repeated reads, writing into same location remove semaphore request. reason this easily understood looking simple logic diagram semaphore flag shown Figure semaphore request latches feed into semaphore flag. Whichever latch first present zero semaphore flag will force side semaphore flag low, other side high. This condition will continue until written into same semaphore request latch. Should other sides semaphore request latch have been written zero meantime, semaphore flag will flip over other side soon written into first sides request latch. second sides flag will
stay until semaphore request latch written with one. From this easy understand that, semaphore requested processor which requested longer needs resource, entire system could hang until written into that semaphore request latch. critical case semaphore timing when both sides request single token attempting write zero into same time. semaphore logic specially designed resolve this problem. simultaneous requests made, logic guarantees that only side receives token. side earlier than other making request, first side make request will receive token. both requests happen same time, assignment will arbitrarily made side other. caution that should noted when using semaphores that semaphores alone guarantee that access resource secure. with powerful programming technique, semaphores misused misinterpreted software error easily happen. Code integrity utmost importance when semaphores used instead hardware handshaking. Initialization semaphores automatic must handled initialization program power-up. Since semaphore which written zero must reset one, both TMS320 must write into semaphore locations initialization assure that semaphores will free when needed.
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Dual-Port Simplifies PC-to-TMS320 Interface
Application Note AN-68
Port
Semaphore RequestLatch Write
Port
Semaphore RequestLatch Write
Semaphore Read
Semaphore Read
Semaphore Latch
2694
Figure IDT71342 Semaphore Logic
Using Semaphores Some Examples
Perhaps simplest application semaphores their application resource markers IDT71342s dual-port SRAM. SRAM divided into blocks, which were dedicated time servicing either TMS320. Semaphore could used indicate side which would control lower section memory, Semaphore could defined indicator upper section memory. take resource, this example lower dual-port RAM, could write then read zero into Semaphore this task successfully completed zero read back, rather than one), would assume control lower Meanwhile, TMS320 might attempt perform same function. Since TMS320 attempting gain control resource after would read back response zero attempted write into Semaphore this point, TMS320s software could choose gain control second section writing, then reading zero into Semaphore succeeded gaining control, would lock Once finished with task, would write Semaphore then gain access Semaphore Semaphore still occupied TMS320, could remove semaphore request perform other tasks until able write, then read zero into Semaphore TMS320 performs similar task with Semaphore this protocol would allow processors swap blocks dual-port with each other. blocks have particular size could even
variable length, depending upon complexity software using semaphore flags. eight semaphores could used divide dualport other shared resources into eight parts. Semaphores useful form arbitration real-time applications, when must locked section memory during transfer, TMS320 cannot tolerate wait states. With semaphores, once processors determined which memory area limits both TMS320 could access their assigned portions memory continuously without wait states. Both processors access their assigned segments full speed. Another application semaphores area complex data structures. this case, block arbitration very important maintenence data integrity. this application processor responsible building updating data structure, which other processor then reads interprets. interpreting processor reads incomplete data structure, major error condition exist. Therefore, some sort arbitration must used between TMS320 Software semaphores perfect fit. building processor uses semaphore arbitrate block lock once that processor able acquire semaphore flag. This processor then able update data structure. When update completed, semaphore corresponding data structure block released. interpreting processor then acquires semaphore which allows come back read complete data structure, thereby guaranteeing consistency.
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APPLICATION NOTE AN-68 This application note describes hassles in

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