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Description MH1RT Gate Array Embedded Array families from Atmel f


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1.6M Used Gates Pads with 3.3V, 2.5V Libraries High Speed Gate Delay Input NAND, (nominal) System Level Integration Technology Cores Request Memories: SRAM TPRAM, Gate Level Embedded, with EDAC Interfaces: Tolerant/Compliant Matrix Options CMOS, LVTTL, LVDS, PCI, USB, etc. Output Currents Programmable from Step Cold Sparing Buffers Max. Leakage Current 3.6V Worst Case Temp.) request), LVDS Max. Toggle Frequency 3.3V Deep Submicron Flow Latch-up Immune; 300K rads Total Dose Capability; Free Cells; 4000V Protection with 5962-01B01, (100 Krads)
Description
MH1RT Gate Array Embedded Array families from Atmel fabricated radiation tolerant 0.35 micron CMOS process, with levels metal interconnect. This family features arrays with million routable gates pads. high density high count capabilities MH1RT family, coupled with ability embed cores memories same silicon, make MH1RT series arrays best choices System Level Integration. MH1RT series supported advanced software environment based industry standards linking proprietary commercial tools. Verilog®, DFT®, Synopsys® Vital reference front tools. Cadence® `Logic Design Planner' floor planning associated with timing driven layout provides efficient back cycle. MH1RT series comes dual series, adding: through process changes, latch-up immunity 300K rads total dose capability required most space programs through cells relayout, immunity allowing harden only where necessary with respect function requirements With background years experience, MH1RT series comes Atmel generation ASIC series designed radiation hardened applications.
Hard 1.6M Used Gates 0.35 CMOS Gates/ Embedded Array
MH1RT
Rev. 4110G-AERO-07/03
Table List Available MH1RT Matrices
Device Number MH1099E MH1156E MH1242E MH1332E Notes: Typical Routable Gates 519,000 764,000 1,198,000 1,634,000 Count Count Gate Speed(1) Max. Sites Count 920,385 1,447,975 2,275,377 3,098,804
Nominal Input NAND Gate 3.3V.
Design
Design Systems Supported
Atmel supports several major software systems design with complete macro cell libraries, well utilities checking netlist estimated pre-route delay simulations. following design systems supported: Table Supported design systems
System Available Tools Verilog-XL® Verilog Simulator Logic Design Planner- Floorplanner BuildGates® Synthesis (Ambit) Modelsim Verilog VHDL (VITAL) Simulator DFT- Scan insertion ATPG, BIST Design Compiler- Synthesis Primetime® Static Path Formality® Equivalence Checking
Cadence
Mentor/Model Tech
Synopsys®
MH1RT
4110G-AERO-07/03
MH1RT
Design Flow Tools
Atmel's design flow Gate Array/Embedded Array structured allow designer consolidate greatest number system components possible onto same silicon chip, using available third party design tools. Atmel's cell library reflects silicon performance over extremes temperature, voltage, process, includes effects metal loading, inter-level capacitance, edge rise fall times. Design Flow includes clock tree synthesis minimize skew latency. extraction performed final design database incorporated into timing analysis. Typical Gate Array/Embedded Array Design Flow, shown page provides pictorial description typical interaction between Atmel's Gate Array/Embedded Array design staff customer. Atmel will deliver design kits support customer's synthesis, verification, floorplanning, SCAN insertion activities. Tools such Synopsys Synthesis, Cadence Mentor Logic Simulators used, many others available. Should design include embedded memory embedded core, Atmel needs understand partition Array, define location memory blocks and/or cores (preliminary place route) that underlayer layout model created (Base Wafer). Following Preliminary Design Review, called Logic Review, design routed, post-route data extracted. Following post-route verification Final Design Review, called Design Review, design taped fabrication. purpose these reviews check conformity design Atmel rules, acknowledge formal documents.
4110G-AERO-07/03
Figure Typical Gate Array/Embedded Array Design Flow
Atmel Design Delivery
Kickoff
Base Wafer Definition
Design Synthesis
SCAN Insertion
Functional Static Path Sims
Atmel Floorplan Preliminary Place Route Base Wafer Creation Atmel Database Handoff Database Acceptance Base Wafer
Pre-route Verification
Logic Review Atmel
Place Route Clock Tree
Atmel Base Wafer Fabrication
Post-route Verification
Design Review Atmel
Tape Metallization Layers
Atmel Masks Generation Atmel
Joint Atmel Customer
Fab., Assembly Test
Rev.1.6 07/2003
MH1RT
4110G-AERO-07/03
MH1RT
Definition Requirements
corner pads reserved Power Ground only. other pads fully programmable Input, Output, Bidirectional, Power Ground. When implementing design with tolerant buffers, buffer site must reserved VDD5 pin, which used distribute power buffers. Figure Gate Array
Figure Embedded Array
SRAM
Standard Gate Array Architecture
Core
Core
Site: SubSections
sites configured input, output, 3-state output bidirectional buffers, each with pullup pulldown capability, required, utilizing their corresponding subsection. Bidirectionnal buffers result input output buffers placed adjacent sub-sections same site. Special buffers require multiple sites. Oscillators require sites, each power ground utilizes site. compatible input output buffers available each bias voltage, Each LVDS buffer uses sites. LVDS drivers specific each bias voltage require external current bias resistor chip; LVDS receiver same bias voltages requires external line matching resistor receiver.
Buffers LVDS Buffers
Cold Sparing
twice same chip, OFF, with signal pins/pads connected pairs, A1I1 with A2I1, A101 with A201,.
4110G-AERO-07/03
During this mode operation: chip must survive operate when turned without functional, reliability impact, current pulled chip must limited value: Atmel specification their dedicated cold sparing buffers worst case signal pins/pads.
other operation mode, refer maximum ratings.
Memory Blocks
Memory blocks either synthesized gates (when smaller than bits) compiled embedded array itself. Various combinations Through Flow Watch EDACs, wide, used alleviate effect induced errors.
MH1RT
4110G-AERO-07/03
MH1RT
ASIC Design Translation
Atmel successfully translated existing designs from most major ASIC vendors (LSI Logic®, Motorola®, SMOS®, Oki®, NEC®, Fujitsu®, AMI® others) into gate arrays. These designs have been optimized speed gate count modified logic memory, replicated pin-to-pin compatible, drop-in replacement. Design entry performed customer using Atmel ASIC library. complete netlist vector must then provided Atmel. Upon acceptance this data set, Atmel continues with standard design flow. Atmel successfully translated existing FPGA/PLD designs from most major vendors (Xilinx®, Actel®, Altera®, AMD® Atmel) into gate arrays. There four primary reasons convert from FPGA/PLD gate array. Conversion high volume devices single combined design cost effective. Performance often optimized speed power consumption. Several FPGA/PLDs combined onto single chip minimize cost while reducing on-board space requirements. Finally, situations where FPGA/PLD used fast cycle time prototyping, gate array provide lower cost answer long-term volume production. Atmel's MH1RT Series gate arrays make extensive library macro cell structures, including logic cells, buffers inverters, multiplexers, decoders, options. Soft macros also available. MH1RT Series operates frequencies with minimal phase error jitter, making ideal frequency synthesis high speed on-chip clocks chip chip synchronization. These cells well characterized SPICE modeling transistor level, with performance verified manufactured test arrays. Characterization performed over rated temperature voltage ranges ensure that simulation accurately predicts performance finished product.
Cells Logic Cells Buffers 2.5V 3.3V Tolerant Compliant Specific Cells LVDS, Hardened Cells Cold Sparing Number Cells
Design Entry
FPGA Conversions
Cell Library
4110G-AERO-07/03
Electrical Characteristics
Absolute Maximum Ratings
Operating Ambient Temperature .-55°C +125°C Storage Temperature. -65°C +150°C Maximum Input Voltage .+0.5V 0.5V Maximum 3.3V Operating Voltage. (VDD) Maximum Operating Voltage. (VCC)
*NOTE:
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions beyond those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
Characteristics
Applicable over recommended operating temperature voltage range unless otherwise noted. Table 2.5V Characteristics
Symbol Parameter Operating Temperature Supply Voltage Low-level Input Current Pull-up resistors PRU1 Pull down resistor PRD1 Buffer Test Condition Min. Max. Units
CMOS
High level Input Current Pull-up resistors PRU1 Pull down resistor PRD1 CMOS
Max.) Vss, (Max.) pull resistor
High impedance state output current
CMOS
0.3Vdd
0.325Vdd
level Input voltage
Schmitt level CMOS
0.475Vdd
0.62
Delta
High level Input voltage CMOS Hysterisis
Schmitt level
1.56 0.42 3.3V 3.3V Iocs (Min.)
Iics
Cold sparing leakage input current PICZ Cold sparing leakage output current Supply threshold cold sparing buffers
Iocs Vcsth
POxxZ POxxZ
Low-level Output Voltage PO11
MH1RT
4110G-AERO-07/03
MH1RT
Table 2.5V Characteristics (Continued)
Symbol Parameter Buffer Test Condition -0.6 (Min.) (Max.), Vout Vouy (Max.) (Max.) 0.27 Min. Max. Units High level output voltage PO11 Output short circuit current Iosn Iosp Leakage current cell Dynamic current gate
Iccsb Iccop
PO11 PO11
µW/MHz
standard pull-ups: (#), {1-31} index Ron: where typ, Max., Min. standard pull-downs: (#), {1-31} index Ron: where typ, Max., Min. Guaranteed tested output buffers (1-C) (1-C):
1-C: value: convert decimal n-channel output drive standard buffers (including cold sparing) measured 0.4V
output buffers (1-C) (1-C):
1-C: value: convert decimal n-channel output drive -0.6 standard buffers (including cold sparing) measured
Applicable over recommended operating temperature voltage range unless otherwise noted.
4110G-AERO-07/03
Table Characteristics
Symbol Parameter Operating Temperature Supply Voltage Low-level Input Current Pull-up resistors PRU1 Pull down resistor PRD1 High level Input Current Pull-up resistors PRU1 Pull down resistor PRD1 High impedance state output current Buffer Test Condition Min. Max.
0.325Vdd
Units
CMOS
CMOS
VDD( Max.) Vss, (Max.) pull resistor
CMOS
level Input voltage
Schmitt level CMOS
0.475Vdd
0.72
Delta Iics Iocs Vcsth
High level Input voltage CMOS Hysterisis
Schmitt level
1.89 0.53 3.3V 3.3V Iocs µW/MHz
Cold sparing leakage input current PICZ Cold sparing leakage output current Supply threshold cold sparing buffers Low-level Output Voltage POxxZ POxxZ
PO11
Vdd(Min.) -0.8 Vdd(Min.) Vdd(Max.), Vout Vouy Vdd(Max.) Vdd(Max.)
High level output voltage
PO11 PO11 PO11
Iccsb Iccop
Output short circuit current Iosn Iosp Leakage current cell Dynamic current gate
standard pull-ups: (#), {1-31} index Ron: where typ, Max., Min. standard pull-downs: (#), {1-31} index Ron: where typ, Max., Min. Guaranteed tested. output buffers (1-C) (1-C): 1-C: value: convert decimal n-channel output drive standard buffers (including cold sparing) measured 0.4V
MH1RT
4110G-AERO-07/03
MH1RT
output buffers (1-C) (1-C):1-C: value: convert decimal n-channel output drive -0.8 standard buffers (including cold sparing) measured 2.4V Parameter Operating Temperature Supply Voltage Low-level Input Current Pull-up resistors PRU1 Pull down resistor PRD1 High level Input Current Pull-up resistors PRU1 Pull down resistor PRD1 High impedance state output current Buffer Test Condition Min. Max.
0.325Vdd
Table 3.3V Characteristics
Symbol Units
CMOS
CMOS
VDD( Max.) Vss, Vdd(Max.) pull resistor
CMOS
level Input voltage
Schmitt level CMOS 0.475Vdd 0.61 3.3V 3.3V Iocs
Delta Iics Iocs Vcsth
High level Input voltage CMOS Hysterisis
Schmitt level
Cold sparing leakage input current PICZ Cold sparing leakage output current Supply threshold cold sparing buffers Low-level Output Voltage POxxZ POxxZ
PO11
Vdd(Min.) -1.8 Vdd(Min.) Vdd(Max.), Vout Vouy Vdd(Max.) Vdd(Max.) 0.63
High level output voltage
PO11 PO11 PO11
Iccsb Iccop
Output short circuit current Iosn Iosp Leakage current cell Dynamic current gate
µW/MHz
standard pull-ups: PRU(#), {1-31} index Ron: where typ, Max., Min. standard pull-downs:PRD(#), {1-31} index Ron: where typ, Max., Min. Guaranteed tested. output buffers (1-C) (1-C): 1-C: value: convert n-channel output drive standard buffers (including cold sparing) measured 0.4V
4110G-AERO-07/03
output buffers (1-C) (1-C): 1-C: value: convert n-channel output drive -1.8 standard buffers (including cold sparing) measured 2.4V
Applicable over recommended operating temperature voltage range unless otherwise noted. Table Characteristics
Symbol Parameter Operating Temperature Supply Voltage Supply Voltage Low-level Input Current Pull-up resistors PRU1 Pull down resistor PRD1 Buffer Tolerant Compliant Test Condition Min. Max.
0.325Vdd
Units
CMOS
High level Input Current Pull-up resistors PRU1 Pull down resistor PRD1 CMOS High impedance state output current
VDD( Max.) orVss,Vdd=Vdd(max pull resistor
PICV, PICV5
level Input voltage
Schmitt level PICV, PICV5 0.475Vdd 3.3V 3.3V Iocs
High level Input voltage
Schmitt level
Iics
Cold sparing leakage input current PICZ Cold sparing leakage output current Supply threshold cold sparing buffers Voltage/2.5V range Voltage/3.0V range Voltage/3.3V range Voltage/2.5V range Voltage/3.0V range Voltage/3.3V range
Iocs Vcsth
POxxZ POxxZ PO11V PO11V PO11V PO11V5 PO11V5 PO11V5
MH1RT
4110G-AERO-07/03
MH1RT
Table Characteristics
Voltage/2.5V range Voltage/3.0V range Voltage/3.3V range Voltage/2.5V range Voltage/3.0V range Voltage/3.3V range Output short circuit current Iosn Iosp PO11V PO11V PO11V PO11V5 PO11V5 PO11V5 Vdd(Max.), Vout Vouy
PO11V PO11V
tolerant/compliant pull-ups: PRU(#), {1-31} index Ron: where typ, Max., Min. tolerant/compliant pull-downs: PRD(#), {1-31} index Ron: where: typ, Max., Min. 3.3V range, typ, Max., Min. range, typ, Max., Min. 2.5V range, Guaranteed tested. output buffers (1-C) (1-C): 1-C: value: convert n-channel output drive compliant buffers (including cold sparing) 3.3V range (Vcc 4.5V measured 0.4V compliant buffers (including cold sparing) 3.0V range (Vcc 4.5V measured 0.4V compliant buffers (including cold sparing) 2.5V range (Vcc 4.5V measured 0.4V output buffers (1-C) (1-C): 1-C: value: convert n-channel output drive compliant buffers (including cold sparing) 3.3V range (Vcc 4.5V measured 2.4V compliant buffers (including cold sparing) 3.0V range (Vcc 4.5V measured 2.4V compliant buffers (including cold sparing) 2.5V range (Vcc 4.5V measured 2.0V
LVDS Driver Characteristics
Applicable over recommended operating temperature voltage range unless otherwise noted. Table 2.5V LVDS Driver DC/AC Characteristics
Symbol |VOD| |Delta VOD| |Delta VOS| ISA, ISAB Parameter Operating Temperature Supply Voltage Output differential voltage Output voltage Output voltage high Output offset voltage Test Condition Rload Rload Rload Rload Min. 230.7 1224 1108 Max. 446.5 1817 1406 1610 Units Comments Figure Figure Figure Figure
Change |VOD| between Rload Change |VOS| between Rload Output current Output current Drivers shorted ground Drivers shorted together
4110G-AERO-07/03
Table 2.5V LVDS Driver DC/AC Characteristics
Rbias Ibias Max. Clock Tfall Trise Tsk1 Tsk2 Bias resistor Bias static current Maximum operating frequency Clock signal duty cycle Fall time 80-20% Rise time 20-80% Propagation delay Duty cycle skew Channel channel skew (same edge) 2.5V 0.2V Max. frequency Rload Rload Rload Rload Rload 1270 10.2 11.7 1178 1167 2660 Consumption 14.8 Figure Figure Figure chip
MH1RT
4110G-AERO-07/03
MH1RT
Applicable over recommended operating temperature voltage range unless otherwise noted. Table LVDS Driver Characteristics
Symbol |VOD| |Delta VOD| |Delta VOS| ISA, ISAB Rbias Ibias Max. Clock Tfall Trise Tsk1 Tsk2 Parameter Operating Temperature Supply Voltage Output differential voltage Output voltage Output voltage high Output offset voltage Test Condition Rload Rload Rload Rload Min. 1088 12.8 1150 Max. 1775 1358 13.2 13.8 2300 Units Comments Figure Figure Figure Figure chip Consumption 18.6 Figure Figure Figure
Change |VOD| between Rload Change |VOS| between Rload Output current Output current Bias resistor Bias static current Maximum operating frequency Clock signal duty cycle Fall time 80-20% Rise time 20-80% Propagation delay Duty cycle skew Channel channel skew (same edge) Drivers shorted ground Drivers shorted together 0.3V Max. frequency Rload Rload Rload Rload Rload
4110G-AERO-07/03
Applicable over recommended operating temperature voltage range unless otherwise noted. Table 3.3V LVDS Driver Characteristics
Symbol |VOD| |Delta VOD| |Delta VOS| ISA, ISAB Rbias Ibias Max. Clock Tfall Trise Tsk1 Tsk2 Parameter Operating Temperature Supply Voltage Output differential voltage Output voltage Output voltage high Output offset voltage Test Condition Rload Rload Rload Rload Min. 251.4 1071 16.3 1120 Max. 452.2 1731 1323 1527 16.7 14.6 2120 Units Comments Figure Figure Figure Figure chip Consumption 14.8 Figure Figure Figure
Change |VOD| between Rload Change |VOS| between Rload Output current Output current Bias resistor Bias static current Maximum operating frequency Clock signal duty cycle Fall time 80-20% Rise time 20-80% Propagation delay Duty cycle skew Channel channel skew (same edge) Drivers shorted ground Drivers shorted together 3.3V 0.3V Max. frequency Rload Rload Rload Rload Rload
Figure Test Termination Measurements
MH1RT
4110G-AERO-07/03
MH1RT
Figure Rise Fall Measurements
Applicable over recommended operating temperature voltage range unless otherwise noted. Table LVDS Receiver Characteristics
Symbol Vidth Parameter Operating Temperature Supply Voltage Input voltage range Input differential voltage Test Condition Cout 2.5V 0.2V Cout 3.0V 0.3V Cout 3.3V 0.3V Cout Min. -100
Max. 2400 +100
Units
Comments
Tskew
Propagation delay Duty cycle distortion
Table Buffers Characteristics
Symbol COUT CI/O Parameter Capacitance, Input Buffer (die) Capacitance, Output Buffer (die) Capacitance, Bi-Directional Test Condition Typical Units
4110G-AERO-07/03
Testability Techniques
complex designs, involving blocks memory and/or cores, careful attention must given design-for-test techniques. sheer size complex designs number functional vectors that would need created exercise them fully, strongly suggests more efficient techniques. Combinations SCAN paths, multiplexed access memory and/or core blocks, built-in-self-test logic must employed, addition functional test patterns, provide both user Atmel ability test finished product. example highly complex design could include clock management synthesis, microcontroller engine both, SRAM support microcontroller engine, glue logic support interconnectivity each these blocks. design each these blocks must take into consideration fact that manufactured device will tested high performance digital tester. Combinations parametric, functional, structural tests, defined digital testers, should employed create suite manufacturing tests. type block dictates type testability technique employed. will, construction, provide access nodes that functional and/or parametric testing performed. Since digital tester must control clocks during testing Gate Array/Embedded Array, provision must made bypassed. Atmel's PLLs include multiplexing capability just this purpose. addition pins will allow other portions isolated test, without impinging upon normal functionality. similar vein, access microcontroller, DSP, SRAM blocks must provided that controllability observability inputs outputs blocks achieved with minimum amount preconditioning. SRAM blocks need provide access both address data ports that comprehensive memory tests performed. Multiplexing pins provides method providing this accessibility. glue logic designed using full SCAN techniques enhance testability. should noted that, almost these cases, purpose testability technique provide Atmel means assess structural integrity Gate Array/Embedded Array, i.e., sort devices with manufacturing-induced defects. techniques described above should considered supplemental patterns which exercise functionality design anticipated operating modes.
MH1RT
4110G-AERO-07/03
MH1RT
Advanced Packaging
MH1RT Series offered ceramic packages: multi layers quad flat packs (MQFP) based ceramic land grid arrays, called multi layer column grid array (MCGA). Table Packaging Options
Package Type MQFP(2) MCGA(2) Notes: Count 196, 349, (1.27 pitch), pitch)
Contact Atmel local design centers check availability matrix/package combination. Four decks packages.
4110G-AERO-07/03
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Disclaimer: Atmel Corporation makes warranty products, other than those expressly contained Company's standard warranty which detailed Atmel's Terms Conditions located Company's site. Company assumes responsibility errors which appear this document, reserves right change devices specifications detailed herein time without notice, does make commitment update information contained herein. licenses patents other intellectual property Atmel granted Company connection with sale Atmel products, expressly implication. Atmel's products authorized critical components life support devices systems. Atmel Corporation 2003. rights reserved. Atmel combinations thereof registered trademarks Atmel Corporation subsidiaries. Cadence trademark Cadence Design Systems. Design Compiler registered trademark Synopsis Incorporated. Synopsis registered trademark Synopsis Incorporated. Mentor trademark Mentor Graphics. Other terms product names trademarks others.
Printed recycled paper.
4110G-AERO-07/03

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