PRELIMINARY IDT70T3339S DRA.T True Dual-Port memory cells wh

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PRELIMINARY IDT70T3339S DRA.T True Dual-Port memory cells wh

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HIGH-SPEED 2.5V 512K SYNCHRONOUS DUAL-PORT STATIC WITH 3.3V 2.5V INTERFACE
PRELIMINARY IDT70T3339S
DRA.T
True Dual-Port memory cells which allow simultaneous access same memory location High-speed data access Commercial: 3.6ns (166MHz)/4.2ns (133MHz)(max.) Industrial: 4.2ns (133MHz) (max.) Selectable Pipelined Flow-Through output mode Counter enable repeat features Dual chip enables allow depth expansion without additional logic Interrupt Collision Detection Flags Full synchronous operation both ports cycle time, 166MHz operation (12Gbps bandwidth) Fast 3.6ns clock data 1.7ns setup clock 0.5ns hold control, data, address inputs 166MHz
Data input, address, byte enable control registers Self-timed write allows fast cycle time Separate byte controls multiplexed matching compatibility 2.5V (±100mV) power supply core LVTTL compatible, selectable 3.3V (±150mV) 2.5V (±100mV) power supply I/Os control signals each port Industrial temperature range (-40°C +85°C) available 133MHz Available 144-pin Thin Quad Flatpack (TQFP), 208-pin fine pitch Ball Grid Array (fpBGA), 256-pin Ball Grid Array (BGA) Supports JTAG features compliant with IEEE 1149.1 limited count JTAG supported 144-pin TQFP package
.unctional Block Diagram
FT/PIPEL
FT/PIPER
R/WL CE0L CE1L
R/WR CE0R CE1R
Dout0-8_L Dout9-17_L
Dout0-8_R Dout9-17_R
FT/PIPER
FT/PIPEL
512K MEMORY ARRAY
I/O0L I/O17L
Din_L
Din_R
I/O0R I/O17R
CLKL A18L REPEATL ADSL CNTENL A18R
CLKR
Counter/ Address Reg.
ADDR_L
ADDR_R
Counter/ Address Reg.
REPEATR ADSR CNTENR
5652
INTERRUPT COLLISION DETECTION LOGIC
INTL
INTR
JTAG
TRST
.EBRUARY 2002
©2002 Integrated Device Technology, Inc. 5652/1
IDT70T3339S High-Speed 2.5V 512K Dual-Port Synchronous Static
DRAFT Preliminary Industrial Commercial Temperature Ranges
Description:
IDT70T3339 high-speed 512K synchronous DualPort RAM. memory array utilizes Dual-Port memory cells allow simultaneous access address from both ports. Registers control, data, address inputs provide minimal setup hold times. timing latitude provided this approach allows systems designed with very short cycle times. With input data register, IDT70T3339 been optimized applications having unidirectional bidirectional data flow bursts. automatic power down feature, controlled CE1, permits on-chip circuitry each port enter very standby power mode. 70T3339 support operating voltage either 3.3V 2.5V both ports, controllable pins. power supply core device (VDD) 2.5V.
6.42
IDT70T3339S High-Speed 2.5V 512K Dual-Port Synchronous Static
DRAFT Preliminary Industrial Commercial Temperature Ranges
Ordering Information
XXXXX Device Type Power Speed Package Process/ Temperature Range
Blank
Commercial (0°C +70°C) Industrial (-40°C +85°C) 208-pin fpBGA (BF-208) 256-pin (BC-256) 144-pin TQFP (DD-144)
Commercial Only Commercial Industrial
Speed Megahertz
Standard Power
70T3339 9Mbit (512K 18-Bit) Synchronous Dual-Port
5652
DRA.T Preliminary Datasheet: Definition
"PRELIMINARY' datasheets contain descriptions products that early release.
Datasheet Document History:
02/25/02: Initial Datasheet
CORPORATE HEADQUARTERS 2975 Stender Santa Clara, 95054
SALES: 800-345-7015 408-727-5166 fax: 408-492-8674 www.idt.com
Tech Support: 831-754-4613 DualPortHelp@idt.com
logo registered trademark Integrated Device Technology, Inc.
6.42

PRELIMINARY IDT70T3339S DRA.T True Dual-Port memory cells wh

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