Chuck Leuthauser Brett Hanson ABSTRACT well known that temperatur

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Chuck Leuthauser Brett Hanson ABSTRACT well known that temperatur

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IMPROVED MOSFET RELIABILITY THROUGH PACKAGING ENHANCEMENTS
Chuck Leuthauser Brett Hanson
ABSTRACT well known that temperature critical operating state parameter today's electronic industry. Temperature influences device operating state characteristics performance. well, crucial variable estimating electronic devices' lifetime. Most failure mechanisms semiconductor devices accelerated higher operating temperatures. antiquated rule thumb suggests that every rise temperature, failure rate doubles. Also, limiting device temperatures meeting performance criteria. Higher operating temperatures usually degrade device performance, example, reducing gain efficiency increasing leakage currents. MOSFET PACKAGING. Device packaging interface between heat generating semiconductor substrate, ambient used dissipate heat generation during device operation. device package's thermal properties therefore essential, require thermal design considerations ensure that device operates safe operating junction temperatures. Many providers high power discrete devices include derating curves extrapolate device performance elevated temperatures order compensate anticipated operating environment. Steady-state transient thermal analysis often performed empirically analytically optimize thermal transfer characteristics. Most device manufacturers provide thermal resistance rating. following paper discusses common package styles: differences their thermal characteristics implications thereof. package, which contains pedestal that supports beryllium oxide (BeO), been mainstay industry many years, while package been limited bipolar junction transistors (BJT). package will used STMicroelectronics power MOSFETs. justification this decision will axiomatic from following discussion. Figures depict geometry materials package. package consists Oxygen-Free-High-Conductivity (OHFC) Copper (Cu) flange with pedestal upon which disk ceramic attached semiconductor eutecticly mounted BeO. size pedestal limited mechanical mismatch stress which cause ceramic crack during assembly during over temperature range. pedestal diameter mils, while diameter mils. package consists flange with Molybdenum (Mo) base insert, compensate mechanical stresses BeO. attached flange semiconductor eutecticly mounted BeO. size mils mils. properties modeled exactly this analysis since only interested comparing packages approximate size, assumed that die-BeO interface constant both package styles. only intrinsic material property needed steady-state thermal analysis thermal conductivities constituent materials. thermal conductivity values used OHFC 10.1
July 2000
AN1227 APPLICATION NOTE respectively. general, material properties function temperature their functional dependence, although specified here, were included nonlinear thermal analysis. order compare thermal dissipation effectiveness these packages Finite-Element Analysis (FEA) performed solve steady-state temperature distribution under given device power dissipation using evaluation copy ANSYS/Multiphysics software. Since rectangular, axes symmetry were used perform separate, dimensional thermal FEAs. Using these axes symmetry three dimensional problem reduced dimensional problem. worst case results from longest dimension, thus potentially highest thermal resistance, presented this application note. Some assumptions about constraints that force thermal solution include infinitely thin heat source surface fixed temperature bottom flange. hus, boundary conditions required solve Poisson's equation describing steady-state temperature distribution are: fixed flange temperature boundary heat sink (entire bottom); heat flux from which power dissipation fixed same value thermal analysis both packages. This value based nominal device power output efficiency. remainder undefined boundaries were given Neumann (adiabatic) condition. Thus assumptions include: heat source located surface; cooling exclusively through bottom surface; active area rectangular located center surface; power distribution uniform over active area device. Figure Package Style
Figure Package Style
results thermal form temperature distribution contour maps shown figures each package styles. temperature contour maps show that temperature gradient large near concentrated heat source, temperature gradient diminishing lower regions near heat sink expected. However, there several interesting features that suggest package thermal advantage over other. most salient feature that package style lower peak temperature than package under conditions this analysis. also seen that package larger temperature throughout
AN1227 APPLICATION NOTE volume compared package. edge package range while edge package range isotherm that includes edge package constricted pedestal allowed spread heat would naturally occur without pedestal, thus higher temperature. This suggests that conductive thermal dissipation through flange more effective package than package. Another interesting feature results that edge flange does appear have significant heating device's power dissipation. Thus modifying flange would result thermal improvement. Figure Package Temperature
Figure Package Temperature
SD2921 SD2921-10 large 150W DMOS Power FETS that were used verify improvements projected thermal modeling. Both devices same overall mechanical dimensioning represent thermal path differences discussed above. SD2921 uses conventional pedestal package with resultant thermal resistance SD2921-10 uses package improvement thermal resistance (0.45 Both these values were determined InfraRed Imaging resultant reduction junction temperature actually better than model projections which were silicon specific. With typical dissipation Watts case temperature following junction temperatures Mean Time Failure (MTTF) lifetimes compared using metal migration lifetime curve (MTTF refractory barriered gold metallization) drain current Id=5A these devices (Table temperature reduction results about 400% life improvement. Even better improvements realized elevated case temperatures where fall-off device performance characteristics with increased junction temperature begin compound accentuate differences thermal properties.
AN1227 APPLICATION NOTE CONCLUSION summary, large devices where silicon size approaches exceeds conventional pedestal size would benefit increased lifetime reduced temperature/parameter effects from package structure. Since MOSFET sizes larger than equivalents (for same power output level), structure would more appropriate high power MOSFETS.
Information furnished believed accurate reliable. However, STMicroelectronics assumes responsibility consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights STMicroelectronics. Specification mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. STMicroelectronics products authorized critical components life support devices systems without express written approval STMicroelectronics. logo trademark STMicroelectronics 2000 STMicroelectronics Printed Italy rights reserved
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Chuck Leuthauser Brett Hanson ABSTRACT well known that temperatur

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