N-CHANNEL 0.0095 DPAK GATE CHARGE STripFETPOWER MOSFET PRELIMINAR
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STD40NF02L
N-CHANNEL 0.0095 DPAK GATE CHARGE STripFETPOWER MOSFET
PRELIMINARY DATA STD40NF02L
DS(on) 0.0115
TYPICAL RDS(on) 0.0095 TYPICAL OPTIMAL RDS(on) TRADE-OFF CONDUCTION LOSSES REDUCED SWITCHING LOSSES REDUCED
DESCRIPTION This application specific Power Mosfet third generation STMicroelectronics unique "Single Feature SizeTM" strip-based process. resulting transistor shows best trade-off between on-resistance gate charge. When used high side buck regulators, gives best performance terms both conduction switching losses. This extremely important motherboards where fast switching high efficiency paramount importance. APPLICATIONS SPECIFICALLY DESIGNED OPTIMISED HIGH EFFICIENCY CORE DC/DC CONVERTERS
DPAK TO-252 (Suffix "T4")
SUFFIX "T4" ORDERING TAPE REEL
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Drain-source Voltage (VGS Drain- gate Voltage ate-source Voltage Drain Current (continuous) Drain Current (continuous) Drain Current (pulsed) otal Dissipation Derating Factor Storage Temperature Max. Operating Junction Temperature
Value 0.37
Current Limited Package Pulse width limited safe operating area
September 2000
STD40NF02L
THERMAL DATA
-case -amb Thermal Resistance Junction-case Thermal Resistance Junction-ambient Maximum Lead Temperature Soldering Purpose 2.73 62.5
ELECTRICAL CHARACTERISTICS (Tcase unless otherwise specified)
Symbo (BR)DSS IGSS Parameter Drain-source Breakdown Voltage Test ditions Min. Typ. Max. Unit
Rating Zero Gate Voltage Drain Current Rating Gate-body Leakage Current (VDS
=125
Symbo GS(th) DS(on) Parameter Gate Threshold Voltage Static Drain-source Resistance State Drain Current Test ditions Min. Typ. Max. 0.0095 0.0115 0.015 0.019 Unit
ID(o DS(on
DYNAMIC
Symbo Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test ditions ID(o DS(on Min. Typ. 1500 Max. Unit
STD40NF02L
ELECTRICAL CHARACTERISTICS (continued) SWITCHING
Symbo d(on) Parameter Turn-on Delay Rise Time Total Charge Gate-Source Charge Gate-Drain Charge Test ditions (Resistive Load, fig. Min. Typ. Max. Unit
SWITCHING
Symbo d(of Parameter Turn-off Delay Fall Test ditions (Resistive Load, fig. Min. Typ. Max. Unit
SOURCE DRAIN DIODE
Symbo Parameter Source-drain Current Source-drain Current (pulsed) Forward Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current di/dt A/µs (see test circuit, fig. Test ditions Min. Typ. Max. Unit
Pulsed: Pulse duration duty cycle Pulse width limited safe operating area
STD40NF02L
Fig. Unclamped Inductive Load Test Circuit Fig. Unclamped Inductive Waveform
Fig. Switching Times Test Circuits Resistive Load
Fig. Gate Charge test Circuit
Fig. Test Circuit Inductive Load Switching Diode Recovery Times
STD40NF02L
TO-252 (DPAK) MECHANICAL DATA
MIN. 0.03 0.64 0.45 0.48 9.35 0.023 TYP. MAX. 0.23 10.1 MIN. 0.086 0.035 0.001 0.025 0.204 0.017 0.019 0.236 0.252 0.173 0.368 0.031 0.039 inch TYP. MAX. 0.094 0.043 0.009 0.035 0.212 0.023 0.023 0.244 0.260 0.181 0.397
DIM.
DETAIL
DETAIL
0068772-B
STD40NF02L
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