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In-System Programming Design Guidelines ispJTAG Devices
In-system programming (ISPTM) often been billed direct replacement configuring device through programmer. idea that devices simply placed board, connected through cable programmed attractive alternative many newer packages such Thin Quad Flat Pack (TQFP) Ball Grid Array (BGA). When devices placed board, however, care must taken design that board loading clock lines, buffering, termination signals. This true signals well datapath control signals generated used device. Therefore, necessary follow some general guidelines when designing in-system programmability into board. ideal setup in-system programming includes buffers both parallel port connection short cable board configured, addition termination lines which parallel such TCK. When there only devices chain, buffer inside ispDOWNLOAD® cable sufficient. following recommendations will make smoother experience.
Device-specific Connections
addition good layout practices, including decoupling capacitors between ground each device minimizing trace lengths wherever possible, additional care must taken ensure programming interface signal integrity. Many Lattice devices include some optional pins (ispEN, BSCAN, ENABLE, EPEN BSCAN/ispEN) that enable IEEE 1149.1 controller. Some devices support optional asynchronous reset pin, TRST. Additionally, available some devices tri-state functional pins. following section provides summary these optional pins. Unless using some outside control, most these optional pins used typical board. typical wiring configuration shown each device family. ispLSI® 2000VE, 2000VL 2000E devices, filtering capacitor (.01µF) must provided between ispEN signal ground when ispEN BSCAN device connected ispEN signal programming connector. This filtering capacitor must located close possible connector PCB, order filter noise during programming. ispEN signal driven while programming. Without capacitor, noise couple into ispEN signal during programming could interrupt programming sequence.
ispLSI 1000EA Family
pins affect controller operation shown Figure Figure ispLSI 1000EA Family
4-wire ispJTAG Programming Interface
ispLSI 1000EA
www.latticesemi.com
ispguide_07
Lattice Semiconductor ispLSI 2000VE, 2000VL 2000E Families
In-System Programming Design Guidelines ispJTAG Devices
strict boundary scan compliance, BSCAN must low. When this high, controller pins disabled functional dedicated inputs selected. Since this requires some external control prevent contention between functional boundary scan signals, recommended reserve these pins boundary scan. Figure shows recommended connection. Figure ispLSI 2000VE, 2000VL 2000E Families
4-wire ispJTAG Programming Interface
BSCAN
ispLSI 2000VE ispLSI 2000VL ispLSI 2000E
ispLSI 5000V Family
will disable functional pins when driven low. Unless using boundary scan tester hardware software that controls TOE, disable this pin. While programming mode EXTEST loaded, pins controlled boundary scan test registers affect. Figure shows tied VCC. Figure ispLSI 5000V Family
4-wire ispJTAG Programming Interface
ispLSI 5000V
ispLSI 8000 Family
strict boundary scan compliance, BSCAN/ispEN must high. When this driven low, controller pins disabled, device enters programming mode pins tri-state. will disable functional pins when driven low. Unless using boundary scan tester hardware software that controls TOE, disable this pin. While programming mode EXTEST loaded, pins controlled boundary scan test registers effect. Figure shows BSCAN/ispEN tied VCC.
Lattice Semiconductor
Figure ispLSI 8000 Family
4-wire ispJTAG Programming Interface
In-System Programming Design Guidelines ispJTAG Devices
BSCAN/ispEN BSCAN/ispEN
ispLSI 8000
ispLSI 8000V ispGDXV Families
strict boundary scan compliance, EPEN must high. When this driven low, controller pins disabled. EPEN used chip select allow pins connected directly bus. will disable functional pins when driven low. Unless using boundary scan tester hardware software that controls TOE, disable this pin. While programming mode EXTEST loaded, pins controlled boundary scan test registers affect. Figure shows EPEN tied VCC. Figure ispLSI 8000V ispGDXV Families
4-wire ispJTAG Programming Interface
EPEN
ispLSI 8000V ispGDXV
ispGDX® Family
strict boundary scan compliance, BSCAN/ispEN must high. When this driven low, controller pins disabled, device enters programming mode pins tri-state. will disable functional pins when driven low. Unless using boundary scan tester hardware software that controls TOE, disable this pin. Figure shows BSCAN/ispEN tied VCC.
Lattice Semiconductor
Figure ispGDX Family
4-wire ispJTAG Programming Interface
In-System Programming Design Guidelines ispJTAG Devices
EPEN
ispGDX
ispMACH 4000B/C, 5000VG, ispGAL®22LV10
pins affect controller operation shown Figure Figure ispMACH 4000B/C, 5000VG, ispGAL22LV10
4-wire ispJTAG Programming Interface
ispMACH 4000B/C, 4000B 5000VG ispGAL22LV10
ispMACH4A Family
TRST ENABLE pins optional JTAG pins only found some ispMACH devices, listed Table strict boundary scan compliance, ENABLE must low. When high, program verify instructions become inactive. designs, recommended that TRST tied high keep controller from being inadvertently reset. ispMACH device supports TRST TRST used, Lattice recommends that 4.7K resistor should connected between TRST signal ground. resistor will hold controller reset until TRST signal overdriven high signal. Adding resistor will increase noise immunity power-up.
Lattice Semiconductor
Figure ispMACH
4-wire ispJTAG Programming Interface
In-System Programming Design Guidelines ispJTAG Devices
TRST ENABLE
ispMACH
Table ispMACH JTAG Programming Support
Device ispMACH (3,5)-32/32 ispMACH (3,5)-64/32 ispMACH 4A3-64/64 ispMACH (3,5)-96/48 ispMACH (3,5)-128/64 ispMACH (3,5)-192/96 Programming Pins Supported TDI, TDO, TMS, TDI, TDO, TMS, TDI, TMS, TCK, TRST, ENABLE TDI, TDO, TMS, TDI, TMS, TCK, TRST, ENABLE TDI, TDO, TMS,
ispMACH (3,5)-256/128 TDI, TMS, TCK, TRST, ENABLE ispMACH 4A3-256/160 TDI, TMS, TCK, TRST, ENABLE ispMACH 4A3-256/192 ispMACH 4A3-384/160 ispMACH 4A3-384/192 ispMACH 4A3-512/160 ispMACH 4A3-512/192 ispMACH 4A3-512/256 TDI, TMS, TDI, TMS, TDI, TDO, TMS, TDI, TMS, TDI, TDO, TMS, TDI, TDO, TMS,
MACH® Devices
MACH devices standard IEEE-1149.1 test access port (TAP) programming interface. comprised four standard pins: TCK, TMS, TDO. Certain devices also include optional asynchronous reset pin, TRST, program enable pin, ENABLE. This configuration found MACH355, MACH445, MACH465, MACH4-128/64, MACH4-192/96 MACH4-256/128. programming environment, only necessary connect four standard pins. With six-pin configuration, while ispVMSystem software supports TRST ENABLE pin, requirement. designs, TRST should permanently tied ENABLE should tied ground. TRST used, should tied ground through 4.7K resistor improve noise immunity. Making connections recommended above MACH devices will simplify layout board will eliminate need additional buffers those signals. TRST used, care should taken minimize crosstalk with other signals. Additionally, TRST should tied ground through 4.7K resistor. This will
Lattice Semiconductor
In-System Programming Design Guidelines ispJTAG Devices
keep device reset until that signal overdriven programming hardware. This increases noise immunity device during power-up situations.
Connections After Programming
After programming testing been completed, question often arises, "What should done with port signals?" requirements IEEE1149.1 standard JTAG port that both have internal pull-up resistors. ensuring that there pin, inadvertent clocking will cause JTAG state machine leave reset state. During power-up, inadvertent clocking cause 1149.1 state machine instruction register come undesirable state. increase noise immunity during power-up, following recommendation made: 4.7K pull-up resistor should used signal 4.7K pull-down resistor signal board. number devices connected TCK/TMS signals increases, pull-up pull-down resistor values need adjusted more internal pull-up resistors affecting those signals. chain with devices, pull-down resistor value should
Buffering
stated earlier, ideal scheme buffering includes buffers both ends cable buffers each group five eight devices programming chain. This case does cover situations, however. example, design with only devices chain, question arises, buffer needed?" recommendation buffering follows: Buffering needed TCK, TMS, TRST lines. should also used signal into board signal board. there fewer than five devices programming chain, additional buffers required, recommended. there five more devices, buffering recommended, well separate buffer each group five eight devices. When using buffer, trace lengths should balanced minimize signal skew. pull-down resistor required pull-up resistor required affter output driver each buffer. ispDOWNLOAD cable should used when available. length this cable should longer than feet length should minimized when possible. TCK, TMS, optional signals mentioned earlier (TRST, TOE, ispEN, BSCAN, ENABLE, EPEN BSCAN/ ispEN) parallel 1149.1 devices board. Therefore, these signals will tend present larger load source driving them. many cases, this ispDOWNLOAD cable connected parallel port. This buffered cable longer than feet length. transmission line effects both cable traces board cause recommendation additional buffering board itself. signals each device daisy chained where device will feed next. more devices connected given signal, greater loading that signal. Therefore, necessary buffer heavily loaded signals split loading given signal that there smaller load. This load should also balanced, both terms number devices driven that signal, lengths traces each device, that signal skew does become issue. There several buffers suitable programming chain. These include 74LS244 74LS367. When selecting buffer, there parameters watch for. first output edge rate. fast, reflections become concern. second input voltage requirements. Certain buffers such 74HC244 have specifications that function Vcc. mixed-signal environment, where there 3.3V supply board, buffer should tied lower supplies reduce VIH. correct buffers board long either solve existing programming problems prevent them. only consideration, however.
Lattice Semiconductor
In-System Programming Design Guidelines ispJTAG Devices
Termination Signals
high-speed board system design, termination signals often required ensure reliable operation. same true environment. Termination correct board layout techniques long develop reliable programming setup. Some effects terminating signal include negative overshoot, where signal will glitch negative voltage very short period time ns), double clocking, where clock signal have negative glitch rising edge. Both situations devastating environment. prevent such possibilities, following steps should taken. Avoid using buffers with extremely fast edge rates such 74F244. Terminate signal either using balanced termination network main trunk signal using resistors series with each signal connected
When Buffers Aren't Used
While buffers recommended designs, they always practical smaller design where there only devices programming chain. situation such this, there precautions that taken minimize problems. there noise problems, they often cleaned using simple filter both signals signal into first device. Additionally, devices always have enough drive capability their pins either pull pull down signal feet away parallel port. this situation following measure taken. 4.7K pull-up pull-down resistor necessary signal last device programming chain reliably switch signal into parallel port. This should only necessary buffers being included part board design.
Mixed Voltage Programming Chains
Combining devices with different voltages into programming chain challenge. Devices that have 3.3V combined with problem because JTAG pins level signals. 3.3V devices combined order. When 2.5V 1.8V devices added onto board with 3.3V devices, voltage levels programming pins compatible. order have combination 1.8V, 2.5V, 3.3V devices, JTAG pins will need referenced common voltage, such 3.3V. Some devices have VCCJ which used reference JTAG pins common voltage supplied VCCJ. Other devices that support VCCJ will have have JTAG voltages translated using translator chip. translator chip such 74LVC07A take 1.8V inputs produce 3.3V outputs. When mixing programming chains, caution must used protect integrity programming chain reduce programming errors.
Debugging Environment
above guidelines followed, programming should smooth reliable. Problems that arise might result improper settings ispVMSystem software improper device configuration. Errors most commonly occur when download software checking structure programming chain reading device IDCODEs Lattice devices chain checking single from other devices. error occurs following could wrong should considered: errors returned either `0,' following could wrong: programming/JTAG connections incorrect should checked. -The programming chain been incorrectly specified. Check both order devices chain number instruction register bits each non-Lattice devices. errors returned combination they vary, lines either sufficiently terminated buffered. Refer guidelines above.
Lattice Semiconductor
In-System Programming Design Guidelines ispJTAG Devices
States Before During Programming
devices shipped from Lattice with fuse pattern that will pins high-impedance state prior programming. This configuration prevents devices from driving unwanted signals other devices system before they properly programmed. During programming cycle, Lattice devices default having their pins tri-stated. most situations, this should cause problems. state needs modified during programming cycle, ispVM System software program cell with ispVM System on-line help more information.
Conclusion
design guidelines debug techniques presented here will lead reliable design programming flow. offers many advantages over traditional programming techniques, additional considerations must taken into account during implementation, such proper buffering termination. This will ensure effective productive experience.
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