Multi-Channel Controller User's Guide August 2003 ipug11_01
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Multi-Channel Controller
User's Guide
August 2003 ipug11_01
Lattice Semiconductor
Multi-Channel Controller User's Guide
Introduction
This document contains technical information about Lattice Multi-Channel Direct Memory Access (MCDMA) Controller. This MCDMA core comes with following documentation files: Data sheet Gate level netlist simulation model Template core testbench instantiation
Core Specification
Features
Selectable 8237 mode Configurable independent channels non-8237 mode Configurable data width 16-, 64-bits non-8237 mode Configurable address width 16-, 32-bits non-8237 mode Configurable Word Count register width non-8237 mode Independent auto-initialization channels Memory-to-memory transfers single, block, demand transfer mode Memory block initialization Software requests
General Description
Multi-Channel Direct Memory Access (MCDMA) Controller designed improve microprocessor system performance allowing external devices transfer information directly from system memory vice versa. Memory-to-memory transfer capability also supported. MCDMA Controller core supports modes operation: 8237 non-8237 modes. When 8237 mode selected, core functionally compatible with Intel 8237A Controller device with variations. These variations listed Compatibility Differences with 8237 Intel Device section this document. 8237 non-8237 modes detailed later this document provide clearer description each mode. Differences Between 8237 Mode Non-8237 Mode MCDMA While 8237 non-8237 modes share some commonality, they also have differences. Table shows differences between modes.
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Multi-Channel Controller User's Guide
Table Feature Differences Between 8237 Non-8237 Modes
Feature
Multiple independent channels Parameterized address Parameterized data Parameterized word count register Auto-initialization Compressed timing Cascade mode transfer configuration each channel Priority request mode request active state Software reset Fixed bits Fixed bits Fixed bits Supported Supported supported supported Rotating/fixed priority mode High/low Supported
8237 Mode
Non-8237 Mode
1-16 bits bits bits Supported supported supported Supported Fixed priority mode High supported
Compatibility Differences with 8237 Intel Device When MCDMA core configured 8237 mode, differs from Intel 8237A core following ways: bi-directional ports split into separate input output ports. MCDMA does support cascade mode operation. latch that holds upper byte address internal address strobe signal ADSTB generated. slave's write cycle MCDMA core synchronous.
Block Diagram
Figure shows block diagram this core. Figure Block Diagram MCDMA Core
cs_n eopin_n reset iorin_n iowin_n ready hlda ain[AIN_BUS_WIDTH-1:0] aout[ADDR_BUS_WIDTH-1:0] hreq iorout_n iowout_n
Interface State Machine
memr_n memw_n eopout_n
dbin[DATA_BUS_WIDTH-1:0]
Register Block Priority Request Encoder
dbout[DATA_BUS_WIDTH-1:0]
dreq[N-1:0]
dack[N-1:0]
Number channels
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Multi-Channel Controller User's Guide
Signal Descriptions
Table shows input output ports MCDMA core that apply both 8237 non-8237 modes. Table Signal Definitions MCDMA Controller
Port Name cs_n reset Type Input Input Input Active State Rising Edge High Description Clock. This signal controls synchronizes operations MCDMA. Chip Select. This active signal used select MCDMA. Reset. This active high signal that clears internal registers. After reset, device placed Idle state requests masked. Ready. This active high signal used extend memory read write pulses from MCDMA. This most often used accommodate slow memories. Hold Acknowledge. This active high signal generated indicates relinquished control system buses. Process Input. This active input permits external termination current service. Read Input. This active signal when asserted along with cs_n. Thus, permits read internal registers MCDMA. Write Input. This active signal. When asserted along with cs_n, permits write into internal registers MCDMA. Address. This signal selects internal registers. 8237 mode, bits wide. non-8237 mode, width depends number channels selected. Data Input. writes internal registers through this data bus. Request. These programmable parity signals asynchronous signals generated peripherals requesting service. device reset initializes dreq active high. 8237 mode, these parity signals programmable active high low. non-8237, these signals always active high. Hold Request. This active high signal sent request control over system bus. Process Out. This active signal indicates normal termination service. Read Output. This active signal used access data from peripheral during Write transfer. Data Output. This contains value internal register when read CPU. write-to-memory phase memory-to-memory operation, dbout data transmits data from temporary register. Write Output. This active signal used load data peripheral during Read transfer. Memory Write. This active signal used indicate that data being written selected memory location during Write memory-to-memory transfer. Memory Read. This active signal used indicate that data being read from selected memory location during Read memory-to-memory transfer.
ready
Input
High
hlda
Input
High
eopin_n iorin_n
Input Input
iowin_n
Input
[AIN_BUS_WIDTH-1:0]
Input
dbin [DATA_BUS_WIDTH-1:0] dreq[N-1:0]
Input Input
High/Low (8237) High (Non-8237)
hreq eopout_n iorout_n dbout [DATA_BUS_WIDTH-1:0]
Output Output Output Output
High
iowout_n memw_n
Output Output
memr_n
Output
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Multi-Channel Controller User's Guide
Table Signal Definitions MCDMA Controller (Continued)
Port Name Type Output Active State High Description Address Enable. This active high signal enables 8-bit latch that contains upper address bits onto system address bus. Address Output. These lines enabled only during active transfer contain memory address. Acknowledge. This signal used notify requesting peripheral that been granted cycle. polarity this signal programmable. device reset initializes dack signals active low.
aout [ADDR_BUS_WIDTH-1:0] dack[N-1:0]
Output Output
High/Low
Note: number channels
Parameter Descriptions
Table lists parameters used configure MCDMA core. values these parameters must prior functional verification. parameters parenthesis ones generated manager tool. Table MCDMA Parameters
Parameter Mode (MODE_8237) Number Channel (NUM_CHANNELS) Data Width (DATA_BUS_WIDTH) Address Width (ADDR_BUS_WIDTH) Description Defines mode. TRUE, will 8237 mode, otherwise will non-8237 mode. Sets number channels. 8237 mode fixed channels. 8237 channels Sets size data buses temporary register. Sets size output address. 8237 mode, sets size current base address register. non-8237 mode, sets size source address register Sets size Word Count Register. Value automatically based number channels parameter (NUM_CHANNELS Supported Values TRUE/FALSE (8237) 1-16 (non 8237) (8237) 8/16/32/64 (non 8237) (8237) 16/24/32 (non 8237)
Word Count Width (WORD_COUNT_WIDTH) Internal Address Width (AIN_BUS_WIDTH)
(8237) 8/16/24/32 (non 8237) (8237) when (non 8237) when (non 8237) when (non 8237) when (non 8237) when (non 8237)
Functional Description
MCDMA contains three basic blocks control logic: Interface (Data Control Blocks), State Machine, Priority Request Encoder
Interface Control
This explanation applies mainly non-8237 mode because most programmability lies this mode. However, concepts also applicable 8237 mode. Interface Control block first decodes bus. then generates enable signals selected registers subset selected registers when byte enables present during write cycle. When registers read, provides select signal multiplexer that routes appropriate register contents onto data bus.
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Multi-Channel Controller User's Guide
Interface Data block contains configuration registers. includes routing logic required transfer either selected register's contents (during register read cycle) temporary register contents (during memory write cycle memory-to-memory transfer).
Finite State Machine
(Finite State Machine) module initiates data transfers generates control signals various transfer modes. also generates address address-enable signals (aen). exchanges signals with interface block priority encoder block. state machine 8237 mode similar non-8237 mode except additional branches 8237 mode that incorporate: Illegal memory transfer mode bits Compressed timing mode Operation When software hardware request received found valid (having passed polarity, mask mode checks), (Idle) state transmits request signal, hreq transitions waits hlda signal. request drops (dreq de-asserted) mode register request hand cascade mode (unsupported), returns (idle). Otherwise, remains Once request acknowledged assertion hlda signal, transitions S1/S11 synonymous). also determines transfer type based Command Mode register that received from interface. memory-to-memory transfer enabled, transitions through states S12, S13, S14, S21, S22, S24. next transfer should continue same request, path from repeated. memory-to-I/O I/O-to-memory enabled, goes through states (eliminated 8237's compressed timing mode), transfer continues, state machine repeats loop from through This goes until Word Count register gets overflow termination from external input occurs. External inputs that terminate transfer includes eopin_n hlda drop request drop during demand transfer. (Note: case non-demand transfer, request dropped after dack received.). eopout_n signal generated falling clock edge transfer. transfer read/write signals generated falling edge clock. state machine described Figure "input signals" refer signals that state machine samples. These signals affect state machine's transition logic. "Output signals" refer signals that will asserted deasserted (transition) while that state.
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Multi-Channel Controller User's Guide
Figure MCDMA Finite State Machine 8237 Non-8237 Modes
Request Dropped Illegal Mode
LAST_TRAN/ SINGLE_TRAN Termination
HDLA
Illegal Mode (8237 only) LAST_TRAN/ SINGLE_TRAN Termination
LAST_TRAN MEM-MEM Ready (NR) Write Phase Read Phase S1/S11 I/O-MEM
Another Transfer
Compressed (8237 only)
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Table State Descriptions
State Idle State
Multi-Channel Controller User's Guide
Description Upon reset, state machine enters idle state, program core's internal registers while this state. device stays this state until unmasked request detected; which point state machine asserts hreq signal then transitions state While state outputs state machine their inactive states.
Input Signals: hardware reset, software reset (only 8237 mode), unmasked dreq signal Asserted Output Signals: hreq Acquire State Possible State Transitions: device stays this state until hlda signal from sampled asserted. internal registers still programmed while this state. Once state machine samples asserts hlda signal, transitions state regular I/O-to-memory memory-to-I/O transfers. memory-tomemory transfers, state machine transitions state S11. criteria detecting memory-to-memory transfer different 8237 non-8237 modes. 8237 Mode: this mode, memory-to-memory transfer detected memorytransfer enable Command register dreq[0] signal asserted. dackout signal generated priority encoder used check Channel highest priority that time. priority scheme will described more priority request encoder section. Non-8237 Mode: this mode, memory-to-memory transfer detected zero current channel's mode register set. current channel's dreq signal de-asserted this state other requests pending, state machine transitions state other requests pending dreq signal remains asserted, state transitions either S11. Input Signals: hlda, command[0] mode[0], dackout Asserted Output Signals: hreq Memory-to-Memory Read Transfer State Possible State Transitions: This first state memory-to-memory transfer. absence dack signal characterizes this transfer. signal asserted. 8237 mode, address from Channel current address register placed address bus. non-8237 mode, contents source address register placed address bus. memr_n memw_n signals de-asserted. During each eight states memory-to-memory transfer, state machine responds external eopin_n signal stops transfer service soon current cycle completed. state machine transitions state S12. Input Signals: eopin_n Asserted Output Signals: aen, address Memory-to-Memory Read Transfer State Possible State Transitions: This second state memory-to-memory transfer. memr_n signal asserted. state transitions state S13. Input Signals: eopin_n Asserted Output Signals: memr_n, address Possible State Transitions:
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Table State Descriptions (Continued)
State Memory-to-Memory Read Transfer State Three
Multi-Channel Controller User's Guide
Description This third state memory-to-memory transfer. state machine samples ready signal stays this state long asserted. machine transitions state when ready signal de-asserted.
Input Signals: eopin_n, ready Asserted Output Signals: memr_n, address Memory-to-Memory Read Transfer State Four Possible State Transitions: S13, This fourth stage memory-to-memory transfer. state machine deasserts memr_n signal asserts enable signal flop incoming data into temporary register. state machine transitions state S21, which first state memory-to-memory write transfer stage. Input Signals: eopin_n Asserted Output Signals: none Memory-to-Memory Write Transfer State Possible State Transitions: This fifth stage memory-to-memory transfer mode. 8237 mode, content current address register Channel address bus. non-8237 mode, content destination address register channel being serviced address bus. memr_n memw_n signals de-asserted. state machine transitions state S22. Input Signals: eopin_n Asserted Output Signals: address Memory-to-Memory Write Transfer State Possible State Transitions: This fifth state memory-to-memory transfer. state transitions state S23. Input Signals: eopin_n Asserted Output Signals: address Memory-to-Memory Write Transfer State Three Possible State Transitions: This seventh state memory-to-memory transfer. memw_n signal asserted, content temporary register placed data bus. state machine samples ready signal stays this state long asserted. Then machine transitions state S24. Input Signals: eopin_n, ready Output Signals: memw_n Possible State Transitions: S23,
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Table State Descriptions (Continued)
State Memory-to-Memory Write transfer state four
Multi-Channel Controller User's Guide
Description This eighth final stage memory-to-memory transfer. state machine de-asserts memw_n signal. 8237 mode, Channel current word register decremented. non-8237 mode, word count register channel being serviced decremented. counter rolls over from 0xFFFF 0x0000, eopout_n signal asserted state machine transitions state Otherwise, state machine transitions state starts memoryto-memory transfer.
Input Signals: eopin_n Asserted Output Signals: eopout_n case counter rolls over) Possible State Transitions: Active State This first state transfer. signal asserted this state while valid address placed address bus. dreq continues asserted, state machine transitions state dreq de-asserted, state machine transitions state requests must held active until dack signal asserted. Input Signals: dreq Asserted Output Signals: aen, address Active state Possible State Transitions: This second state transfer. dack signal asserted. dreq signal does need held asserted after this state block single transfer mode selected. memr_n iorout_n asserted depending direction transfer. 8237 Mode: memw_n iowout_n asserted extended write option selected command register. state machine will skip state transition state compressed timing option selected. This will result both read write pulses being asserted just single cycle. Non-8237 Mode: memw_n iowout_n asserted, state machine transitions state While state state machine will terminate block demand transfer eopin_n signal sampled asserted. Input Signals: eopin_n, dreq Asserted Output Signals: dack, memw_n, memr_n, iorout_n, iowout_n Possible State Transitions: Active state three This third state transfer. 8237 mode, memw_n iowout_n signal asserted extended write selected. state machine sensitive eopin_n dreq signals demand transfers. state machine transitions state when ready signal sampled de-asserted. machine stays state long ready sampled asserted. Input Signals: eopin_n, dreq, ready Asserted Output Signals: memw_n, iowout_n Possible State Transitions:
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Table State Descriptions (Continued)
State Active state four
Multi-Channel Controller User's Guide
Description This last stage transfer. memw_n iowout_n signal deasserted, depends operation (I/O-to-memory memory-to-I/O). same thing happens memr_n iorout_n signal only them being deasserted. eopout_n signal asserted current word register rolls over from 0xFFFF 0x0000. This causes state machine transition state block demand transfer mode selected, counter rolled over, hasn't satisfied transfer complete-conditions, state machine transitions state where transfers will continue. This next state depends upon mode operation.
8237 Mode: state machine transitions state long higher order address remains same. higher order address transfer changes, state machine transitions state enable external latch update latched value. Non-8237 Mode: state machine transitions state Input Signals: eopin_n Asserted Output signals: eopout_n Compressed Timing Mode Possible State Transitions: This feature only available 8237 mode MCDMA. purpose this mode allow MCDMA achieve greater throughput compressing memory-toI/O I/O-to-memory) transfer time clock cycles. this mode, state removed from state machine. This causes read pulse-width equal write pulse-width. Thus, transfer only state change address state perform read/write operation.
Priority Request Encoder
This block prioritizes request asserts dack signal winning request. 8237 mode, arbitrating scheme user programmable available either fixed priority rotating priority mode. non8237 operation, arbitrating scheme restricted fixed priority mode. fixed priority mode, dreq[0] highest priority dreq[n] lowest priority. 8237 mode, (channel number) fixed while non-8237 mode, user selectable 16). rotating priority mode assigns lowest priority channel that been serviced most recently. This mode ensures that devices will serviced fairly prevents channel from monopolizing system. maximum wait time channel serviced time taken service other channels. main function this block generate dack[x] signal. Each channel associated priority register that indicates channel's priority. fixed priority mode, values these registers will never change, while rotating priority mode, their values change every time channel serviced.
Operation
non-8237 mode, each channel programmed perform operation between memory locations from I/O-to-memory. Each channel dedicated source address register that holds address targeted read memory location destination address register, which points targeted write memory location. Memory locations addressable, locations addressable. source address register non8237 mode holds memory location address during transfers between device memory.
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Multi-Channel Controller User's Guide
functionality core non-8237 mode very similar that 8237 mode. However, modes have totally different sets programmable control registers. This increases programmability features non-8237 mode. Some features available only non-8237 mode are: Multiple channels Configurable channels transfers between memory-and-memory I/O-and-memory Parameterized address output data width Parameterized word-count register microprocessor programs number registers ensure controller functions properly. internal registers accessed when cs_n signal asserted address register placed bus. When iowin_n signal low, registers over written with data dbin bus. When iorin_n signal asserted, registers read their contents placed dbout bus. least significant eight bits data access internal registers irrespective data width. prevent erroneous behavior, registers should programmed only when controller Idle State (SI) before receives hlda signal from microprocessor. adhering these rules will cause controller function non-deterministic way. registers visible microprocessor different 8237 non-8237 modes. MCDMA controller core fully synchronous machine that runs positive edge clock. However, request signals, dreq[N-1:0], asynchronous with respect clock. These signals have synchronized within core.
Initialization
Once Command Mode registers programmed controller enabled, transfers initiated either asserting unmasked channel's dreq signal requesting programming request register. internal registers core accessible during idle state (SI) when channel requesting service transfers progress. core operates cycles: Idle Active. core remains idle cycle long performing transfers none unmasked channels have pending request. this state, microprocessor program device. Once unmasked channel requests service, device asserts hreq signal take control enters first active cycle state device still programmed state until receives hlda signal from arbiter. transfers between memory I/O, active cycles from states through When memory-to-memory transfers performed, active cycles through states S11, S12, S13, memory read operation states S21, S22, S23, memory write operation. Wait states introduced whenever slave device ready transfer.
MCDMA Transfer Modes
When MCDMA active cycle, service takes place following three modes: Single Transfer Mode: single transfer mode, device programmed make transfer only. Following each transfer, Word Count decrements address decrements increment, depending what selected Mode register. recognized, dreq signal must held active until dack becomes active. dreq held active throughout single transfer, hreq goes inactive releases system. After transfer, hreq will active again. When controller receives hlda, another single transfer will performed. Block Transfer Mode: block transfer mode, dreq signals device continue making transfers during service until terminal count encountered (generation eopout_n).This occurs when word count goes 0xFFFF, external Process (eopin_n) encountered. dreq signal must held active until dack becomes active. Auto-initialization occurs service channel been programmed
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Demand Transfer Mode: demand transfer mode, device programmed continue making transfers until Terminal Count external eopin_n encountered until dreq goes inactive. Thus, transfers continue until device exhausted data capacity. After device chance catch service reestablished dreq.
Timing Diagram
Figure illustrates waveform write operation into internal registers MCDMA core. Clock edges indicate point where data written into registers. Clock edges indicate backto-back write operation into same register. iorin_n signal held high during entire write operation. Figure Processor Write Timing Waveform
Clock
cs_n iowin_n
dbin
Figure shows processor read timing waveform. Data available following clock edge after cs_n iorin_n asserted. Clock edges indicate edges which data valid. Figure Processor Read Timing Waveform
Clock
cs_n
iorin_n
dbout
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Figure shows timing waveform words transfer. Figure Word Transfer Timing Waveform
Clock
dreq
hreq
hlda
aout
Valid Address
Valid Address
dack
iorout_n/memr_n
iowout_n/memw_n Note Note This timing diagram demonstrates extended write operation. 8237 mode, when normal write operation selected, iowout_n memw_n asserted clock cycle later. compressed timing selected, state bypassed, making read write pulses equal width. This only applicable 8237 mode. iowout_n memw_n signals generated falling clock edge. This ensures address held least half cycle after rising edge write signal.
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Register Descriptions
8237 non-8237 modes MCDMA Controller have different types number internal registers. 8237 mode types internal registers that visible microprocessor while non-8237 mode seven types internal registers that visible microprocessor.
8237 Mode Internal Registers
Table Internal Registers 8237 Mode
Name Base Address Registers Base Word Count Registers Current Address Registers Current Word Count Registers Command Register Status Register Temporary Register Mode Register Mask register Request Register Size Bits Number Registers
Current Address Register This register only available 8237 mode. Each four channels -bit wide Current Address Register that holds value address used during transfers. address automatically incremented decremented after each transfer. microprocessor loads Current Address Register simultaneously with Base Address Register. Auto-Initialization enabled, MCDMA reloads base address value cycle. This register written consecutive cycles after clearing byte pointer. Current Word Count Register This register only available 8237 mode. Each channel 16-bit Current Word Count register that determines number transfers performed. actual number transfers more than value programmed into this register. Current Word Count decremented after each transfer. Auto-Initialization enabled, value Base Word Count register reloaded service. When value register goes from zero 0xFFFF, terminal count (eopout_n) signal generated. Auto-Initialization enabled, this register count 0xFFFF service. Base Address Register This register only available 8237 mode. Each channel 16-bit Base Address Register. This register stores starting address transfer. idle state program condition, microprocessor simultaneously writes Base Address register Current Address register. microprocessor cannot read this register. Base Word Count Register This register available only 8237 mode. Each channel 16-bit Base Word Count register that stores starting word count transfers. During Auto-Initialization, this value used restore current word count register. microprocessor cannot read this register. Command Register This register controls operation core. 8237 mode, this register bits wide. non-8237 mode, bits wide. When state idle, microprocessor programs this register. reset master clear clears register. Table lists function this register.
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Mode Register Each channel 6-bit wide register. During write operation microprocessor when MCDMA idle state, least significant bits (bit data determine which channel mode register being accessed. reset master clear clears mode registers. Table lists format mode register 8237 mode. Mask Register This register only visible 8237 mode. Each channel associated with that used mask hardware request (disable incoming dreq). four bits this register accessed once, program each bits separately. Each mask when associated channel produces eopout_n signal. reset master clear sets four bits masks channels. Table Table list mask register format 8237 mode. Request Register This register only visible 8237 mode. request register allows software requests. values mask register mask hardware request (dreq). Software requests generated from request register nonmaskable. Individual bits this register accessed with channel number supplied least significant bits data bus. reset master clear clears this register. channel must block mode order make software request. Table lists request register format 8237 Mode. Status Register This register only available 8237 mode. microprocessor read status register, which contains information about status device. This information includes which channels have completed their service which channels have request pending. Status Register reset upon hardware reset master clear. Bits through which indicate which channel reached Terminal Count, cleared every time Status register read. Bits through when their corresponding channel requesting service. Table shows status register format. Temporary Register This register holds data during memory-to-memory transfers. reset master clear command clears this register. microprocessor read this register 8237 mode while MCDMA idle state. This register yields last data transferred during most recent memory-to-memory transfer. Table Command Register 8237 Mode
Description Memory-to-memory disable Memory-to-memory enable Channel address hold disable Channel address hold enable bit0 Controller enable Controller disable Normal timing Compressed timing bit0 Fixed Priority Rotating Priority Late Write Extended Write bit3 dreq active high dreg active dack active dack active high
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Table Mode Register 8237 Mode
Multi-Channel Controller User's Guide
Description Channel select Channel select Channel select Channel select Verify transfer Write transfer Read transfer Illegal bits Auto-initialization disable Auto-initialization enable Address increment Address decrement Demand mode select Single mode select Block mode select Cascade mode (unsupported)
Table Mask Register: Access Bits 8237 Mode
Description
Channel unmasked Channel masked Channel unmasked Channel masked Channel unmasked Channel masked Channel unmasked Channel masked
Table Mask Register: Access 8237 Mode
Description Select channel mask Select channel mask Select channel mask Select channel mask Clear mask mask
Don't care
Table Request Register: Access 8237 Mode
Description Select channel request Select channel request Select channel request Select channel request Clear request request
Don't care
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Table Status Register: Access 8237 Mode
Description Channel terminal count Channel terminal count Channel terminal count Channel terminal count Channel request Channel request Channel request Channel request
Table Non-8237 Internal Registers
Name Source Address Register Word Count Register Destination Address Register Command Register Temporary Register Mode Register Channel Control Register
Size Bits 8,16,32
Number Registers
Based width address selected Based width word count register selected Based width data selected Number channels selected
Source Address Register This register only available non-8237 mode. Each channel Source Address Register whose width matches with address width. This register stores value source memory address used during transfers. address automatically incremented decremented after each transfer, depending respective data width bits. This register written consecutive cycles after clearing byte pointer. number cycles taken access this register depends size address bus. During transfer between location memory, this register holds address memory location. During memory-to-memory transfer, this register stores address location that read from. user must always program register with address that aligned with width data bus. Destination Address Register This register only available non-8237 mode. Each channel Destination Address Register whose width matches with address width. address automatically incremented decremented after each transfer depending respective data width bits. This register written consecutive cycles after clearing byte pointer. number cycles taken access this register depends size address bus. During memory-to-memory transfers, this register stores address memory location that written into. This register used during transfers between memory I/O. user must always program register with address that aligned with width data bus. Word Count Register This register only available non-8237 mode, width configurable. This register determines number transfers performed. actual number transfers more than value programmed into this register. current word count decremented after each transfer. When value register goes from zero 0xFFFF, Terminal Count (eopout_n) signal generated. transfer, this register value 0xFFFF auto-initialization enabled channel.
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Command Register This register controls operation core. This register bits wide non-8237 mode. reset master clear clears register. Table lists functions this register non-8237 mode. Mode Register (Non- 8237 Mode) Each channel 8-bit mode register. Table lists format mode register non-8237 mode. Programming corresponding increment decrement bits same value hold source destination address constant. Channel Control Register This register visible non-8237 mode. Each channel channel control register. Table lists register's format. reset master clear resets request sets mask. This masks channel's hardware requests. Auto-initialization disabled upon reset. Table Command Register Non-8237 Mode
Description Controller enable Controller disable
Reserved. This always Reserved. This always dack active dack active high
Table Mode Register Non-8237 Mode
Description Memory-to-memory disable Memory-to-memory enable Write transfer Read transfer bit0=1 Increment Source Address disable Increment Source Address enable Decrement Source Address disable Decrement Source Address enable Increment Destination Address disable Increment Destination Address enable Decrement Destination Address disable Decrement Destination Address enable Demand mode select Single mode select Block mode select Illegal
Note: Bits mutually exclusive. They cannot enabled same time since address will either increment decrement. This also applies Bits
Table Channel Control Register Non-8237 Mode
Description Clear Request Request
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Description Channel unmasked Channel masked Auto Initialization disable Auto Initialization enable
Register Address
8237 non-8237 modes MCDMA Controller decode different numbers input signals. signal used mapping register address decoding software command. Table Register Address Software Command 8237 Mode
ain3 ain2 ain1 ain0 Channel Write iorin_n iowin_n Base current Address Base current Word Count Base current Address Base current Word Count Base current Address Base current Word Count Base current Address Base current Word Count Command Register Single Request command Single Mask command Mode Register Clear Byte Pointer command Master clear command Clear Mask Register command Mask register Read iorin_n iowin_n Current address Current Word Count Current address Current Word Count Current address Current Word Count Current address Current Word Count Read Status Register Illegal Illegal Illegal Illegal Read temporary Illegal Illegal
8237 mode, additional software commands are: Clear Byte Pointer, Master Clear Clear Mask Register. Table Register Address Software Command Non-8237 Mode
ain2 ain1 ain0 Write: iorin_n iowin_n Read: iorin_n iowin_n Command register Source Address register Word Count register Destination Address register Mode register Channel Control register Master Clear command Clear Byte Pointer command
Programming MCDMA Controller
Programming core achieve desired functionality very similar both 8237 non-8237 modes. differences address name registers
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8237 mode, steps program core are: Disable controller through command register
Multi-Channel Controller User's Guide
Program Mode Register Select channel programmed features channel programmed, such transfer mode, read/write/verify transfer, address increment/decrement, etc. Write into Address Registers Word Count Register base source address register number transfer performed Word Count Registers. Enable controller non-8237 mode, steps program core are: Disable controller Input first bits ain, ain[2:0], selects which registered programmed. rest bits select which channel programmed. Program Mode Channel control registers channels Write into Address registers Word Count register Enable controller core remains idle state (SI) long transfers requested. While state dreq signals sampled. When unmasked request presented, core enters active state. request either software hardware request. Although internal registers programmed state before hlda signal asserted, good practice program internal registers only while core Idle state (SI). functionality controller guaranteed deterministic internal registers accessed during active cycle.
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MCDMA Core Design Flow
Core implemented using various methods. scope this document covers only push-button Graphical User Interface (GUI) flow. Figure illustrates software flow model used when evaluating MCDMA core. Figure Lattice Evaluation Flow
Start
Install launch ispLEVER software
Obtain desired package (download Core Evaluation package purchase package)
Install package Simulation Model Perform functional simulation with provided core model Core Netlist
Synthesize top-level design with black declaration
Place route design
static timing analysis
Done
Manager Tool
Lattice parameterization tool, Manager, incorporated ispLEVER software. provides Graphical User Interface (GUI) entering required parameters configure core. After required parameters have been entered, following file generated: Parameter file (<module name>.lpc) This file contains configuration parameters entered user Manager GUI.
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Manager from ispLEVER software environment: Launch ispLEVER software. Select File Project. project exists, skip Step Browse directory desired location project. files generated will located this directory. Type project name select Schematic/VHDL, Schematic/VerilogHDL EDIF project type, skip step Select File Open Project. Browse project directory select project. Select Tools Module/IP Manager launch Manager GUI. Double-click folder names click plus sign expand Cores folder then Lattice folder. Figure shows Manager. Figure Manager Main Window
Click MC-DMA_Controller Core open core dialog box. Enter desired module name fill other required fields shown Figure Click Customize button bring parameter configuration dialog shown Figure
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Figure MC-DMA Controller Parameter Configuration Dialog
Enter desired parameter values, click Generate button. Manager tool generates output files described above. Find generated output files from project directory. more detailed information Manager, please refer Module/IP Manager User Manual.
Functional Simulation under ModelSim Platform)
Once Multi-Channel Controller been downloaded unzipped designated directory, core ready evaluation. functional simulation Decoder core involved developing verification environment that supports very comprehensive test suite. simulation script file provided "eval" directory simulation. script file vsim_dma_mc.do uses pre-compiled models provided with this package. pre-compiled library models located directory: Simulation Procedures Launch ModelSim. Using main GUI, change directory location. Select: File Change Directory Execute <Modelsim macro name>.do Select: Macro Execute Macro scripts/vsim_dma_mc.do pre-compiled model provided this evaluation package does work with version ModelSim embedded ispLEVER v.3.0 software. more information ModelSim, please refer ModelSim User's Manual.
Lattice Semiconductor
Multi-Channel Controller User's Guide
Core Implementation
Users instantiate core netlist implement into their system design. following Verilog files Multi-Channel Controller core provided: dma_mc_o4_2_00x.v Multi-Channel-DMA Controller core-top instantiated module top_mc_dma.v top-level module Users core-top black system designs. default signal names top-level file must replaced with real signal names from system design.
Black Considerations
Since core delivered gate-level netlist, synthesis software will re-synthesize internal nets core. more information regarding Synplify's black declaration, please refer Instantiating Black Boxes Verilog section Synplify Reference Manual. core implementation consists synthesis place route sections. Each sections described below. synthesis tools, Synplicity Synplify LeonardoSpectrum, included ispLEVER software seamless processing designs. current cores being tested with EDIF flow. following step-bystep procedure each synthesis tool generate EDIF netlist containing core black box.
Synthesis using Synplicity Synplify
step-by-step procedure provided below describes synthesis using Synplify. Create working directory synthesis. Launch Synplify synthesis tool. Start project specified files following order: ~/source/orca4_synplify.v ~/source/orca_pll.v ~/source/dma_mc_o4_2_00x.v ~/source/top_mc_dma.v Implementation Options select target device 4E02, speed grade package BA352. Specify EDIF netlist filename EDIF netlist output location Implementation Options. This top-level EDIF netlist will used during Place Route. Implementation Options, following: Fanout guide: Enable Compiler Enable Resource Sharing global frequency constraint 80MHz Select Run.
Synthesis using LeonardoSpectrum
step-by-step procedure provided below describes synthesis using LeondardoSpectrum. Create working directory synthesis. Launch LeonardoSpectrum synthesis tool.
Lattice Semiconductor
Multi-Channel Controller User's Guide
Start project select Lattice device technology ORCA-4E. Select Input tab, Working Directory path pointed source directory. Open specified files following order: ~/source/top_mc_dma.v ~/source/orca_pll.v ~/source/dma_mc_o4_2_00x.v Constraints tab, Clock Frequency 80MHz. synthesis directory, created step path where would like save output netlist. Specify EDIF netlist filename output file. This top-level EDIF netlist will used during Place Route. Select Flow
Place Route ORCA
Once EDIF netlist generated, next step import EDIF into Project Navigator. ispLEVER software automatically detects provided EDIF netlist instantiated core design. step-by-step procedure provided below describes perform Place Route ispLEVER ORCA device: Create working directory Place Route. Start project, assign project name select project type EDIF. Select ORCA target device, with speed grade BA352 package. Copy following files Place Route working directory: .\.\par\dma_mc_o4_2_00x.ngo .\.\par\dma_mc_o4_2_00x.prf top-level EDIF netlist generated from running synthesis Rename dma_mc_o4_2_00x.prf file step match project name. example, project name "demo", then .prf file must renamed demo.prf. preference file name must match that project name. Note: might need delete <project_name>.prf before rename dma_mc_o4_2_00x.prf <project_name>.prf Import EDIF netlist into project. ispLEVER Project Navigator, select Tools Timing Checkpoint Options. Timing Checkpoint Options window will appear. both Checkpoint Options, select Continue. ispLEVER Project Navigator, highlight Place Route Design, with right mouse click select Properties. following properties: Placement Iterations: Placement Save Best Run: Placement Iteration Start Point: Routing Resource Optimization: Routing Delay Reduction Passes: Routing Passes: Placement Effort Level:
Lattice Semiconductor
Multi-Channel Controller User's Guide
other options remain their default values. properties shown above settings dma_mc_o4_2_001. Each configuration properties settings. appropriate settings specific configuration, please refer Readme.htm that located downloaded package. Select Place Route Trace Report project navigator execute Place Route generate timing report ORCA. fMAX core does meet required static timing, then proceed step Otherwise, jump step Select Cycle Stealing process Project Navigator. Highlight Place Route TRACE Report, with right mouse click select Force Level. timing report generated. Timing violations over-constraints appear timing report. following steps describe obtain correct timing report: Copy file post_route_trace.prf that located directory place route working directory step Open DOS-shell change directory working directory step Type: trce post_route_trace.twr <your project_name>.ncd post_route_trace.prf timing report generated post_route_trace.twr
Reference Information
ispLEVER Software User Manual, Lattice Semiconductor Corporation 8237A High Performance Programmable Controller, Intel Corporation, September 1993.
Technical Support Assistance
Hotline: 1-800-LATTICE (North America) +1-408-826-6002 (Outside North America) e-mail: techsupport@latticesemi.com Internet: www.latticesemi.com
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