Selectable 8237 Mode Configurable Independent Channels Non-8237 Mode C

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Selectable 8237 Mode Configurable Independent Channels Non-8237 Mode C

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Multi-Channel Controller
Selectable 8237 Mode Configurable Independent Channels Non-8237 Mode Configurable Data Width Bits Non-8237 Mode Configurable Address Width Bits Non-8237 Mode Configurable Word Count Register Width Non-8237 Mode Independent Auto-Initialization Channels Memory-to-Memory Transfers Single, Block, Demand Transfer Mode Memory Block Initialization Software Requests
General Description
Multi-Channel Direct Memory Access (MCDMA) Controller designed improve microprocessor system performance allowing external devices transfer information directly from system memory. Memory-to-memory transfer capability also supported. MCDMA Controller core supports modes: 8237 non-8237. When 8237 mode selected, core compatible with Intel 8237A Controller with variations. These variations listed Compatibility Differences with 8237 Intel Device section this document. 8237 mode supports four independent channels while non-8237 mode supports independent channels.
Block Diagram
Figure Controller Core Diagram
cs_n eopin_n reset iorin_n iowin_n ready hlda ain[AIN_BUS_WIDTH -1:0] dbin[DATA_BUS_WIDTH -1:0 Register Block dbout[DATA_BUS_WIDTH -1:0] dreq[N-1:0] Priority Request Encoder dack[N-1:0] Number channels
2003 Lattice Semiconductor Corp. Lattice trademarks, registered trademarks, patents, disclaimers listed www.latticesemi.com/legal. other brand product names trademarks registered trademarks their respective holders. specifications information herein subject change without notice. product described herein subject continuing development, applicable specifications information subject change without notice. Such specifications information provided good faith; actual performance guaranteed, dependent many factors, including user's system design.
hreq iorout_n Interface State Machine iowout_n memr_n memw_n eopout_n
aout[ADDR_BUS_WIDTH -1:0]
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ip1011_02
Lattice Semiconductor
Multi-Channel Controller
Interface State Machine
Interface block consists blocks: Control Data. Interface Control Block decodes (address in). generates Enable signals selected registers during write cycle. When registers read, provides Select signal multiplexer, which routes appropriate register's contents onto data bus. Interface block implements configuration registers. includes routing logic transfer either selected register contents during register read cycle temporary register contents during memory write cycle memory-to-memory transfer mode. State Machine handles behavior transfer. controls transfer mode memory-tomemory I/O-to-memory. While non-8237 mode does support compressed mode, 8237 mode does. 8237 mode I/O-memory transfer clock cycles. This enhances greater throughput.
Priority Request Encoder
This Priority Request Encoder prioritizes requests asserts dack signal winning request. 8237 mode, arbitrating scheme user programmable available either fixed priority rotating priority mode. non-8237 mode restricted mode which fixed priority mode. fixed priority mode, highest priority channel zero. lowest priority three 8237 mode user selectable channel non-8237 mode. With rotating priority, lowest priority channel most recent serviced channel. This mode ensures that channels served equally. maximum wait channel serviced time taken service other channels.
Register Block
8237 non-8237 modes have different types registers. Tables list these registers show each width. Table Internal Registers 8237 Mode
Name Base Address Registers Base Word Count Registers Current Address Registers Current Word Count Registers Command Register Status Register Temporary Register Mode Register Mask Register Request Register Size Bits Number Registers
Lattice Semiconductor
Table Internal Registers Non-8237 Mode
Name Source Address Register Word Count Register Destination Address Register Command Register Temporary Register Mode Register Channel Control Register
Multi-Channel Controller
Size Bits
Number Registers
Based width address selected Based width word count register selected Based width data selected Number channels selected
Compatibility Differences with 8237 Intel Device
When MCDMA core configured 8237 mode, differs from 8237A Intel core following ways: bidirectional ports split into separate input output ports. MCDMA does support cascade mode operation. latch that holds upper byte address internal address strobe signal ADSTB generated. slave's write cycle MCDMA core synchronous.
Transfer Mode
Both 8237 non-8237 mode MCDMA supports three kinds transfer mode: Single Transfer Mode single transfer mode, MCDMA programmed make transfer only. word count decrements. When word count about roll over from zero FFFFH, signal Process Output (eopout_n) asserted. Block Transfer Mode block transfer mode, MCDMA programmed continue making transfers until eopout_n encountered. Demand Transfer Mode demand transfer mode, MCDMA programmed continue making transfers until eopout_n asserted external eopin_n encountered until dreq deasserted.
Parameter Descriptions
Table lists parameters used configuring MCDMA core. values these parameters must done prior synthesis functional verification. parameters parenthesis ones generated Manager tool.
Lattice Semiconductor
Table MCDMA Parameters
Parameter Mode (MODE_8237) Number Channel (NUM_CHANNELS) Data Width (DATA_BUS_WIDTH) Address Width (ADDR_BUS_WIDTH) Word Count Width (WORD_COUNT_WIDTH) Internal Address Width (AIN_BUS_WIDTH) Description
Multi-Channel Controller
Supported Values TRUE/FALSE (8237) (non 8237) (8237) (non 8237) (8237) (non 8237) (8237) (non 8237) (8237) when (non 8237) when (non 8237) when (non 8237) when (non 8237) when (non 8237)
Defines mode. TRUE, will 8237 mode, otherwise will non-8237 mode. Sets number channels. 8237 mode fixed four channels. non-8237, channels Sets size data buses temporary register. Sets size output address. 8237 mode, sets size current base address register. non8237 mode, sets size source address register. Sets size Word Count Register. Value automatically based Number Channel parameter (NUM_CHANNELS
Table MCDMA Signal List Ports Within User's Application
Port Name cs_n reset Type Input Input Input Active State Rising Edge High Description Clock. This signal controls synchronizes operations MCDMA. Chip Select. This active signal used select MCDMA. Reset. This active high signal that clears internal registers. After reset, device placed Idle state requests masked. Ready. This active high signal used extend memory read write pulses from MCDMA. This most often used accommodate slow memories. Hold Acknowledge. This active high signal generated indicates relinquished control system buses. Process Input. This active input permits external termination current service. Read Input. This active signal. When asserted along with cs_n, permits read internal registers MCDMA. Write Input. This active signal. When asserted along with cs_n, permits write into internal registers MCDMA. Address. This signal selects internal registers. 8237 mode, four bits wide. non-8237 mode, width depends number channels selected. Data Input. writes internal registers through this data bus.
ready
Input
High
hlda
Input
High
eopin_n iorin_n
Input Input
iowin_n
Input
[AIN_BUS_WIDTH-1:0]
Input
dbin [DATA_BUS_WIDTH-1:0]
Input
Lattice Semiconductor
Multi-Channel Controller
Table MCDMA Signal List Ports Within User's Application (Continued)
Port Name dreq[N-1:0] Type Input Active State High/Low (8237) High (Non-8237) Description Request. These parity signals asynchronous signals generated peripherals requesting service. device reset initializes dreq signals active high. 8237 mode, these parity signals programmable active high low. non-8237, these signals always active high. Hold Request. This active high signal sent request control over system bus. Process Out. This active signal indicates normal termination service. Read Output. This active signal used access data from peripheral during Write transfer. Data Output. This contains value internal register when read CPU. write-to-memory phase memory-to-memory operation, dbout data transmits data from temporary register. Write Output. This active signal used load data peripheral during Read transfer. Memory Write. This active signal used write data selected memory location during Write memory-to-memory transfer. Memory Read. This active signal used access data from selected memory location during Read memory-to-memory transfer. Address Enable. This active high signal enables eightbit latch that contains upper eight address bits onto system address bus. Address output. These lines enabled only during active transfer contain memory address. Acknowledge. This signal used notify requesting peripheral that been granted cycle. polarity this signal programmable. device reset initializes dack signals active low.
hreq eopout_n iorout_n dbout [DATA_BUS_WIDTH-1:0]
Output Output Output Output
High
iowout_n memw_n
Output Output
memr_n
Output
Output
High
aout [ADDR_BUS_WIDTH-1:0] dack[N-1:0]
Output Output
High/Low
Note: Number channels
Custom Core Configurations
MCDMA configurations that available Evaluation Package, please contact your Lattice sales office request custom configuration.
Related Information
more information core usage, please refer Multi-Channel Controller Core User's Guide, available Lattice site www.latticesemi.com.
Lattice Semiconductor
Multi-Channel Controller
Appendix ORCA® Series FPGAs
Table Performance Resource Utilization1
Mode 8237 Name Parameter File dma_mc_o4_2_001.lpc LUTs 1258 2661 ORCA PFUs2 Registers 1187 SysMem External Pins fMAX (MHz)
Non-8237 dma_mc_o4_2_002.lpc
Performance utilization characteristics generated using OR4E02-2PBGAM680-DE Lattice's ispLEVERv3.0 software. Synthesized using Synplicity Synplify v.7.03. When using this core different density, package, speed, grade within ORCA family, performance vary slightly. standard logic block some Lattice devices. more information, check data sheet device.
Supplied Netlist Configurations
Ordering Part Number (OPN) configurations this core ORCA Series devices DMA-MC-O4-N2. Table lists Lattice-specific netlists that available Evaluation Package, which downloaded from Lattice site www.latticesemi.com. Table Core Configuration
Name Parameter File 8237 Mode dma_mc_o4_2_001.lpc Non-8237 Mode dma_mc_o4_2_002.lpc Number Channels Data Width Address Width Word Count Width
load preset parameters this core, click "Load Parameters" button inside Manager tool. Make sure that looking file inside this core's directory location. Lattice Parameter Configuration files (.lpc) located within this directory.
Lattice Semiconductor
Multi-Channel Controller
Appendix ispXPGA
Table Performance Resource Utilization1
Mode 8237 Non-8237 Name Parameter File dma_mc_xp_2_001.lpc dma_mc_xp_2_002.lpc LUT42 1450 3487 ispXPGA PFUs2 1072 Registers 1181 sysMEM EBRs External Pins fMAX (MHz)
Performance utilization characteristics generated using LFX1200B-05F900C Lattice's ispLEVERv3.0 software. Synthesized using Synplicity Synplify v.7.03. When using this core different density, package, speed, grade within ispXPGA family, performance vary slightly. standard logic block some Lattice devices. more information, check data sheet device.
Supplied Netlist Configurations
Ordering Part Number (OPN) configurations this core ispXPGA devices DMA-MC-XP-N2. Table lists Lattice-specific netlists that available Evaluation Package, which downloaded from Lattice site www.latticesemi.com. Table Core Configuration
Name Parameter File 8237 Mode dma_mc_xp_2_001.lpc Non-8237 Mode dma_mc_xp_2_002.lpc Number channels Data Width Address Width Word Count Width
load preset parameters this core, click "Load Parameters" button inside Manager tool. Make sure that looking file inside this core's directory location. Lattice Parameter Configuration files (.lpc) located within this directory.

Selectable 8237 Mode Configurable Independent Channels Non-8237 Mode C

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