Page Mode Dual Work Flash Memory 32M-bit, 64M-bit, 128M-bit LH28F
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APPENDIX FUM00701 ISSUE: Jan. 2003
Page Mode Dual Work Flash Memory
32M-bit, 64M-bit, 128M-bit LH28F320BF, LH28F640BF, LH28F128BF Series
Rev.
FUM00701
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Rev. 2.44
FUM00701
CONTENTS
PAGE Introduction. Features Definition Block, Plane Partition Product Overview Product Description. 1.4.1 Memory Block Organization 1.4.2 Four Physical Planes 1.4.3 Partition 1.4.4 Parameter Block 1.4.5 Main Block. 1.4.6 (One Time Program) block. Principles Operation Operation Mode after Power-up Reset Mode Read, Program Erase Operation Status Register Each Partition Data Protection. Operation Read Array Output Disable Standby. Reset. Read Identifier Codes/OTP. Read Query Write Command Command Definitions Write Command 4.1.1 Using Dual Work Operation 4.1.2 Using Dual Work Operation 4.1.3 Full Chip Erase Program Read Array Command Read Identifier Codes/OTP Command Read Query Command. Read Status Register Command. Clear Status Register Command Block Erase Command. Full Chip Erase Command. Program Command 4.10 Page Buffer Program Command
PAGE 4.11 Block Erase Suspend Command Block Erase Resume Command 4.12 (Page Buffer) Program Suspend Command (Page Buffer) Program Resume Command. 4.13 Block Lock Command 4.14 Clear Block Lock Command. 4.15 Block Lock-Down Command 4.16 Program Command. 4.17 Partition Configuration Register Command 4.17.1 Partition Configuration Register 4.17.2 Partition Configuration Design Considerations Hardware Design Considerations. 5.1.1 Control using RST#, 5.1.2 Power Supply Decoupling 5.1.3 Traces Printed Circuit Boards. 5.1.4 VCC, VPP, RST# Transitions. 5.1.5 Power-Up/Down Protection 5.1.6 Power Dissipation 5.1.7 Automatic Power Savings 5.1.8 Reset Operation. Software Design Considerations 5.2.1 (Write State Machine) Polling. 5.2.2 Attention Program Operation. Data Protection Method High Performance Read Mode. 5.4.1 Compatibility. 5.4.2 Using Asynchronous Page Mode 5.4.3 Single Read Mode. Common Flash Interface. Query Structure Output. Query Structure Overview Block Status Register Query Identification String System Interface Information. Device Geometry Definition. Sharp-Specific Extended Query Table. Related Document Information.
Rev. 2.44
FUM00701
Introduction
This appendix describes LH28F320BF series, LH28F640BF series LH28F128BF series, Page Mode Dual Work Flash memory. this document, functions LH28F320BF series, LH28F640BF series LH28F128BF series explained. However, function which available varies according each product. Refer specifications whether each function this document available not. function which described specifications used that product. LH28F320BF series, LH28F640BF series LH28F128BF series Flash memory called product this document. Section outlines product. Sections describe memory organization functionality. When designing specific system, take into design considerations described Section
Plane0 Plane3 contains parameter blocks main blocks. Plane1 Plane2 consist only main blocks. Partition: Read operation done partition while Program/Erase operation being done another partition. Partition contains least plane four planes. Partition boundaries flexibly plane boundary Partition Configuration Register command. partition configuration register "111" plane dual work mode), partition exactly same plane. Section 4.17 more information. Table Address Range Each Plane (1), Plane Plane Plane Plane Plane Contains Blocks within following Address 000000H-07FFFFH 080000H-0FFFFFH 100000H-17FFFFH 180000H-1FFFFFH 000000H-0FFFFFH 100000H-1FFFFFH 200000H-2FFFFFH 300000H-3FFFFFH
Features
product following features: Dual work operation Flexible partition configuration High performance asynchronous reads Page buffer program Individual block locking blocks locked power-up 8-word (One Time Program) block power consumption Parameter block architecture
NOTE: This table shows density memory area selected each (CE#) when product more (CE#) pins Refer specifications address range product which 32-bit interface.
Product Overview
product capable dual work operation: erase program operation partition read operation other partitions (see Table partition accessed automatically identified according input address. Dual work operations achieved dividing memory array into four physical planes shown Figure through Figure 3.2. Each plane exactly quarter entire memory array. device also virtual partitions. Several planes flexibly merged partition writing Partition Configuration Register command. This feature allows user read from partition even though other partitions executing erase program operation. device partitions configuration, each partition exactly same each physical plane. After power-up device reset, plane merged into partition parameter devices plane1-3 merged into partition bottom parameter devices.
Definition Block, Plane Partition
Block, Plane Partition defined used this document explained below. Refer specifications number blocks, planes partitions product which more (CE#) pins which 32-bit interface. Block Main Block: Words. Parameter Block: Words. 32M-bit device parameter blocks main blocks. 64M-bit device parameter blocks main blocks. Plane: 32M-bit 64M-bit devices divided into four physical planes (see Table
Rev. 2.44
FUM00701
During dual work operation, read operations partition being erased programmed access status register which indicates whether erase program operation successfully completed not. Dual work operation cannot executed during full chip erase program mode. Memory array data read asynchronous 8-word page mode. default after power-up device reset asynchronous read mode which 8-word page mode available. product contains page buffer words. page buffer program mode, data programmed first stored into page buffer before being transferred memory array. page buffer program high speed program performance. page buffer program operation programs 16-word data sequential addresses within block. That this operation cannot used program data addresses separated something even same block, divided into different blocks. Page buffer program cannot applied block described later this section. parameter blocks main blocks, individual block locking scheme that allows block locked, unlocked locked-down with latency. time required block locking less than minimum command cycle time (minimum time from rising edge write command next rising edge WE#). block locked Block Lock command Block Lock-down command. Block erase, full chip erase (page buffer) program operation cannot executed locked block, protect codes data from unwanted operation noises, etc. When VIL, locked-down block cannot unlocked. When VIH, lockdown bits disabled block locked unlocked through software. After goes VIL, block previously marked lock-down revert that state. power-up device reset, blocks default locked state locked-down, regardless states before power-off reset operation. This means that write operations block disabled. Unauthorized cellular phone, communication device, etc. avoided storing security code into 8-word (One Time Program) block (see Figure provided addition parameter main blocks. ensure high reliability, lock function block provided.
product which monitors level power supply voltage. When VPPLK, memory contents cannot altered data blocks completely write protected (see Note Note that used only checking supply voltage, used device power supply pin. Automatic Power Savings (APS) power features help increase battery life portable applications. mode initiated shortly after read cycle completion. this mode, current consumption decreases value equivalent that standby mode. Standard address access timings (tAVQV) provide data when addresses changed. During dual work operation (one partition being erased programmed, while other partitions read modes), device cannot enter Automatic Power savings mode input address remains unchanged. (Command User Interface) serves interface between system processor internal operation device. valid command sequence written initiates device automation. product uses advanced (Write State Machine) automatically execute erase program operations within memory array. controlled through CUI. writing valid command sequence CUI, instructed automatically handle sequence internal events timings required block erase, full chip erase, (page buffer) program program operations. Status registers prepared each partition indicate status partition. Even occupied executing erase program operation partition, status register other partition reports that device busy when device partitions configuration.
(Note Please note following: lockout voltage VPPLK inhibit write functions, refer specifications. should kept lower than VPPLK (GND) during read operations protect data blocks.
Rev. 2.44
FUM00701
When RST# VIL, reset mode enabled which minimizes power consumption provides write protection. RST# also useful resetting read array mode initializing status register bits "80H". During power-on/off transitions, keep RST# level protect data from noises, initialize device's internal control circuit. reset time (tPHQV) required from RST# switching high until outputs valid. Likewise, device wake time (tPHWL, tPHEL) from RST#-high until writes recognized.
Erase operation erases block blocks. Programming executed either word increments page sized increments using high speed program page buffers. These operations industry standard command sequences. Suspend commands exist both erase program operations permit system interrupt erase program operation progress enable access another memory location same partition. Nested suspend also supported. This allows software suspend erase partition, start programming second partition, suspend programming second partition, then read from second partition. After reading from second partition, resume suspended program second partition, then resume suspended erase first partition. Figure shows block diagram product. example descriptions explained Table
Table Simultaneous Operation Modes Allowed with Four Planes(1, THEN MODES ALLOWED OTHER PARTITION PARTITION Read Array Read ID/OTP Read Status Read Query Word Program Page Buffer Program Program Block Erase Full Chip Erase Program Suspend Block Erase Suspend Read Read Read Array ID/OTP Status Read Word Query Program Page Block Block Full Chip Program Buffer Erase Program Erase Erase Suspend Program Suspend
NOTES: denotes operation available. Configurative Partition Dual Work Restrictions: Status register reflects partition state, (Write State Machine) state this allows status register each partition. Only partition erased programmed time command queuing. Commands must written address within block targeted that command.
Rev. 2.44
FUM00701
DQ0-DQ15
VCCQ
Output Buffer
Input Buffer
Logic Query
Output Multiplexer
Partition Configuration Register
Data Register
Identifier Codes Register Status Register
Command User Interface
RST#
Multiplexer Data Comparator
Decoder
Parameter Block Parameter Block Parameter Block Parameter Block Parameter Block Parameter Block Parameter Block Parameter Block
Page Buffer
Y-Gating Main Block (N-1) Main Block Main Block Main Block
Block
A0-A20 (32M) A0-A21 (64M)
Write state Machine
Erase/Program Voltage switch
Input Buffer
Decoder
32K-Word Main Blocks (N-2)
number main blocks N=62 (32Mbit) N=126 (64Mbit)
Block diagram 32Mbit 64Mbit with 16-bit interface pin.
Figure Block Diagram
Rev. 2.44
FUM00701
Table Descriptions Symbol A0-A20 A0-A21 Type INPUT INPUT Name Function ADDRESS INPUTS: Inputs addresses. 32M: A0-A20 ADDRESS INPUTS: Inputs addresses. 128M: A0-A21 DATA INPUTS/OUTPUTS: Inputs data commands during (Command User Interface) write cycles, outputs data during memory array, status register, query code, identifier code partition configuration register code reads. Data pins float highimpedance (High when chip outputs deselected. Data internally latched during erase program cycle. CHIP ENABLE: Activates device's control logic, input buffers, decoders sense amplifiers. CE#-high (VIH) deselects device reduces power consumption standby levels. RESET: When (VIL), RST# resets internal automation inhibits write operations which provides data protection. RST#-high (VIH) enables normal operation. After power-up reset mode, device automatically read array mode. RST# must during power-up/down. OUTPUT ENABLE: Gates device's outputs during read cycle. WRITE ENABLE: Controls writes array blocks. Addresses data latched rising edge (whichever goes high first). WRITE PROTECT: When VIL, locked-down blocks cannot unlocked. Erase program operation executed blocks which locked lockeddown. When VIH, lock-down disabled.
DQ0-DQ15
INPUT/ OUTPUT
INPUT
RST#
INPUT
INPUT INPUT
INPUT
RY/BY#
READY/BUSY#: Indicates status internal (Write State Machine). When low, performing internal operation (block erase, full chip erase, (page buffer) OPEN DRAIN program program). RY/BY#-High indicates that ready OUTPUT commands, block erase suspended (page buffer) program inactive, (page buffer) program suspended, device reset mode. MONITORING POWER SUPPLY VOLTAGE: used power supply pin. With VPPVPPLK, block erase, full chip erase, (page buffer) program program cannot executed should attempted. Applying 12V±0.3V provides fast erasing fast programming mode. this mode, power supply pin. Applying 12V±0.3V during erase/program only done maximum 1,000 cycles each block. connected 12V±0.3V total hours maximum. this beyond these limits reduce block cycling capability cause permanent damage. DEVICE POWER SUPPLY (see specifications): With VCCVLKO, write attempts flash memory inhibited. Device operations invalid voltage (see Characteristics) produce spurious results should attempted. INPUT/OUTPUT POWER SUPPLY (see specifications): Power supply input/ output pins. GROUND: float ground pins. CONNECT: Lead internally connected; driven floated.
INPUT
VCCQ
SUPPLY
SUPPLY SUPPLY
Rev. 2.44
FUM00701 Product Description 1.4.1 Memory Block Organization
device divided into four physical planes partitions flexibly configured Partition Configuration Register command. This allows dual work operations, that simultaneous read-while-erase read-while-program operations. address locations blocks, memory Figure through Figure 3.2. Refer specifications address locations product which more (CE#) pins which 32-bit interface.
1.4.5 Main Block
32K-word main blocks store code and/or data. protection main block also controlled using combination VPP, RST#, WP#, block lock block lock-down bit.
1.4.6 (One Time Program) block
block special block that cannot erased order secure high system reliability. This 8-word (128-bit) block independent main blocks parameter blocks. Figure shows block address map. block divided into areas. factory programmed area where unique number been programmed SHARP factory. This factory programmed area "READ ONLY" (already locked). other customer programmable area that available customers. This customer programmable area also locked. After locking, this customer programmable area protected permanently. data within block read Read Identifier Codes/OTP command (90H). return read array mode, write Read Array command (FFH) CUI. block bits programmed writing Program command (C0H) CUI. Write Program command (C0H) command cycle then write address data cycle. program operation failed, status register SR.4 "1". block locked, status register bits SR.4 SR.1 "1". block locked using Program command (C0H). Write Program command (C0H) command cycle then write data (FFFDH) lock location (80H) cycle. Read cycle from address (80H) indicates lockout state block. address (80H) means factory programmed area lock state ("1" "NOT LOCKED" "LOCKED"). address (80H) means customer programmable lock state. block lockout state reversible. Unlike main array block lock configuration, lock state block kept unchanged even power turned reset operation performed. Program command only available programming block. Page buffer program operations available main array. program cannot suspended through (Page Buffer) Program Suspend command (described later). Dual work operation cannot executed during program.
1.4.2 Four Physical Planes
product four physical planes (one parameter plane three uniform planes). Each plane consists 8M-bit (32M-bit device) 16M-bit (64M-bit device) Flash memory. parameter plane consists eight 4Kword parameter blocks fifteen (32M-bit device) thirty-one (64M-bit device) 32K-word main blocks. Each uniform plane consists sixteen (32M-bit device) thirty-two (64M-bit device) 32K-word main blocks. Each block erased independently 100,000 times. Refer specifications number planes each plane density product which more (CE#) pins which 32-bit interface.
1.4.3 Partition
Partition boundaries configured Partition Configuration Register command. Dual work operation done partitions. partition configuration Table Figure more detail. Only partition erased programmed time. Simultaneous operation modes shown Table
1.4.4 Parameter Block
Eight 4K-word parameter blocks within parameter partition provided memory area facilitate storage frequently update small parameters that would normally stored EEPROM. using software techniques, word-rewrite functionality EEPROMs emulated. protection parameter block controlled using combination VPP, RST#, WP#, block lock block lock-down bit.
Rev. 2.44
FUM00701
BLOCK NUMBER ADDRESS RANGE
4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 1FF000H 1FFFFFH 1FE000H 1FEFFFH 1FD000H 1FDFFFH 1FC000H 1FCFFFH 1FB000H 1FBFFFH 1FA000H 1FAFFFH 1F9000H 1F9FFFH 1F8000H 1F8FFFH 1F0000H 1F7FFFH 1E8000H 1EFFFFH
PLANE3 (PARAMETER PLANE)
BLOCK NUMBER ADDRESS RANGE
32K-WORD 32K-WORD 32K-WORD 0F8000H 0FFFFFH 0F0000H 0F7FFFH 0E8000H 0EFFFFH 0E0000H 0E7FFFH 0D8000H 0DFFFFH 0D0000H 0D7FFFH 0C8000H 0CFFFFH 0C0000H 0C7FFFH 0B8000H 0BFFFFH 0B0000H 0B7FFFH 0A8000H 0AFFFFH 0A0000H 0A7FFFH 098000H 09FFFFH 090000H 097FFFH 088000H 08FFFFH 080000H 087FFFH
PLANE1 (UNIFORM PLANE)
1E0000H 1E7FFFH 1D8000H 1DFFFFH 1D0000H 1D7FFFH 1C8000H 1CFFFFH 1C0000H 1C7FFFH 1B8000H 1BFFFFH 1B0000H 1B7FFFH 1A8000H 1AFFFFH 1A0000H 1A7FFFH 198000H 19FFFFH 190000H 197FFFH 188000H 18FFFFH 180000H 187FFFH
32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD
32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD
178000H 17FFFFH 170000H 177FFFH 168000H 16FFFFH
32K-WORD 32K-WORD 32K-WORD
078000H 07FFFFH 070000H 077FFFH 068000H 06FFFFH 060000H 067FFFH 058000H 05FFFFH 050000H 057FFFH 048000H 04FFFFH 040000H 047FFFH 038000H 03FFFFH 030000H 037FFFH 028000H 02FFFFH 020000H 027FFFH 018000H 01FFFFH 010000H 017FFFH 008000H 00FFFFH 000000H 007FFFH
PLANE2 (UNIFORM PLANE)
PLANE0 (UNIFORM PLANE)
160000H 167FFFH 158000H 15FFFFH 150000H 157FFFH 148000H 14FFFFH 140000H 147FFFH 138000H 13FFFFH 130000H 137FFFH 128000H 12FFFFH 120000H 127FFFH 118000H 11FFFFH 110000H 117FFFH 108000H 10FFFFH 100000H 107FFFH
32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD
Figure 2.1. Memory 32Mbit (Top Parameter)
Rev. 2.44
FUM00701
BLOCK NUMBER ADDRESS RANGE
32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 0F8000H 0FFFFFH 0F0000H 0F7FFFH 0E8000H 0EFFFFH 0E0000H 0E7FFFH 0D8000H 0DFFFFH 0D0000H 0D7FFFH 0C8000H 0CFFFFH 0C0000H 0C7FFFH 0B8000H 0BFFFFH 0B0000H 0B7FFFH 0A8000H 0AFFFFH 0A0000H 0A7FFFH 098000H 09FFFFH 090000H 097FFFH 088000H 08FFFFH 080000H 087FFFH
PLANE1 (UNIFORM PLANE)
BLOCK NUMBER ADDRESS RANGE
32K-WORD 32K-WORD 32K-WORD 1F8000H 1FFFFFH 1F0000H 1F7FFFH 1E8000H 1EFFFFH 1E0000H 1E7FFFH 1D8000H 1DFFFFH 1D0000H 1D7FFFH 1C8000H 1CFFFFH 1C0000H 1C7FFFH 1B8000H 1BFFFFH 1B0000H 1B7FFFH 1A8000H 1AFFFFH 1A0000H 1A7FFFH 198000H 19FFFFH 190000H 197FFFH 188000H 18FFFFH 180000H 187FFFH
PLANE3 (UNIFORM PLANE)
32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD
32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD
078000H 07FFFFH 070000H 077FFFH 068000H 06FFFFH 060000H 067FFFH 058000H 05FFFFH 050000H 057FFFH 048000H 04FFFFH 040000H 047FFFH 038000H 03FFFFH 030000H 037FFFH 028000H 02FFFFH 020000H 027FFFH 018000H 01FFFFH 010000H 017FFFH 008000H 00FFFFH 007000H 007FFFH 006000H 006FFFH 005000H 005FFFH 004000H 004FFFH 003000H 003FFFH 002000H 002FFFH 001000H 001FFFH 000000H 000FFFH
32K-WORD 32K-WORD 32K-WORD
178000H 17FFFFH 170000H 177FFFH 168000H 16FFFFH 160000H 167FFFH 158000H 15FFFFH 150000H 157FFFH 148000H 14FFFFH 140000H 147FFFH 138000H 13FFFFH 130000H 137FFFH 128000H 12FFFFH 120000H 127FFFH 118000H 11FFFFH 110000H 117FFFH 108000H 10FFFFH 100000H 107FFFH
PLANE0 (PARAMETER PLANE)
PLANE2 (UNIFORM PLANE)
32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD
Figure 2.2. Memory 32Mbit (Bottom Parameter)
Rev. 2.44
FUM00701
BLOCK NUMBER ADDRESS RANGE
4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 3FF000H 3FFFFFH 3FE000H 3FEFFFH 3FD000H 3FDFFFH 3FC000H 3FCFFFH 3FB000H 3FBFFFH 3FA000H 3FAFFFH 3F9000H 3F9FFFH 3F8000H 3F8FFFH 3F0000H 3F7FFFH 3E8000H 3EFFFFH 3E0000H 3E7FFFH 3D8000H 3DFFFFH 3D0000H 3D7FFFH 3C8000H 3CFFFFH 3C0000H 3C7FFFH 3B8000H 3BFFFFH 3B0000H 3B7FFFH 3A8000H 3AFFFFH 3A0000H 3A7FFFH 398000H 39FFFFH 390000H 397FFFH 388000H 38FFFFH 380000H 387FFFH 378000H 37FFFFH 370000H 377FFFH 368000H 36FFFFH 360000H 367FFFH 358000H 35FFFFH 350000H 357FFFH 348000H 34FFFFH 340000H 347FFFH 338000H 33FFFFH 330000H 337FFFH 328000H 32FFFFH 320000H 327FFFH 318000H 31FFFFH 310000H 317FFFH 308000H 30FFFFH 300000H 307FFFH 2F8000H 2FFFFFH 2F0000H 2F7FFFH 2E8000H 2EFFFFH 2E0000H 2E7FFFH 2D8000H 2DFFFFH 2D0000H 2D7FFFH 2C8000H 2CFFFFH 2C0000H 2C7FFFH 2B8000H 2BFFFFH 2B0000H 2B7FFFH 2A8000H 2AFFFFH 2A0000H 2A7FFFH 298000H 29FFFFH 290000H 297FFFH 288000H 28FFFFH 280000H 287FFFH 278000H 27FFFFH 270000H 277FFFH 268000H 26FFFFH 260000H 267FFFH 258000H 25FFFFH 250000H 257FFFH 248000H 24FFFFH 240000H 247FFFH 238000H 23FFFFH 230000H 237FFFH 228000H 22FFFFH 220000H 227FFFH 218000H 21FFFFH 210000H 217FFFH 208000H 20FFFFH 200000H 207FFFH
BLOCK NUMBER ADDRESS RANGE
32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 1F8000H 1FFFFFH 1F0000H 1F7FFFH 1E8000H 1EFFFFH 1E0000H 1E7FFFH 1D8000H 1DFFFFH 1D0000H 1D7FFFH 1C8000H 1CFFFFH 1C0000H 1C7FFFH 1B8000H 1BFFFFH 1B0000H 1B7FFFH 1A8000H 1AFFFFH 1A0000H 1A7FFFH 198000H 19FFFFH 190000H 197FFFH 188000H 18FFFFH 180000H 187FFFH 178000H 17FFFFH 170000H 177FFFH 168000H 16FFFFH 160000H 167FFFH 158000H 15FFFFH 150000H 157FFFH 148000H 14FFFFH 140000H 147FFFH 138000H 13FFFFH 130000H 137FFFH 128000H 12FFFFH 120000H 127FFFH 118000H 11FFFFH 110000H 117FFFH 108000H 10FFFFH 100000H 107FFFH 0F8000H 0FFFFFH 0F0000H 0F7FFFH 0E8000H 0EFFFFH 0E0000H 0E7FFFH 0D8000H 0DFFFFH 0D0000H 0D7FFFH 0C8000H 0CFFFFH 0C0000H 0C7FFFH 0B8000H 0BFFFFH 0B0000H 0B7FFFH 0A8000H 0AFFFFH 0A0000H 0A7FFFH 098000H 09FFFFH 090000H 097FFFH 088000H 08FFFFH 080000H 087FFFH 078000H 07FFFFH 070000H 077FFFH 068000H 06FFFFH 060000H 067FFFH 058000H 05FFFFH 050000H 057FFFH 048000H 04FFFFH 040000H 047FFFH 038000H 03FFFFH 030000H 037FFFH 028000H 02FFFFH 020000H 027FFFH 018000H 01FFFFH 010000H 017FFFH 008000H 00FFFFH 000000H 007FFFH
PLANE3 (PARAMETER PLANE)
PLANE2 (UNIFORM PLANE)
Figure 3.1. Memory 64Mbit (Top Parameter)
PLANE0 (UNIFORM PLANE)
PLANE1 (UNIFORM PLANE)
Rev. 2.44
FUM00701
BLOCK NUMBER ADDRESS RANGE
32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 1F8000H 1FFFFFH 1F0000H 1F7FFFH 1E8000H 1EFFFFH 1E0000H 1E7FFFH 1D8000H 1DFFFFH 1D0000H 1D7FFFH 1C8000H 1CFFFFH 1C0000H 1C7FFFH 1B8000H 1BFFFFH 1B0000H 1B7FFFH 1A8000H 1AFFFFH 1A0000H 1A7FFFH 198000H 19FFFFH 190000H 197FFFH 188000H 18FFFFH 180000H 187FFFH 178000H 17FFFFH 170000H 177FFFH 168000H 16FFFFH 160000H 167FFFH 158000H 15FFFFH 150000H 157FFFH 148000H 14FFFFH 140000H 147FFFH 138000H 13FFFFH 130000H 137FFFH 128000H 12FFFFH 120000H 127FFFH 118000H 11FFFFH 110000H 117FFFH 108000H 10FFFFH 100000H 107FFFH 0F8000H 0FFFFFH 0F0000H 0F7FFFH 0E8000H 0EFFFFH 0E0000H 0E7FFFH 0D8000H 0DFFFFH 0D0000H 0D7FFFH 0C8000H 0CFFFFH 0C0000H 0C7FFFH 0B8000H 0BFFFFH 0B0000H 0B7FFFH 0A8000H 0AFFFFH 0A0000H 0A7FFFH 098000H 09FFFFH 090000H 097FFFH 088000H 08FFFFH 080000H 087FFFH 078000H 07FFFFH 070000H 077FFFH 068000H 06FFFFH 060000H 067FFFH 058000H 05FFFFH 050000H 057FFFH 048000H 04FFFFH 040000H 047FFFH 038000H 03FFFFH 030000H 037FFFH 028000H 02FFFFH 020000H 027FFFH 018000H 01FFFFH 010000H 017FFFH 008000H 00FFFFH 007000H 007FFFH 006000H 006FFFH 005000H 005FFFH 004000H 004FFFH 003000H 003FFFH 002000H 002FFFH 001000H 001FFFH 000000H 000FFFH
BLOCK NUMBER ADDRESS RANGE
32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 3F8000H 3FFFFFH 3F0000H 3F7FFFH 3E8000H 3EFFFFH 3E0000H 3E7FFFH 3D8000H 3DFFFFH 3D0000H 3D7FFFH 3C8000H 3CFFFFH 3C0000H 3C7FFFH 3B8000H 3BFFFFH 3B0000H 3B7FFFH 3A8000H 3AFFFFH 3A0000H 3A7FFFH 398000H 39FFFFH 390000H 397FFFH 388000H 38FFFFH 380000H 387FFFH 378000H 37FFFFH 370000H 377FFFH 368000H 36FFFFH 360000H 367FFFH 358000H 35FFFFH 350000H 357FFFH 348000H 34FFFFH 340000H 347FFFH 338000H 33FFFFH 330000H 337FFFH 328000H 32FFFFH 320000H 327FFFH 318000H 31FFFFH 310000H 317FFFH 308000H 30FFFFH 300000H 307FFFH 2F8000H 2FFFFFH 2F0000H 2F7FFFH 2E8000H 2EFFFFH 2E0000H 2E7FFFH 2D8000H 2DFFFFH 2D0000H 2D7FFFH 2C8000H 2CFFFFH 2C0000H 2C7FFFH 2B8000H 2BFFFFH 2B0000H 2B7FFFH 2A8000H 2AFFFFH 2A0000H 2A7FFFH 298000H 29FFFFH 290000H 297FFFH 288000H 28FFFFH 280000H 287FFFH 278000H 27FFFFH 270000H 277FFFH 268000H 26FFFFH 260000H 267FFFH 258000H 25FFFFH 250000H 257FFFH 248000H 24FFFFH 240000H 247FFFH 238000H 23FFFFH 230000H 237FFFH 228000H 22FFFFH 220000H 227FFFH 218000H 21FFFFH 210000H 217FFFH 208000H 20FFFFH 200000H 207FFFH
PLANE3 (UNIFORM PLANE)
PLANE2 (UNIFORM PLANE)
Figure 3.2. Memory 64Mbit (Bottom Parameter)
PLANE0 (PARAMETER PLANE)
PLANE1 (UNIFORM PLANE)
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[A21-A0] 000088H Customer Programmable Area 000085H 000084H Factory Programmed Area 000081H 000080H
Reserved Future Implementation (DQ15-DQ2)
Customer Programmable Area Lock (DQ1) Factory Programmed Area Lock (DQ0)
Figure Block Address Program(1, (The area outside 80H~88H cannot used.) NOTES: used 32M-bit device. Refer Table through Table block address read operation.
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Principles Operation
product includes on-chip (Write State Machine) automatically execute block erase, full chip erase, (page buffer) program program operation after writing proper command (Command User Interface).
lock configuration codes, device configuration codes, data within block query codes. block, user store interface software that initiates polls progress block erase (page buffer) program. Because product dual work function, data read from partition being erased programmed without using block erase suspend (page buffer) program suspend. When target partition being erased programmed, block erase suspend (page buffer) program suspend allows system software read/program data from/to blocks other than that which suspended.
Operation Mode after Power-up Reset Mode
After initial power-up reset mode (refer Operation Section device defaults following mode. Asynchronous read mode which 8-word page mode available Plane merged into partition parameter devices plane1-3 merged into partition bottom parameter devices. blocks default locked state lockeddown. Manipulation external memory control pins (CE#, OE#) allow read array, standby output disable modes.
Status Register Each Partition
product status registers each partition. 8bit status register available monitor partition state, erase program status. Status Register indicates status partition, WSM. Even status register SR.7 "1", occupied other partition when device partitions configuration. status register reports erase program operation each partition been successfully completed, not, indicates reason error. This register cannot set, only cleared writing Clear Status Register command resetting device.
Read, Program Erase Operation
Independent voltage, memory array, status register, identifier codes, block query codes accessed. also, set/clear block lock configuration partition configuration register available even voltage lower than VPPLK. Applying specified voltage VPPH1/2 enables successful block erase, (page buffer) program program operation. Applying specified voltage VPPH1 enables successful full chip erase operation. functions associated with altering memory contents, which block erase, full chip erase, (page buffer) program program, accessed verified through status register. Commands written using standard microprocessor write timings. Addresses data internally latched rising edge whichever goes high first during command write cycles. contents serve input WSM, which controls block erase, full chip erase, (page buffer) program program. internal algorithms regulated WSM, including pulse repetition, internal verification margining data. Writing appropriate command outputs array data, status register data, identifier codes,
Data Protection
Block lock block lock-down each block, protect data within block. RST# driven (VIL), voltage below write lock voltage (VLKO), voltage below write lock voltage (VPPLK), then write functions including program disabled. system should designed switch voltage below write lock voltage (VPPLK) read cycles. This scheme provides data protection hardware level. two-cycle command sequence architecture block erase, full chip erase, (page buffer) program, program, block lock configuration provides data protection software level against data alternation.
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Operation
system reads writes flash memory. cycles from flash memory conform standard microprocessor cycles. Table lists operation. function which available varies according each product. Refer specifications whether each function this document available not. function which described specifications used that product, even that function explained this section.
Standby
logic-high level (VIH) places product standby mode. standby mode, product substantially reduces power consumption because almost internal circuits inactive. DQ0-DQ15 outputs High state independent OE#. Even during block erase, full chip erase, (page buffer) program program, device continues operation consumes active power until completion operation.
Read Array
product five control pins (CE#, OE#, WE#, RST# WP#). When RST# VIH, read operations access memory array, status register, identifier codes, block query codes independent voltage VPP. device automatically initialized upon power-up device reset mode asynchronous read mode which 8-word page mode available. necessary, write appropriate read command (Read Array, Read Identifier codes/OTP, Read Query Read Status Register command) with partition address (Command User Interface). decodes partition address target partition appropriate read mode. Asynchronous page mode available only main array, that parameter blocks main blocks. Read operations status register, identifier codes, block query codes support single asynchronous read cycle. read data from product, RST# must VIH, VIL. device selection control, CE#-low enables selected memory device. data output (DQ0-DQ15) control OE#-low drives selected memory data onto bus.
Reset
Driving RST# logic-low level (VIL) places product reset mode. RST# held minimum tPLPH read modes, device deselected internal circuitry turned off. Outputs placed High state. Status register 80H. Time tPHQV required after return from reset mode until initial memory access outputs valid. After this wake-up interval, normal operation restored. device returns initial mode described Section 2.1. During block erase, full chip erase, (page buffer) program program mode, RST#-low will abort operation. Memory contents being altered longer valid; data partially erased programmed. Status register SR.7 remains until reset operation been completed. After RST# goes VIH, time tPHWL tPHEL required before another command written. with automated device, important assert RST# during system reset. When system comes reset, expects read data from flash memory. product allows proper initialization following system reset through RST# input. this application, RST# controlled same RESET# signal that resets system CPU. After return from reset mode, product automatically asynchronous read mode which 8-word page mode available. Delay time tPHQV required until memory access outputs valid.
Output Disable
With VIH, device outputs disabled. Output pins DQ15 placed high-impedance (High state.
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Table Operation(1, Mode Read Array Output Disable Standby Reset Read Identifier Codes/OTP Notes RST# Address Table through Table Section DQ0-15 DOUT High High High Table through Table Section RY/BY# High
Read Query Write
4,5,6
NOTES: Refer Characteristics. When VPPVPPLK, memory contents read, cannot altered. control pins addresses, VPPLK VPPH1/2 VPP. Characteristics VPPLK VPPH1/2 voltages. RST# GND±0.2V ensures lowest power consumption. Command writes involving block erase, (page buffer) program program reliably executed when VPP=VPPH1/2 specified voltage. Command writes involving full chip erase reliably executed when VPP=VPPH1 specified voltage. Refer Table valid during write operation. Never hold same timing. Refer Section more information about query code. RY/BY# when (Write State Machine) executing internal block erase, full chip erase, (page buffer) program program algorithms. High during when busy, block erase suspend mode (with program page buffer program inactive), (page buffer) program suspend mode, reset mode.
Read Identifier Codes/OTP
manufacturer code, device code, block lock configuration codes, partition configuration register code data within block read read identifier codes/OTP mode (see Table through Table Using manufacturer device codes, system automatically match device with proper algorithms.
Read Query
(Common Flash Interface) code, which called query code, read after writing Read Query command. address read query code should partition address which written with Read Query command. data structure contains information such block size, density, command electrical specifications (see Section this mode, read cycles retrieve information. return read array mode, write Read Array command (FFH) with partition address.
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Write Command
Except Full Chip Erase command, writing commands always requires word address, block address partition address. Before writing Block Erase command, Full Chip Erase command, (Page Buffer) Program command Program command, (Write State Machine) should ready used partition. Applying specified voltage VPPH1/2 enables successful block erase, (page buffer) program program with writing proper command address CUI. Applying specified voltage VPPH1 enables successful full chip erase with writing proper command CUI. Erase program operation occur only partition time. Other partitions must read modes. Block Erase command requires appropriate command address within block erased. Full Chip Erase command requires appropriate command. (Page Buffer) Program command requires appropriate command address location programmed. Set/Clear Block Lock Block Lock-down command requires appropriate command address within target block. Program command requires appropriate command address location programmed within block. Partition Configuration Register command requires appropriate command configuration register code presented addresses A0-A15. itself does occupy addressable memory location. When both (valid), command written address data latched rising edge WE#, whichever goes high first. command written standard microprocessor writing timing.
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Command Definitions
Operations device selected specific commands written (Command User Interface). Since commands partition-specific, important write commands within target partition's address range (see Table command which available varies according each product. Refer specifications whether each command this document available not. command which described specifications used that product, even that command explained this section.
Write Command 4.1.1 Using Dual Work Operation
product supports dual work operation customer store flash memory interface software internal memory array this device. enable flash memory interface software read time, partition which flash memory interface software stored must remain read array mode. Therefore, command except Read Array command, Full Chip Erase command (refer Section 4.1.3) Program command (refer Section 4.1.3) must written partition which flash memory interface software stored. example, when device divided into partitions such partition partition flash memory interface software stored partition command except commands mentioned above must written partition following describes reasons. addresses which written first cycle should same addresses which written second cycle. commands except Full Chip Erase command Program command require partition address. Partition Address (Refer Figure through Figure memory map) A20-A16 (32M-bit device) A21-A16 (64M-bit 128M-bit device) When command written, partition address must placed address A20-A16 A21A16 first, second subsequent command cycle.
Each command except Full Chip Erase command Program command affects only mode partition which command written. After first cycle command block erase (20H), program (40H 10H), set/clear block lock (60H), block lock-down (60H), partition configuration register (60H) written, target partition which command written into read status register mode. Subsequent read operations that partition output status register data partition. After first cycle command page buffer program (E8H) written, target partition which command written into read extended status register mode. Subsequent read operations that partition output extended status register data. After second cycle command block erase (D0H), program (data programmed), block lock (01H), clear block lock (D0H) block lock-down (2FH) written, target partition which command written remains read status register mode. After second cycle command partition configuration register (04H) written operation successfully completed, partitions return read array mode. operation completed successfully, target partition which command written remains read status register mode. After second subsequent cycle commands page buffer program written, target partition which command written into read status register mode. Subsequent read operations that partition output status register data partition.
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4.1.2 Using Dual Work Operation
this case, flash memory interface software must stored external area. command written partition. However, first second cycle command addresses should same commands require partition address.
accepted other partitions except full chip erase program operation. Since product provide dual work capability, partitions executing block erase (page buffer) program operation allowed read array mode memory array data within partitions read without suspending block erase (page buffer) program operation.
4.1.3 Full Chip Erase Program
Full chip erase program different from other modes, which dual work operation available. following describes reasons. After first cycle command full chip erase (30H) program (C0H) written partition, partitions into read status register mode. Subsequent read operations partition output status register data. memory array data cannot read these modes. After second cycle command full chip erase (D0H) program (data programmed) written partition, partitions remain read status register mode. Subsequent read operations partition output status register data. memory array data cannot read these modes. read memory array data, write Read Array command (FFH) after full chip erase program operation been successfully completed. When full chip erase program operation used, customer must store flash memory interface software that initiates polls progress full chip erase program external area.
Read Identifier Codes/OTP Command
read identifier codes/OTP mode initiated writing Read Identifier Codes/OTP command (90H) target partition. Read operations that partition output identifier codes data within block. terminate operation, write another valid command partition. this mode, manufacturer code, device code, block lock configuration codes, partition configuration register code data within block well block lock state read addresses shown Table through Table Once internal started block erase, full chip erase, (page buffer) program program partition, partition will recognize Read Identifier Codes/OTP command until completes operation unless suspended Block Erase Suspend (Page Buffer) Program Suspend command. However, Read Identifier Codes/ command accepted other partitions except full chip erase program operation. Like Read Array command, Read Identifier Codes/OTP command functions independently voltage RST# must VIH. read data block, important write addresses within area's address range (refer Table through Table Asynchronous page mode available reading identifier codes/OTP. Read operations identifier codes block support single asynchronous read cycle.
Read Array Command
Upon initial device power-up after reset mode, partitions device default asynchronous read mode which 8-word page mode available. Read Array command partition places partition read array mode. partition remains enabled read array mode until another valid command written partition. When RST# VIH, Read Array command valid independent voltage VPP. Once internal (Write State Machine) started block erase, full chip erase, (page buffer) program program partition, partition will recognize Read Array command until completes operation unless suspended Block Erase Suspend (Page Buffer) Program Suspend command. However, Read Array command
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Table Command Definitions(11) Command Read Array Read Identifier Codes/OTP Read Query Read Status Register Clear Status Register Block Erase Full Chip Erase Program Page Buffer Program Block Erase (Page Buffer) Program Suspend Block Erase (Page Buffer) Program Resume Block Lock Clear Block Lock Block Lock-down Program Partition Configuration Register Cycles Req'd First Cycle Notes Oper(1) Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Addr(2) PCRC Data Write Write Write Write Write PCRC Write Write Write Write Read Read Read Second Cycle Oper(1) Addr(2) Data(3)
NOTES: operations defined Table addresses which written first cycle should same addresses which written second cycle. X=Any valid address within device. PA=Address within selected partition. IA=Identifier codes address (See Table through Table QA=Query codes address. Refer Section details. BA=Address within block being erased, set/cleared block lock block lock-down bit. WA=Address memory location Program command first address Page Buffer Program command. OA=Address block read programmed (See Figure PCRC=Partition configuration register code presented address A0-A15. ID=Data read from identifier codes. (See Table through Table QD=Data read from query database. Refer Section details. SRD=Data read from status register. Table description status register bits. WD=Data programmed location Data latched rising edge (whichever goes high first) during command write cycles. OD=Data within block. Data latched rising edge (whichever goes high first) during command write cycles. N-1=N number words loaded into page buffer. Following Read Identifier Codes/OTP command, read operations access manufacturer code, device code, block lock configuration code, partition configuration register code data within block (See Table through Table Read Query command available reading (Common Flash Interface) information. Block erase, full chip erase (page buffer) program cannot executed when selected block locked. Unlocked block erased programmed when RST# VIH. Either recognized (Command User Interface) program setup. Following third cycle, input program sequential address write data times. Finally, input valid address within target block programmed confirm command (D0H). Refer Section 4.10
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details. program operation partition suspended erase operation other partition also suspended, suspended program operation should resumed first, then suspended erase operation should resumed next. Full chip erase program operations suspended. Program command accepted while block erase operation being suspended. Following Clear Block Lock command, block which locked-down unlocked when VIL. When VIH, lock-down disabled selected block unlocked regardless lock-down configuration. Commands other than those shown above reserved SHARP future device implementations should used.
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Table Identifier Codes Address Read Operation Code Manufacturer Code Device Code Block Lock Configuration Code Manufacturer Code Parameter Device Code Bottom Parameter Device Code Block Unlocked Block Locked Block Locked-Down Block Locked-Down Device Configuration Code Partition Configuration Register Lock 0006H 0080H 0081-0088H Block Address Address [A15-A0] 0000H 0001H 0001H Data [DQ15-DQ0] 00B0H Refer specifications PCRC OTP-LK Notes
NOTES: address A21, A20-A16 shown below table reading manufacturer code, device code, device configuration code data. parameter device parameter blocks plane3 (The highest address). Bottom parameter device parameter blocks plane0 (The lowest address). Block Address beginning location block address within partition which Read Identifier Codes/OTP command (90H) been written. DQ15-DQ2 reserved future implementation. PCRC=Partition Configuration Register Code. OTP-LK=OTP Block Lock configuration. OTP=OTP Block data. Refer specifications information product which more (CE#) pins which 32-bit interface.
Table Identifier Codes Address Read Operation Partition Configuration(1) (32M-bit device) Partition Configuration Register PCR.10 PCR.9 PCR.8 Address (32M-bit device) [A20-A16]
NOTES: address read identifier codes data dependent partition which selected when writing Read Identifier Codes/OTP command (90H). Refer Table partition configuration register.
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Table Identifier Codes Address Read Operation Partition Configuration(1) (64M-bit device) Partition Configuration Register PCR.10 PCR.9 PCR.8 Address (64M-bit device) [A21-A16]
NOTES: address read identifier codes data dependent partition which selected when writing Read Identifier Codes/OTP command (90H). Refer Table partition configuration register.
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FUM00701
Read Query Command
read query mode initiated writing Read Query command (98H) target partition. Read operations that partition output query code (Common Flash Interface code) shown Section terminate operation, write another valid command partition. Once internal started block erase, full chip erase, (page buffer) program program partition, partition will recognize Read Query command until completes operation unless suspended Block Erase Suspend (Page Buffer) Program Suspend command. However, Read Query command accepted other partitions except full chip erase program operation. Like Read Array command, Read Query command functions independently voltage RST# must Refer Section more information about query code. Asynchronous page mode available reading query code. Read operations query code support single asynchronous read cycle.
Asynchronous page mode available reading status register. Read operations status register support single asynchronous read cycle. During dual work operation, status register data read from partition which executing block erase (page buffer) program operation. memory array data read from other partitions which executing block erase (page buffer) program operation. partition accessed automatically identified according input address.
Clear Status Register Command
Status register bits SR.5, SR.4, SR.3 SR.1 that have been "1"s only cleared writing Clear Status Register command (50H). This command functions independently voltage. RST# must VIH. clear status register, write Clear Status Register command address within target partition CUI. Status register bits SR.5, SR.4, SR.3 SR.1 indicate various error conditions occurring after writing commands (see Table When erasing multiple blocks programming several words sequence, clear these bits before starting each operation. status register bits indicate error during sequence. After executing Clear Status Register command, partition returns read array mode. This command clears only status register addressed partition. During block erase suspend (page buffer) program suspend, Clear Status Register command invalid status register cannot cleared.
Read Status Register Command
status register read determine when block erase, full chip erase, (page buffer) program program been completed whether operation been successfully completed (see Table status register read time writing Read Status Register command (70H) target partition. Subsequent read operations that partition output status register data until another valid command written. status register contents latched falling edge whichever occurs later. This requires address setup time (tAVGL tAVEL) address hold time (tGLAX tELAX) from later falling edge CE#. must toggle before further reads update status register latch. Read Status Register command functions independently voltage RST# must VIH.
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Table Status Register Definition WSMS BESS BEFCES PBPOPS VPPS PBPSS NOTES:
SR.15 SR.8 RESERVED FUTURE ENHANCEMENTS SR.7 WRITE STATE MACHINE STATUS (WSMS) Ready Busy SR.6 BLOCK ERASE SUSPEND STATUS (BESS) Block Erase Suspended Block Erase Progress/Completed SR.5 BLOCK ERASE FULL CHIP ERASE STATUS (BEFCES) Error Block Erase Full Chip Erase Successful Block Erase Full Chip Erase SR.4 (PAGE BUFFER) PROGRAM PROGRAM STATUS (PBPOPS) Error (Page Buffer) Program Program Successful (Page Buffer) Program Program SR.3 STATUS (VPPS) Detect, Operation Abort SR.2 (PAGE BUFFER) PROGRAM SUSPEND STATUS (PBPSS) (Page Buffer) Program Suspended (Page Buffer) Program Progress/Completed SR.1 DEVICE PROTECT STATUS (DPS) Erase Program Attempted Locked Block, Operation Abort Unlocked SR.0 RESERVED FUTURE ENHANCEMENTS
Status Register indicates status partition, (Write State Machine). Even SR.7 "1", occupied other partition when device partitions configuration. Check SR.7 RY/BY# determine block erase, full chip erase, (page buffer) program program completion. SR.6 SR.1 invalid while SR.7="0". both SR.5 SR.4 "1"s after block erase, full chip erase, (page buffer) program, set/clear block lock bit, block lock-down bit, partition configuration register attempt, improper command sequence entered. SR.3 does provide continuous indication level. interrogates indicates level only after Block Erase, Full Chip Erase, (Page Buffer) Program Program command sequences. SR.3 guaranteed report accurate feedback when VPPVPPH1, VPPH2 VPPLK. SR.1 does provide continuous indication block lock bit. interrogates block lock only after Block Erase, Full Chip Erase, (Page Buffer) Program Program command sequences. informs system, depending attempted operation, block lock set. Reading block lock configuration codes after writing Read Identifier Codes/OTP command indicates block lock status. SR.15 SR.8 SR.0 reserved future should masked when polling status register.
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Table Extended Status Register Definition
XSR.15-8 RESERVED FUTURE ENHANCEMENTS XSR.7 STATE MACHINE STATUS (SMS) Page Buffer Program available Page Buffer Program available
NOTES: After issue Page Buffer Program command (E8H), XSR.7="1" indicates that entered command accepted. XSR.7 "0", command accepted next Page Buffer Program command (E8H) should issued again check page buffer available not.
XSR.15-8 XSR.6-0 reserved future XSR.6-0 RESERVED FUTURE ENHANCEMENTS should masked when polling extended status register.
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Block Erase Command
two-cycle Block Erase command initiates block erase addressed block within target partition. Read operations that partition output status register data partition. first cycle, command (20H) address within block erased written CUI, command (D0H) same address first cycle written second cycle. Once Block Erase command successfully written, automatically starts erase verification processes. data selected block erased (becomes FFFFH). system detect block erase completion analyzing output data status register SR.7. partition including block erased remains read status register mode after completion block erase operation until another command written CUI. Figure Figure show flowchart block erase operation. Check status register SR.5 block erase. block erase error detected, status register should cleared before system software attempts corrective actions. partition remains read status register mode until command written that partition. This two-cycle command sequence ensures that block contents accidentally erased. invalid Block Erase command sequence will result status register bits SR.5 SR.4 partition being operation will aborted. reliable block erase operation, apply specified voltage VPPH1/2 VPP. absence this voltage, block erase operations guaranteed. example, attempting block erase VPPVPPLK causes SR.5 SR.3 being "1". Also, successful block erase requires that selected block unlocked. When block erase attempted locked block, bits SR.5 SR.1 will "1". Block erase operation occur only partition time. Other partitions must read modes.
erase operation unlocked blocks, skipping locked blocks. full chip erase operation cannot suspended through erase suspend command (described later). system detect full chip erase completion analyzing output data status register SR.7. partitions remain read status register mode after completion full chip erase operation until another command written CUI. Figure Figure show flowchart full chip erase operation. aborts operation upon encountering error during full chip erase operation leaves remaining blocks erased. After full chip erase operation, check status register SR.5. When full chip erase error detected, partitions will "1". status registers partitions should cleared before system software attempts corrective actions. After that, retry Full Chip Erase command erase block block using Block Erase command. This two-cycle command sequence ensures that block contents accidentally erased. invalid Full Chip Erase command sequence will result status register bits SR.5 SR.4 partitions being operation will aborted. reliable full chip erase operation, apply specified voltage VPPH1 VPP. absence this voltage, full chip erase operations guaranteed. example, attempting full chip erase VPPVPPLK causes SR.5 SR.3 being "1". full chip erase operation with applying VPPH2 inhibited some products. Refer specifications whether full chip erase operation with applying VPPH2 available not. previously mentioned, Full Chip Erase command erases blocks except locked blocks. Unlike block erase, status register bits SR.5 SR.1 even locked block included. However, when blocks locked, bits SR.5 SR.1 operation will executed. error detected during full chip erase operation, error bits status registers partitions "1". This requires that Clear Status Register command written partitions clear error bits. Dual work operation available during full chip erase mode. memory array data cannot read this mode. return read array mode, write Read Array command (FFH) after completion full chip erase operation.
Full Chip Erase Command
two-cycle Full Chip Erase command erases unlocked blocks. Before writing this command, partitions should ready (WSM should occupied partition). first cycle, command (30H) written CUI, command (D0H) written second cycle. After writing command, device outputs status register data when address within device selected. automatically starts
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Start Status Check Partitions Desired Write 20H, Block Address Write D0H, Block Address Read Status Register, Block Address SR.7= Full Status Check Desired Block Erase Complete STATUS CHECK PROCEDURE PARTITIONS BEFORE BLOCK ERASE OPERATION Status Check Partitions Partition Address Partition Write 70H, Partition Address Read Status Register, Partition Address Suspend Block Erase Suspend Block Erase Loop
Operation
Command
Comments <First cycle> Data=20H Addr=Within Block Erased <Second cycle> Data=D0H Addr=Within Block Erased Status Register Data Addr=Within Block Erased Check SR.7 1=WSM Ready 0=WSM Busy
Write
Block Erase
Read
Standby
When subsequently erasing block, repeat above sequence. Full status check done after each block erase after sequence block erasures. Write after sequence block erasures place device read array mode.
Operation Write Read
Command
Comments
Read Status Data=70H Register Addr=Within Partition Status Register Data Addr=Within Partition Check SR.7 1=WSM Ready 0=WSM Busy Check SR.6 1=Block Erase Suspended 0=Block Erase Completed Check SR.2 1=(Page Buffer) Program Suspended 0=(Page Buffer) Program Completed
SR.7= SR.2=
Suspended (Page Buffer) Program should resumed first
Standby
Standby
SR.6= Another Partition Exist? Complete Partition Address Next Partition Suspended Block Erase should resumed first
Standby
Figure 5.1. Automated Block Erase Flowchart
Rev. 2.44
FUM00701
FULL STATUS CHECK PROCEDURE Read Status Register Data
Operation Standby
Command
Comments Check SR.3 1=VPP Error Detect Check SR.1 1=Device Protect Detect Block lock set. Check SR.4,5 Both 1=Command Sequence Error Check SR.5 1=Block Erase Error
SR.3= SR.1=
Range Error
Standby
Device Protect Error
Standby
SR.4,5= SR.5= Block Erase Successful Block Erase Error Command Sequence Error
Standby
SR.5, SR.4, SR.3 SR.1 only cleared Clear Status Register Command cases where multiple blocks erased before full status checked. error detected, clear status register before attempting retry other error recovery.
Figure 5.2. Automated Block Erase Flowchart (Continued)
Rev. 2.44
FUM00701
Start Status Check Partitions Desired Write
Operation
Command
Comments <First cycle> Data=30H Addr=X <Second cycle> Data=D0H Addr=X Status Register Data Addr=X Check SR.7 1=WSM Ready 0=WSM Busy
Write
Write
Full Chip Erase
Read Status Register
Read
SR.7= Full Status Check Desired Full Chip Erase Complete
Standby
Check status after full chip erase. Write after full chip erase place device read array mode.
STATUS CHECK PROCEDURE PARTITIONS BEFORE FULL CHIP ERASE OPERATION Status Check Partitions Partition Address Partition Write 70H, Partition Address Read Status Register, Partition Address
Operation Write Read
Command
Comments
Read Status Data=70H Register Addr=Within Partition Status Register Data Addr=Within Partition Check SR.7 1=WSM Ready 0=WSM Busy Check SR.6 1=Block Erase Suspended 0=Block Erase Completed Check SR.2 1=(Page Buffer) Program Suspended 0=(Page Buffer) Program Completed
Standby
SR.7= SR.2= SR.6= Another Partition Exist? Complete
Standby
Suspended (Page Buffer) Program should resumed first
Standby
Suspended Block Erase should resumed first
Partition Address Next Partition
Figure 6.1. Automated Full Chip Erase Flowchart
Rev. 2.44
FUM00701
FULL STATUS CHECK PROCEDURE Read Status Register Data
Operation Standby
Command
Comments Check SR.3 1=VPP Error Detect Check SR.1 1=Device Protect Detect Blocks locked. Check SR.4,5 Both 1=Command Sequence Error Check SR.5 1=Full Chip Erase Error
SR.3= SR.1=
Range Error
Standby
Device Protect Error
Standby
SR.4,5= SR.5= Full Chip Erase Successful Full Chip Erase Error Command Sequence Error
Standby
SR.5, SR.4, SR.3 SR.1 only cleared Clear Status Register Command cases where multiple blocks erased before full status checked. error detected, clear status register before attempting retry other error recovery.
Figure 6.2. Automated Full Chip Erase Flowchart (Continued)
Rev. 2.44
FUM00701
Program Command
two-cycle command sequence written target partition initiates word program operation. Read operations target partition programmed output status register data until another valid command written. first cycle, write command (standard alternate 10H) address memory location programmed, followed second write that specifies address data. then takes over, controlling internal word program algorithm. system detect word program completion analyzing output data status register SR.7. Figure Figure show program flowchart. internal verify only detects errors "1"s that successfully programmed "0"s. Check status register SR.4 word program. word program error detected, status register should cleared before system software attempts corrective actions. partition remains read status register mode until receives another command. reliable word program operation, apply specified voltage VPPH1/2 VPP. absence this voltage, word program operations guaranteed. example, attempting word program VPPVPPLK causes SR.4 SR.3 being "1". Also, successful word program requires selected block unlocked. When word program attempted locked block, bits SR.4 SR.1 will "1". Word program operation occur only partition time. Other partitions must read modes.
4.10 Page Buffer Program Command
product 16-word page buffer, which perform fast sequential programming words. However, this 16-word address must inside every 4K-word address range XXX000H-XXXFFFH, shown Figure When programming across this 4K-word address range, sequence error occurs status register bits SR.5 SR.4 "1". data once loaded page buffer programmed flash array when confirm command (D0H) written. flowchart Figure Figure 9.2. page buffer program executed least fourcycle 19-cycle command sequence. First, write Page Buffer Program setup command (E8H) start address partition's CUI. this point, read operations target partition programmed output extended status register data (see Table 10). Check extended status register data. When XSR.7 "1", setup command written valid. Then, second cycle, write word count [N]-1 start address number words programmed total. That when number word, write (00H); words, write (0FH). word count [N]-1 must less than equal 0FH. Attempting write more than word count causes sequence error status register bits SR.5 SR.4 "1". After writing word count [N]-1, read operations target partition programmed output status register data. third cycle following write [N]-1, write first data programmed start address partition's CUI. Lower bits (A0-A3) start address also correspond page buffer address data stored page buffer. fourth subsequent cycles, write additional data address, depending count. subsequent address must within start address plus count. After writing word data, write confirm command (D0H) address within target block programmed last cycle. This initiates being transferring data from page buffer flash array. command other than confirm command (D0H) written, sequence error occurs status register bits SR.5 SR.4 partition "1". When data transferred from page buffer flash array, status register SR.7 "0". Then, target partition page buffer program busy mode.
Rev. 2.44
FUM00701
Page Buffer Program command attempted past erase block boundary, device will program data flash array erase block boundary then stop programming. status register bits SR.5 SR.4 will (command sequence error). SR.5 SR.4 should cleared before writing next command. reliable page buffer program operation, apply specified voltage VPPH1/2 VPP. absence this voltage, page buffer program operations guaranteed. example, attempting page buffer program VPPVPPLK causes SR.4 SR.3 being "1". Also, successful page buffer program requires selected block unlocked. When page buffer program attempted locked block, bits SR.4 SR.1 will "1".
During page buffer program, dual work operation available. array data read from partitions being programmed. Page buffer program operation occur only partition time. Other partitions must read modes.
ADDRESS RANGE
4K-Word 4K-Word 16-Word Page Buffer 4K-Word 4K-Word 4K-Word 4K-Word 4K-Word 4K-Word XX7000H XX7FFFH XX6000H XX6FFFH XX5000H XX5FFFH XX4000H XX4FFFH XX3000H XX3FFFH XX2000H XX2FFFH XX1000H XX1FFFH XX0000H XX0FFFH
Figure 32K-Word Block
Rev. 2.44
FUM00701
Start Status Check Partitions Desired Write 10H, Word Address Write Word Data Address Read Status Register, Word Address SR.7= Full Status Check Desired Suspend Word Program Suspend Word Program Loop
Operation
Command
Comments <First cycle> Data=40H Addr=Location Programmed <Second cycle> Data= Data Programmed Addr=Location Programmed Status Register Data Addr=Location Programmed Check SR.7 1=WSM Ready 0=WSM Busy
Write
Word Program
Read
Standby
Word Program Complete STATUS CHECK PROCEDURE PARTITIONS BEFORE WORD PROGRAM OPERATION Status Check Partitions Partition Address Partition Write 70H, Partition Address Read Status Register, Partition Address
Repeat above sequence subsequent word programs. full status check done after each word program, after sequence word programs. Write after sequence word programs place device read array mode.
Operation Write
Command
Comments
Read Status Data=70H Register Addr=Within Partition Status Register Data Addr=Within Partition Check SR.7 1=WSM Ready 0=WSM Busy Check SR.2 1=Program Suspended 0=Program Completed
SR.7= SR.2= Another Partition Exist? Complete
Read
Suspended Program Operation should resumed first
Standby
Partition Address Next Partition
Standby
Figure 8.1. Automated Program Flowchart
Rev. 2.44
FUM00701
FULL STATUS CHECK PROCEDURE Read Status Register Data
Operation Standby
Command
Comments Check SR.3 1=VPP Error Detect Check SR.1 1=Device Protect Detect Block lock set. Check SR.4 1=Word Program Error
SR.3= SR.1= SR.4= Word Program Successful
Range Error
Standby
Device Protect Error
Standby
Word Program Error
SR.4, SR.3 SR.1 only cleared Clear Status Register Command cases where multiple locations programmed before full status checked. error detected, clear status register before attempting retry other error recovery.
Figure 8.2. Automated Program Flowchart (Continued)
Rev. 2.44
FUM00701
Start Status Check Partitions Desired Write E8H, Start Address Read Extended Status Register XSR.7= Write [Word Count N]-1, Start Address Write Buffer Data, Start Address Write Buffer Time
Operation Write
Command
Comments
<First cycle> Page Buffer Data=E8H Program Addr=Start Address Extended Status Register Data Check XSR.7 1=Page Buffer Program Ready 0=Page Buffer Program Busy <Second cycle> Data=[Word Count N]-1 Addr=Start Address <Third cycle> Data=Buffer Data Addr=Start Address
Read
Standby
Write (Note Write (Note
Abort Buffer Write Command? Write Buffer Data, Address X=X+1 Page Buffer Program Abort Write Another Block Address
Page Buffer <(N+2)th cycle> Program Write Data=Buffer Data (Note Addr=Sequential Address following start address Write <(N+3)th cycle> Data=D0H Addr=Within Block Status Register Data Addr=Within Partition Check SR.7 1=WSM Ready 0=WSM Busy
Read
Standby
Write
Read Status Register, Partition Address Suspend Page Buffer Program Loop
SR.7= Full Status Check Desired Page Buffer Program Complete Suspend Page Buffer Program
Word count values DQ0-7 loaded into count register. Write Buffer contents will programmed start address. Align start address Write Buffer boundary maximum programming performance. device aborts Page Buffer Program command current address outside original block address. Status Register indicates "improper command sequence" Page Buffer Program command aborted. Follow this with Clear Status Register command. full status check done after each page buffer program, after sequence page buffer programs. Write after last page buffer program operation place device read array mode.
Figure 9.1. Automated Page Buffer Program Flowchart
Rev. 2.44
FUM00701
STATUS CHECK PROCEDURE PARTITIONS BEFORE PAGE BUFFER PROGRAM OPERATION Status Check Partitions Partition Address Partition
Operation Write Read
Command
Comments
Read Status Data=70H Register Addr=Within Partition Status Register Data Addr=Within Partition Check SR.7 1=WSM Ready 0=WSM Busy Check SR.2 1=Program Suspended 0=Program Completed
Write 70H, Partition Address Read Status Register, Partition Address
Standby
SR.7= SR.2= Another Partition Exist? Complete
Standby
Suspended Program Operation should resumed first
Partition Address Next Partition
FULL STATUS CHECK PROCEDURE PAGE BUFFER PROGRAM OPERATION Read Status Register Data
Operation Standby
Command
Comments Check SR.3 1=VPP Error Detect Check SR.1 1=Device Protect Detect Block lock set. Check SR.4,5 Both 1=Command Sequence Error Check SR.4 1=Page Buffer Program Error
SR.3= SR.1= SR.4,5= SR.4=
Range Error
Standby
Device Protect Error
Standby
Command Sequence Error
Standby
Page Buffer Program Error
Page Buffer Program Successful
SR.5,SR.4,SR.3 SR.1 only cleared Clear Status Register command cases where multiple locations programmed before full status checked. error detected, clear Status Register before attempting retry other error recovery.
Figure 9.2. Automated Page Buffer Program Flowchart (Continued)
Rev. 2.44
FUM00701
4.11 Block Erase Suspend Command Block Erase Resume Command
Block Erase Suspend command (B0H) allows block erase interruption read program data blocks other than that which suspended. This command valid block erase operation full chip erase operation suspended. Once block erase process starts partition, writing Block Erase Suspend command partition requests that suspends block erase sequence predetermined point algorithm. Read operations target partition after writing Block Erase Suspend command access status register. Status register bits SR.7 SR.6 indicate block erase operation been suspended (both will "1"). Specification tWHRH2 tEHRH2 defines block erase suspend latency. When Block Erase Suspend command written after completion block erase operation, partition returns read array mode. Therefore, Read Status Register command (70H) must written target partition after writing Block Erase Suspend command. status register bits SR.7 SR.6 "1", block erase been suspended. this point, Read Array command written read data from blocks other than that which suspended. (Page Buffer) Program command sequence also written during block erase suspend program data other blocks. Using (Page Buffer) Program Suspend command (see Section 4.12), program operation also suspended during block erase suspend. During word program operation with block erase suspended, status register SR.7 will return "0". However, SR.6 will remain indicate block erase suspend status. Page Buffer Program setup command (E8H) written target partition during block erase suspend which SR.7 SR.6 "1", read operations target partition programmed output extended status register data. read extended status register mode, XSR.7 only valid, which indicates that written command (E8H) available, other bits (from XSR.6 XSR.0) invalid (see Table 10). When writing word count [N]-1 start address next command cycle, target partition returns read status register mode status register bits SR.7 SR.6 "1". After Page Buffer Program confirm command (D0H) written, status register SR.7 will return
"0". However, SR.6 will remain indicate block erase suspend status. valid commands while block erase suspended Read Array, Read Identifier Codes/OTP, Read Query, Read Status Register, (Page Buffer) Program, Block Lock Bit, Clear Block Lock Bit, Block Lock-down Block Erase Resume command. commands other than those mentioned above accepted should used during block erase suspend. resume block erase operation, write Block Erase Resume command (D0H) partition. Status Register bits SR.7 SR.6 will automatically cleared. After Block Erase Resume command written, target partition automatically outputs status register data when read. must remain VPPH1/2 same level before block erase suspended) while block erase suspended. RST# must remain must also remain same level before block erase suspended). Block erase cannot resume until (page buffer) program operation initiated during block erase suspend completed. Figure shows block erase suspend block erase resume flowchart. interval time from Block Erase Resume command subsequent Block Erase Suspend command shorter than tERES sequence repeated, block erase operation finished.
Rev. 2.44
FUM00701
Start Write B0H, Partition Address Write 70H, Partition Address
Operation Write Write
Command
Comments
Block Erase Data=B0H Suspend Addr=Within Partition Read Status Data=70H Register Addr=Within Partition Status Register Data Addr=Within Partition Check SR.7 1=WSM Ready 0=WSM Busy Check SR.6 1=Block Erase Suspended 0=Block Erase Completed Data=D0H Block Erase Addr=Within Block Resume Suspended
Read Status Register, Partition Address
Read
SR.7= SR.6= Read Word/Page Buffer Read Program Word/Page Buffer Program Done? Write Block Erase Resumed Write Word/Page Buffer Program Loop Block Erase Completed
Standby
Standby
Write
Read Array Data
Read Array Data
Figure Block Erase Suspend Block Erase Resume Flowchart
Rev. 2.44
FUM00701
4.12 (Page Buffer) Program Suspend Command (Page Buffer) Program Resume Command
(Page Buffer) Program Suspend command (B0H) allows word page buffer program interruption read data from locations other than that which suspended. Once (page buffer) program process starts partition, writing (Page Buffer) Program Suspend command partition requests that suspends (page buffer) program sequence predetermined point algorithm. Read operations target partition after writing (Page Buffer) Program Suspend command access status register. Status register bits SR.7 SR.2 indicate (page buffer) program operation been suspended (both will "1"). Specification tWHRH1 tEHRH1 defines (page buffer) program suspend latency. When (Page Buffer) Program Suspend command written after completion (page buffer) program operation, partition returns read array mode. Therefore, Read Status Register command (70H) must written target partition after writing (Page Buffer) Program Suspend command. status register bits SR.7 SR.2 "1", (page buffer) program been suspended. this point, Read Array command written read data from locations other than that which suspended. valid commands while (page buffer) program suspended Read Array, Read Identifier Codes/OTP, Read Query, Read Status Register (Page Buffer) Program Resume command. commands other than those mentioned above accepted should used. example, block erase operation cannot executed during (page buffer) program suspend.
resume (page buffer) program operation, write (Page Buffer) Program Resume command (D0H) partition. Status Register bits SR.7 SR.2 will automatically cleared. After (Page Buffer) Program Resume command written, target partition automatically outputs status register data when read. must remain VPPH1/2 same level before (page buffer) program suspended) while (page buffer) program suspended. RST# must remain must also remain same level before (page buffer) program suspended). Figure shows (page buffer) program suspend (page buffer) program resume flowchart. interval time from (Page Buffer) Program Resume command subsequent (Page Buffer) Program Suspend command short sequence repeated, (page buffer) program operation finished. After (Page Buffer) Program Suspend command written partition suspend program operation while partition block erase suspend mode, (Page Buffer) Program Resume command should written partition first resume suspended (page buffer) program operation. After that, Block Erase Resume command written partition resume suspended block erase operation. Block Erase Resume command written before (Page Buffer) Program Resume command, Block Erase Resume command ignored partition which Block Erase Resume command written read array mode with block erase suspended.
Rev. 2.44
FUM00701
Start Write B0H, Partition Address Write 70H, Partition Address Read Status Register, Partition Address
Operation Write
Command
Comments
(Page Buffer) Data=B0H Program Addr=Within Partition Suspend Read Status Data=70H Register Addr=Within Partition Status Register Data Addr=Within Partition Check SR.7 1=WSM Ready 0=WSM Busy Check SR.2 1=(Page Buffer) Program Suspended 0=(Page Buffer) Program Completed Data=FFH Addr=Within Partition Read array locations from block other than that being programmed (Page Buffer) Data=D0H Program Addr=Location Resume Suspended
Write Read
SR.7= SR.2= Write
Standby
(Page Buffer) Program Completed
Standby
Read Array Data
Write
Done? Write (Page Buffer) Program Resumed Write
Read
Write
Read Array Data
Figure (Page Buffer) Program Suspend (Page Buffer) Program Resume Flowchart
Rev. 2.44
FUM00701
4.13 Block Lock Command
product provided with block lock each parameter block main block. features block lock follows: block independently locked setting block lock bit. time required block locking less than minimum command cycle time (minimum time from rising edge write command next rising edge WE#). Block erase, full chip erase (page buffer) program locked block cannot executed (see Table Table 12). power-up device reset, blocks default locked state, regardless states before power-off reset operation. (Lock volatile.) Block Lock command two-cycle command. first cycle, command (60H) address within block locked written target partition. second cycle, command (01H) same address first cycle written. Read operations target partition output status register
data until another valid command written. After writing second cycle command, block lock within minimum command cycle time corresponding block locked. check lock status, write Read Identifier Codes/OTP command (90H) address within target block. Subsequent reads Block Base Address (see Table through Table will output lock/unlock status that block. lock/unlock status represented output DQ0. output "1", block lock correctly. Figure shows block lock flowchart. two-cycle command sequence ensures that block accidentally locked. invalid Block Lock command sequence will result both status register bits SR.5 SR.4 being operation will executed. Block Lock command available when power supply voltage specified level, independent voltage VPP. power-up device reset, since blocks default locked state, write Clear Block Lock command described later clear block lock before erase program operation.
Table Functions Block Lock(5) Block Lock-Down Current State State [000] [001](3) [011] [100] [101](3) [110](4) [111] DQ1(1) DQ0(1) State Name Unlocked Locked Locked-down Unlocked Locked Lock-down Disable Lock-down Disable Erase/Program Allowed
NOTES: DQ0=1: block locked; DQ0=0: block unlocked. DQ1=1: block locked-down; DQ1=0: block locked-down. Erase program general terms, respectively, express: block erase, full chip erase (page buffer) program operations. power-up device reset, blocks default locked state locked-down, that [001] (WP#=0) [101] (WP#=1), regardless states before power-off reset operation. When driven [110] state, state changes [011] blocks automatically locked. (One Time Program) block lock function which different from those described above.
Rev. 2.44
FUM00701
Table Block Locking State Transitions upon Command Write(4) Current State State [000] [001] [011] [100] [101] [110] [111] Result after Lock Command Written (Next State) Lock(1) [001] Change(3) Change [101] Change [111] Change Clear Lock(1) Change [000] Change Change [100] Change [110] Lock-down(1) [011](2) [011] Change [111](2) [111] [111](2) Change
NOTES: "Set Lock" means Block Lock command, "Clear Lock" means Clear Block Lock command "Set Lock-down" means Block Lock-Down command. When Block Lock-Down command written unlocked block (DQ0=0), corresponding block locked-down automatically locked same time. Change" means that state remains unchanged after command written. this state transitions table, assumes that changed fixed VIH.
Table Block Locking State Transitions upon Transition(4) Current State Previous State State [110](2) Other than [110](2) [000] [001] [011] [100] [101] [110] [111] Result after Transition (Next State) WP#=01(1) [100] [101] [110] [111] WP#=10(1) [000] [001] [011](3) [011]
NOTES: "WP#=01" means that driven "WP#=10" means that driven VIL. State transition from current state [011] next state depends previous state. When driven [110] state, state changes [011] blocks automatically locked. this state transitions table, assumes that lock configuration commands written previous, current next state.
Rev. 2.44
FUM00701
Start Status Check Partitions Desired Write 60H, Block Address Write 01H/2FH, Block Address Read Status Register, Partition Address Command Sequence Error
Operation
Command
Comments <First cycle> Data=60H Addr=Within Block Locked Locked-down
Write
Block Lock Bit/Set Block Lock- <Second cycle> Data= (Lock Bit), down 2FH(Lock-down Bit) Addr=Within Block Locked Locked-down Status Register Data Addr=Within Partition Check SR.4, Both 1=Command Sequence Error Read Code Data=90H Addr=Within Partition Lock Lock-down Data Addr=Block Address+2 (see Table through Table Check DQ0/DQ1 1=Lock Lock-down
SR.4,5= Write 90H, Partition Address Read Block Address+2
Read
Standby
Write
DQ0/DQ1=
Read
Lock/Lock-down Complete STATUS CHECK PROCEDURE PARTITIONS BEFORE LOCK/LOCK-DOWN OPERATION Status Check Partitions Partition Address Partition Write 70H, Partition Address Read Status Register, Partition Address
Standby
SR.7= Another Partition Exist? Complete
Repeat subsequent block lock/lock-down bit. Lock status check done after each block lock/ lock-down operation after sequence block lock/lock-down operations. SR.5 SR.4 only cleared Clear Status Register command cases where multiple block lock/ lock-down bits before full status checked. error detected, clear status register before attempting retry other error recovery. Write after sequence block lock/lock-down operations place device read array mode.
Partition Address Next Partition
Operation Write Read
Command
Comments
Read Status Data=70H Register Addr=Within Partition Status Register Data Addr=Within Partition Check SR.7 1=WSM Ready 0=WSM Busy
Standby
Figure Block Lock Block Lock-down Flowchart
Rev. 2.44
FUM00701
4.14 Clear Block Lock Command
locked block unlocked writing Clear Block Lock command. features clear block lock follows: block independently unlocked clearing block lock bit. time required unlocked less than minimum command cycle time (minimum time from rising edge write command next rising edge WE#). Block erase, full chip erase (page buffer) program unlocked block executed (see Table Table 12). Clear Block Lock command two-cycle command. first cycle, command (60H) address within block unlocked written target partition. second cycle, command (D0H) same address first cycle written. Read operations target partition output status register data until another valid command written. After writing second cycle command, block lock cleared within minimum command cycle time corresponding block unlocked. check unlock status, write Read Identifier Codes/OTP command (90H) address within target block. Subsequent reads Block Base Address (see Table through Table will output lock/unlock status that block. lock/unlock status represented output DQ0. output "0", block lock cleared correctly. Figure shows clear block lock flowchart. two-cycle command sequence ensures that block accidentally unlocked. invalid Clear Block Lock command sequence will result both status register bits SR.5 SR.4 being operation will executed. Clear Block Lock command available when power supply voltage specified level, independent voltage VPP.
4.15 Block Lock-Down Command
block lock-down bit, when set, increases security data protection. block lock-down following functions. block independently locked-down setting block lock-down bit. time required locked-down less than minimum command cycle time (minimum time from rising edge write command next rising edge WE#). Locked-down block automatically locked regardless VIH. When VIL, locked-down blocks protected from lock status changes. When VIH, lock-down bits disabled locked-down blocks individually unlocked software command. These blocks then re-locked unlocked desired while remains VIH. When goes VIL, blocks that were previously marked lock-down return locked locked-down state regardless changes made while (see Table 13). power-up device reset, blocks lockeddown regardless states before power-off reset operation. (Lock-down volatile.) Lock-down cannot cleared software, only power-off device reset. Block Lock-down command two-cycle command. first cycle, command (60H) address within block locked-down written target partition. second cycle, command (2FH) same address first cycle written. Read operations target partition output status register data until another valid command written. After writing second cycle command, block lock-down within minimum command cycle time corresponding block locked-down. check lockdown status, write Read Identifier Codes/OTP command (90H) address within target block. Subsequent reads Block Base Address (see Table through Table will output lock/unlock status that block. lock-down status represented output DQ1. output "1", block lock-down correctly. Figure shows block lock-down flowchart.
Rev. 2.44
FUM00701
Start Status Check Partitions Desired Write 60H, Block Address Write D0H, Block Address Read Status Register, Partition Address Command Sequence Error
Operation
Command
Comments
Write
<First cycle> Data=60H Addr=Within Block Clear Block Unlocked Lock <Second cycle> Data= Addr=Within Block Unlocked Status Register Data Addr=Within Partition Check SR.4, Both 1=Command Sequence Error Read Code Data=90H Addr=Within Partition Lock Data Addr=Block Address+2 (see Table through Table Check 0=Lock Cleared
SR.4,5= Write 90H, Partition Address Read Block Address+2
Read
Standby
Write
DQ0= Clear Lock Complete
Read
Standby
STATUS CHECK PROCEDURE PARTITIONS BEFORE CLEAR LOCK OPERATION Status Check Partitions Partition Address Partition Write 70H, Partition Address Read Status Register, Partition Address
Repeat subsequent clear block lock bit. Lock status check done after each clear block lock operation after sequence clear block lock operations. SR.5 SR.4 only cleared Clear Status Register command cases where multiple block lock bits cleared before full status checked. error detected, clear status register before attempting retry other error recovery. Write after sequence clear block lock operations place device read array mode.
SR.7=
Operation Write
Command
Comments
Another Partition Exist? Complete
Partition Address Next Partition
Read Status Data=70H Register Addr=Within Partition Status Register Data Addr=Within Partition Check SR.7 1=WSM Ready 0=WSM Busy
Read
Standby
Figure Clear Block Lock Flowchart
Rev. 2.44
FUM00701
two-cycle command sequence ensures that block accidentally locked-down. invalid Block Lock-down command sequence will result both status register bits SR.5 SR.4 being operation will executed. Block Lock-down command available when power supply voltage specified level, independent voltage VPP. power-up device reset, since blocks lockeddown, write Block Lock-down command necessary. While VIH, lock-down bits disabled cleared. Once block locked-down, cannot cleared until power-off device reset.
4.16 Program Command
program executed two-cycle command sequence. first cycle, command (C0H) address within block (see Figure written, followed second write that specifies address data. After writing command, device outputs status register data when address within device selected. then takes over, controlling internal program algorithm. system detect program completion analyzing output data status register SR.7. Figure 14.1 Figure 14.2 show program flowchart. address written command cycle must address within block (refer Figure Writing address outside block will cause program error status register SR.4 "1". Clear status register before writing next command. internal verify only detects errors "1"s that successfully programmed "0"s. Check status register SR.4 program. program error detected, status register should cleared before system software attempts corrective actions. reliable program operation, apply specified voltage VPPH1/2 VPP. absence this voltage, program operations guaranteed. example, attempting program VPPVPPLK causes SR.4 SR.3 being "1". program operation locked area causes SR.4 SR.1 being operation will executed. program cannot suspended through (Page Buffer) Program Suspend command (B0H). Even (Page Buffer) Program Suspend command written during program operation, suspend command will ignored. error detected during program operation, error bits status registers partitions "1". This requires that Clear Status Register command written partitions clear error bits. Dual work operation available while program mode, memory array data cannot read even that operation been completed. return read array mode, write Read Array command (FFH) partition's after completion program operation.
Rev. 2.44
FUM00701
Start Status Check Partitions Desired Write C0H, Address Write Data Address Read Status Register
Operation
Command
Comments <First cycle> Data=C0H Addr=Location Programmed
Write
Write
Program <Second cycle> Data=Data Programmed Addr=Location Programmed Status Register Data Addr=X Check SR.7 1=WSM Ready 0=WSM Busy
SR.7= Full Status Check Desired Program Complete
Read
Standby
STATUS CHECK PROCEDURE PARTITIONS BEFORE PROGRAM OPERATION Status Check Partitions Partition Address Partition Write 70H, Partition Address Read Status Register, Partition Address
Repeat subsequent program. full status check done after each program, after sequence programs. Write after program operation place device read array mode.
Operation Write Read
Command
Comments
Read Status Data=70H Register Addr=Within Partition Status Register Data Addr=Within Partition Check SR.7 1=WSM Ready 0=WSM Busy
SR.7= Another Partition Exist? Complete
Standby
Partition Address Next Partition
Figure 14.1. Automated Program Flowchart
Rev. 2.44
FUM00701
FULL STATUS CHECK PROCEDURE Read Status Register Data
Operation Standby Standby
Command
Comments Check SR.3 1=VPP Error Detect Check SR.1 1=Device Protect Detect Check SR.4 1=OTP Program Error
SR.3= SR.1= SR.4= Program Successful
Range Error
Device Protect Error
Standby
Program Error
SR.4, SR.3 SR.1 only cleared Clear Status Register command cases where multiple locations programmed before full status checked. error detected, clear status register before attempting retry other error recovery.
Figure 14.2. Automated Program Flowchart (Continued)
Rev. 2.44
FUM00701
4.17 Partition Configuration Register Command
Partition Configuration Register (PCR) bits writing Partition Configuration Register command device. This operation initiated two-cycle command sequence. partition configuration register configured writing command with partition configuration register code. first cycle, command (60H) partition configuration register code written. second cycle, command (04H) same address first cycle written. partition configuration register code placed address bus, latched rising edge CE#, (whichever occurs first). partition configuration register code sets partition boundaries. This command functions independently voltage. RST# must VIH. After executing this command, device returns read array mode status registers cleared. Figure shows partition configuration register flowchart. NOTES: partition configuration register code read Read Identifier Codes/OTP command (90H). Address 0006H contains partition configuration register code (see Table through Table Partition configuration after device power-up reset follows. (Partition configuration register bits volatile.) Plane merged into partition. (top parameter device) Plane1-3 merged into partition. (bottom parameter device)
4.17.1 Partition Configuration Register
partition configuration register writing Partition Configuration Register command, previously described. following summarizes partition configuration register. first cycle Partition Configuration Register command, write following data address. Data (Command) DQ15-DQ8=Any data. These bits affect operation. DQ7-DQ0=60H Address A20-A16=Partition address (32M-bit device). A21-A16=Partition address (64M-bit 128M-bit device). partition address must address within partition which flash memory interface software stored. A15-A11=Any address. These bits affect operation. A10-A8=Partition configuration register code. These bits determine partiton boundaries shown Table Figure A7-A0=Any address. These bits affect operation. After writing first cycle command (60H), target partition which command written into read status register mode. Subsequent read operations that partition output status register data partition. second cycle Partition Configuration Register command, write following data address. Data (Command) DQ15-DQ8=Any data. These bits affect operation. DQ7-DQ0=04H Address (All addresses same first cycle.) A20-A16=Partition address (32M-bit device). A21-A16=Partition address (64M-bit 128M-bit device). partition address must address within partition which flash memory interface software stored.
Rev. 2.44
FUM00701
A15-A11=Any address. These bits affect operation. A10-A8=Partition configuration register code. These bits determine partiton boundaries shown Table Figure A7-A0=Any address. These bits affect operation. After writing second cycle command (04H) operation successfully completed, partitions return read array mode. operation completed successfully, target partition which command written remains read status register mode. After second cycle command, write Read Status Register command (70H) partition which Partition Configuration Register command written. Then, check status register partition clarify that command sequence error detected. command sequence error detected (SR.5, SR.4="1"), write Clear Status Register command (50H) partition which error detected. After that, reattempt sequence setting partition configuration register. command sequence error detected, write Read Identifier Codes/OTP command (90H) partition which Partition Configuration Register command written. Subsequent read operations following address output partition configuration register code. A20-A16=Partition address (32M-bit device). A21-A16=Partition address (64M-bit 128M-bit device). partition address must address within partition which Read Identifier Codes/ command written. A15-A0=0006H Check partition configuration register code data DQ10-DQ8 clarify that partition boundaries correctly set. partition boundaries correctly, reattempt sequence setting partition configuration register.
4.17.2 Partition Configuration
partition configuration shown Table determines partiton boundaries dual work (simultaneous read while erase/program) operation. partition boundaries plane boundaries. partition configuration register bits PCR.10-8 (PC.2-0) "001", partition boundary between plane0 plane1. There partitions this configuration. Plane1-3 merged partition. Status registers plane1-3 also merged one. partition configuration register bits "101", partition boundaries between plane0 plane1 between plane2 plane3. There three partitions this configuration. Plane1-2 merged partition. partition configuration register bits "111", there four partitions. Figure illustrates various partition configuration.
Rev. 2.44
FUM00701
Table Partition Configuration Register Definition
PCR.15-11 RESERVED FUTURE ENHANCEMENTS PCR.10-8 PARTITION CONFIGURATION (PC2-0) partitioning. Dual Work allowed. Plane1-3 merged into partition. (default bottom parameter device) Plane Plane2-3 merged into partition respectively. Plane merged into partition. (default parameter device) Plane merged into partition. There three partitions this configuration. Dual work operation available between partitions. Plane merged into partition. There three partitions this configuration. Dual work operation available between partitions. Plane merged into partition. There three partitions this configuration. Dual work operation available between partitions.
PC1PC0
There four partitions this configuration. Each plane corresponds each partition respectively. Dual work operation available between partitions. PCR.7-0 RESERVED FUTURE ENHANCEMENTS NOTES: After power-up device reset, PCR10-8 (PC2-0) "001" bottom parameter device "100" parameter device. Figure detail partition configuration. PCR.15-11 PCR.7-0 reserved future should masked when checking partition configuration register.
PARTITIONING DUAL WORK PARTITION0
PLANE3 PLANE2 PLANE1 PLANE0
PC1PC0
PARTITIONING DUAL WORK PARTITION2 PARTITION1 PARTITION0
PLANE3 PLANE2 PLANE1 PLANE0
PARTITION1
PLANE3 PLANE2 PLANE1
PARTITION0
PLANE0
PARTITION2 PARTITION1 PARTITION0
PLANE3
PLANE2
PLANE1
PARTITION1
PLANE3 PLANE2
PARTITION0
PLANE1 PLANE0
PARTITION2 PARTITION1 PARTITION0
PLANE3 PLANE2 PLANE1
PARTITION1
PLANE3 PLANE2
PARTITION0
PLANE1 PLANE0
PARTITION3 PARTITION2 PARTITION1 PARTITION0
PLANE3
PLANE2
PLANE1
Figure Partition Configuration
Rev. 2.44
PLANE0
PLANE0
PLANE0
FUM00701
Start Status Check Partitions Desired Write 60H, Configuration Register Code Write 04H, Configuration Register Code Write 70H, Partition Address Read Status Register, Partition Address Command Sequence Error
Operation
Command
Comments
Write
<First cycle> Data=60H Addr=Partition Configuration Partition Register Code (see Table Configuration <Second cycle> Register Data= Addr=Partition Configuration Register Code (see Table Read Status Data=70H Register Addr=Within Partition Status Register Data Addr=Within Partition Check SR.4, Both 1=Command Sequence Error Read Code Data=90H Addr=Within Partition Partition Configuration Register Code Addr=0006H (see Table through Table Check DQ10-DQ8 Partition Configuration Register Code
Write Read
SR.4,5= Write 90H, Partition Address Read A0=0006H
Standby
Write
Correctly?
Read
Partition Configuration Register Complete STATUS CHECK PROCEDURE PARTITIONS BEFORE PARTITION CONFIGURATION REGISTER OPERATION Status Check Partitions Partition Address Partition Write 70H, Partition Address Read Status Register, Partition Address
Standby
Partition configuration register code read after partition configuration register operation. SR.5 SR.4 only cleared Clear Status Register command. error detected, clear status register before attempting retry other error recovery. After successful partition configuration register operation, device returns read array mode.
Operation Write Read
Command
Comments
SR.7= Another Partition Exist? Complete
Read Status Data=70H Register Addr=Within Partition Status Register Data Addr=Within Partition Check SR.7 1=WSM Ready 0=WSM Busy
Partition Address Next Partition
Standby
Figure Partition Configuration Register Flowchart
Rev. 2.44
FUM00701
Design Considerations Hardware Design Considerations 5.1.1 Control using RST#,
device will often used large memory arrays. SHARP provides three control input pins accommodate multiple memory connection. Three control input pins, RST#, provide for: Minimize power consumption memory Avoid data confliction data effectively these control input pins, access desired memory enabling through address decoder. Connect READ# control signal memory devices system. With these connections, selected memory devices activated deselected memory devices standby mode. RST# should connected system POWERGOOD signal prevent unintended writes during system power transitions. POWERGOOD should toggle (once VIL) during system reset.
5.1.3 Traces Printed Circuit Boards
product only used monitor power supply voltage used power supply except supply. Therefore, even when onboard writing flash memory system, required consider that supplies currents printed circuit boards. However, erase program operations with applying 12V±0.3V pin, used power supply pin. When executing these operations, trace widths layout should similar that supply flash memory cells current erasing programming. Adequate supply traces, decoupling capacitors placed adjacent component, will decrease spikes overshoots.
5.1.4 VCC, VPP, RST# Transitions
lower than VPPLK, lower than VLKO, RST# VIH, block erase, full chip erase, (page buffer) program program operation guaranteed. When error detected, status register bits SR.5 SR.4 (depending attempted operation) SR.3 will "1". RST# transitions during block erase, full chip erase, (page buffer) program program operation, status register SR.7 will remain until reset operation been completed. Then, attempted operation will aborted device will enter reset mode after completion reset sequence. RST# taken during block erase, full chip erase, (page buffer) program program operation, memory contents aborted location longer valid. Therefore, proper command must written again after RST# driven VIH. also, transitions lower than VLKO during block erase, full chip erase, (page buffer) program program operation, attempted operation will aborted memory contents aborted location longer valid. Write proper command again after transitions above VLKO.
5.1.2 Power Supply Decoupling
Flash memory's power switching characteristics require careful device decoupling eliminating noises system power lines. System designers should consider standby current levels (ICCS), active current levels (ICCR) transient peaks produced falling rising edges OE#. Transient current magnitudes depend device outputs' capacitive inductive loading. Two-line control proper decoupling capacitor selection will suppress these transient voltage peaks. Each flash device should have 0.1µF ceramic capacitor connected between each VCC, VCCQ between (when used supply). These high-frequency, inherently low-inductance capacitors should placed close possible package leads. Additionally, every eight devices, 4.7µF electrolytic capacitor should placed array's power supply connection between GND. These capacitors will overcome voltage slumps caused circuit board trace inductance.
Rev. 2.44
FUM00701
5.1.5 Power-Up/Down Protection
product designed offer protection against accidental block erase, full chip erase, (page buffer) program, program noises during power transitions. When device power-up, holding RST# until reached specified level stable. additional information, please refer AP-007-SW-E RST#, Electric Potential Switching Circuit. After power-up, product defaults mode descri
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