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High Performance Configurable 8-bit Microcontroller ver 3.01

CPU FEATURES

High Performance Configurable 8-bit Microcontroller ver 3.01
OVERVIEW
CPU FEATURES
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Scan test ready 1.3 GHz virtual clock frequency in a 0.35u technological process
Timers clocked by internal source Auto reload 8-bit timers Externally gated event counters
Full-duplex serial port
PERIPHERALS
DoCD debug unit
Processor execution control Run Halt Step into instruction Skip instruction Read-write all processor contents Program Counter (PC) Program Memory Internal (direct) Data Memory Special Function Registers (SFRs) External Data Memory Hardware execution breakpoints Program Memory Internal (direct) Data Memory Special Function Registers (SFRs) External Data Memory Hardware breakpoints activated at a certain Program address (PC) Address by any write into memory Address by any read from memory Address by write into memory a required data Address by read from memory a required data Three wire communication interface
Synchronous mode, fixed baud rate 8-bit asynchronous mode, fixed baud rate 9-bit asynchronous mode, fixed baud rate 9-bit asynchronous mode, variable baud rate
CONFIGURATION
The following parameters of the DR8051 core can be easy adjusted to requirements of dedicated application and technology. Configuration of the core can be prepared by effortless changing appropriate constants in package file. There is no need to change any parts of the code.
· Memory style · Program Memory type · Program Memory waitstates - Harward - von Neumann - synchronous - asynchronous - used (0-7) - unused - used - unused - synchronous - asynchronous - 64 kB - 16 MB - used (0-7) - unused subroutines location
· Program Memory writes · Internal Data Memory type · External Data Memory size · External Data Memory wait-states
Power Management Unit
Power management mode Switchback feature Stop mode
- used - unused - used - unused - used - unused
Interrupt Controller
2 priority levels 2 external interrupt sources 3 interrupt sources from peripherals
Four 8-bit I / O Ports
Bit addressable data direction for each line Read / write of single line and 8-bit group
Besides mentioned above parameters all available peripherals and external interrupts can be excluded from the core by changing appropriate constants in package file.
Two 16-bit timer / counters
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Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.
DELIVERABLES
Source code: VHDL Source Code or / and VERILOG Source Code or / and Encrypted, or plain text EDIF netlist VHDL & VERILOG test bench environment Active-HDL automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Technical documentation Installation notes HDL core specification Datasheet Synthesis scripts Example application Technical support IP Core implementation support 3 months maintenance
Single Design to Unlimited Designs
SYMBOL
clk reset ramdatai(7:0) ramdatao(7:0) ramaddr(7:0) ramoe ramwe sfrdatao(7:0) sfraddr(7:0) sfroe sfrwe prgdatao(7:0) prgdataz prgaddr(15:0) prgrd prgwr xramdatao(7:0) xramdataz xramaddr(23:0) xramrd xramwr docddatao docdclk stop pmm port0o(7:0) port1o(7:0) port2o(7:0) port3o(7:0)
sfrdatai(7:0)
prgdatai(7:0)
xramdatai(7:0)
Delivery the IP Core updates, minor and major versions changes Delivery the documentation updates Phone & email support
int0 int1 docddatai
LICENSING
Comprehensible and clearly defined licensing methods without royalty fees make using of IP Core easy and simply. Single Design license allows use IP Core in single FPGA bitstream and ASIC implementation. Unlimited Designs, One Year licenses allow use IP Core in unlimited number of FPGA bitstreams and ASIC implementations. In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited. There is no time restriction except One Year license where time of use is limited to 12 months. Single Design license for
VHDL, Verilog source code called HDL Source Encrypted, or plain text EDIF called Netlist
port0i(7:0) port1i(7:0) port2i(7:0) port3i(7:0) t0 gate0 t1 gate1 rxd0i
rxd0o txd0
One Year license for
Encrypted Netlist only
Unlimited Designs license for
HDL Source Netlist
Upgrade from
HDL Source to Netlist All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl
Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.
BLOCK DIAGRAM
clk reset prgdatai(7:0) prgdatao(7:0) prgdataz prgaddr(15:0) prgrd prgwr xramdatai(7:0) xramdatao(7:0) xramdataz xramaddr(23:0) xramrd xramwr ramdatai(7:0) ramdatao(7:0) ramaddr(7:0) ramoe ramwe sfrdatai(7:0) sfrdatao(7:0) sfraddr(7:0) sfroe sfrwe docddatai docddatao docdclk
Opcode Decoder ALU
ramdatao7:0 ramaddr7:0 ramoe ramwe sfrdatao7:0 sfraddr7:0
output output output output output output output output output output output output output output output output output output output output output output output output output output output output output output
Data bus for Internal Data Memory Internal Data Memory address bus Internal Data Memory output enable Internal Data Memory write enable Data bus for user SFRs User SFRs address bus User SFRs output enable User SFRs write enable Program Memory address bus Output data bus for Program Memory PRGDATA tri-state buffers control line Program Memory read Program Memory write Data bus for External Data Memory XDATA tri-state buffers control line External Data Memory address bus External Data Memory read External Data Memory write DoCD data output DoCD clock line Power management mode indicator Stop mode indicator Port 0 output Port 1 output Port 2 output Port 3 output Serial receiver output 0 Serial transmitter line 0 Serial receiver output 1 Serial transmitter line 1
Program Memory Interface
sfroe
Control Unit
sfrwe prgaddr15:0 prgdatao7:0
External Memory Interface
prgdataz
Interrupt Controller
int0 int1
prgrd prgwr xramdatao7:0 xramdataz xramaddr23:0 xramrd xramwr docddatao docdclk pmm stop port0o7:0 port1o7:0 port2o7:0 port3o7:0 rxd0o txd0 rxd1o txd1
Internal Data Memory Interface I / O Ports User SFR Interface
port0i(7:0) port1i(7:0) port2i(7:0) port3i(7:0) port0o(7:0) port1o(7:0) port2o(7:0) port3o(7:0)
DoCD Debug Unit
Power Management Unit
stop pmm
rxd0o rxd0i txd0
UART 0
Timers 0 & 1
t0 gate0 t1 gate1
PINS DESCRIPTION
clk reset ramdatai7:0 sfrdatai7:0 prgdatai7:0 xramdatai7:0 int0 int1 docddatai port0i7:0 port1i7:0 port2i7:0 port3i7:0 t0 gate0 t1 gate1 rxd0i
input input input input input input input input input input input input input input input input input input
DESCRIPTION
Global clock Global synchronous reset Data bus from Internal Data Memory Data bus from user SFRs Input data bus from Program Memory Data bus from External Data Memory External interrupt 0 line External interrupt 1 line DoCD data input Port 0 input Port 1 input Port 2 input Port 3 input Timer 0 clock line Timer 0 clock line gate control Timer 1 clock line Timer 1 clock line gate control Serial receiver input 0
UNITS SUMMARY
ALU - Arithmetic Logic Unit performs the arithmetic and logic operations during execution of an instruction. It contains accumulator (ACC), Program Status Word (PSW), (B) registers and related logic such as arithmetic unit, logic unit, multiplier and divider. Opcode Decoder - Performs an instruction opcode decoding and the control functions for all other blocks. Control Unit - Performs the core synchronization and data flow control. This module is directly connected to Opcode Decoder and manages execution of all microcontroller tasks. Program Memory Interface - Contains Program Counter (PC) and related logic. It performs the instructions code fetching. Program Memory can be also written. This feature allows usage of a small boot loader loading new
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All trademarks mentioned in this document are trademarks of their respective owners.
Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are trademarks of their respective owners.
http://www.DigitalCoreDesign.com http://www.dcd.pl
Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.
PERFORMANCE
The following tables give a survey about the Core area and performance in Programmable Logic Devices after Place & Route (CPU features and peripherals have been included):
Device ORCA 4E Speed grade -3 Fmax 45 MHz
Core performance in LATTICE® devices
Function 8-bit addition (immediate data) 8-bit addition (direct addressing) 8-bit addition (indirect addressing) 8-bit addition (register addressing) 8-bit subtraction (immediate data) 8-bit subtraction (direct addressing) 8-bit subtraction (indirect addressing) 8-bit subtraction (register addressing) 8-bit multiplication 8-bit division 16-bit addition 16-bit subtraction 16-bit multiplication 32-bit addition 32-bit subtraction 32-bit multiplication Average speed improvement: Improvement 7, 20 6, 00 6, 00 7, 20 7, 20 6, 00 6, 00 7, 20 10, 67 9, 60 7, 20 7, 64 9, 75 7, 20 7, 43 9, 04 7, 58
80C51 (12MHz)
80C310 (33MHz)
DR8051 (40MHz)
Area utilized by the each unit of DR8051 core in vendor specific technologies is summarized in table below.
Component CPU Interrupt Controller Power Management Unit I / O ports Timers UART0 Total area Area
LC / PFU FFs
CPU - consisted of ALU, Opcode Decoder, Control Unit, Program & Internal & External Memory Interfaces, User SFRs Interface
Core components area utilization
Dhrystone Benchmark Version 2.1 was used to measure Core performance. The following table gives a survey about the DR8051 performance in terms of Dhrystone / sec and VAX MIPS rating.
Device 80C51 80C310 DR8051 Target ORCA 4E Clock frequency 12 MHz 33 MHz 40 MHz Dhry / sec (VAX MIPS) 268 (0.153) 1550 (0.882) 6452 (3.672)
Core performance in terms of Dhrystones
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http://www.DigitalCoreDesign.com http://www.dcd.pl
Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.
The main features of each DR8051 family member have been summarized in table below. It gives a briefly member characterization helping user to select the most suitable IP Core for its application. User can specify its own peripheral set (including listed below and the others) and requests the core modifications.
Program Memory space Internal Data Memory space External Data Memory space External Data Memory Wait States Power Management Unit Interface for additional SFRs Program Memory Wait States
Architecture speed grade
Compare / Capture
Interrupt sources
Stack space size
Timer / Counters
Interrupt levels
Master I C Bus Controller 2 Slave I C Bus Controller
Design
DR8051CPU DR8051 DR8051XP
6.7 64k 256 256 16M 6.7 64k 256 256 16M 6.7 64k 256 256 16M
DR8051 family of High Performance Microcontroller Cores
All trademarks mentioned in this document are trademarks of their respective owners.
http://www.DigitalCoreDesign.com http://www.dcd.pl
Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.
Fixed Point Coprocessor Floating Point Coprocessor -
Data Pointers
Watchdog
CONTACTS
For any modification or special request please contact to Digital Core Design or local distributors. Headquarters: Wroclawska 94 41-902 Bytom, POLAND e-mail: iinffo@dcd.pll n o@dcd p tel. fax : +48 32 282 82 66 : +48 32 282 74 37
Field Office: Texas Research Park 14815 Omicron Dr. suite 100 San Antonio, TX 78245, USA e-mail: iinffoUS@dcd.pll n oUS@dcd p tel. fax : +1 210 422 8268 : +1 210 679 7511
Distributors: MTC - Micro Tech Components GmbH AM Reitweg 15 89407 Dillingen, GERMANY
MTC n o@m c de e-mail : MTCiinffo@mttc.de
tel. : +49 9071 7945-0 fax : +49 9071 7945-20 Territory: Germany, Austria, Switzerland
All trademarks mentioned in this document are trademarks of their respective owners.
http://www.DigitalCoreDesign.com http://www.dcd.pl
Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.